2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
9 #include <linux/init.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/sched.h>
15 #include <linux/module.h>
17 #include <asm/mmu_context.h>
18 #include <asm/system.h>
21 #include <asm/octeon/octeon.h>
23 #include "octeon_boot.h"
25 volatile unsigned long octeon_processor_boot = 0xff;
26 volatile unsigned long octeon_processor_sp;
27 volatile unsigned long octeon_processor_gp;
29 #ifdef CONFIG_HOTPLUG_CPU
30 static unsigned int InitTLBStart_addr;
33 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
35 const int coreid = cvmx_get_core_num();
38 /* Load the mailbox register to figure out what we're supposed to do */
39 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid));
41 /* Clear the mailbox to clear the interrupt */
42 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
44 if (action & SMP_CALL_FUNCTION)
45 smp_call_function_interrupt();
47 /* Check if we've been told to flush the icache */
48 if (action & SMP_ICACHE_FLUSH)
49 asm volatile ("synci 0($0)\n");
54 * Cause the function described by call_data to be executed on the passed
55 * cpu. When the function has finished, increment the finished field of
58 void octeon_send_ipi_single(int cpu, unsigned int action)
60 int coreid = cpu_logical_map(cpu);
62 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
65 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
68 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
73 for_each_cpu_mask(i, *mask)
74 octeon_send_ipi_single(i, action);
78 * Detect available CPUs, populate cpu_possible_map
80 static void octeon_smp_hotplug_setup(void)
82 #ifdef CONFIG_HOTPLUG_CPU
83 uint32_t labi_signature;
86 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
87 LABI_ADDR_IN_BOOTLOADER +
88 offsetof(struct linux_app_boot_info,
90 if (labi_signature != LABI_SIGNATURE)
91 pr_err("The bootloader version on this board is incorrect\n");
93 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
94 LABI_ADDR_IN_BOOTLOADER +
95 offsetof(struct linux_app_boot_info,
100 static void octeon_smp_setup(void)
102 const int coreid = cvmx_get_core_num();
105 int core_mask = octeon_get_boot_coremask();
106 #ifdef CONFIG_HOTPLUG_CPU
107 unsigned int num_cores = cvmx_octeon_num_cores();
110 /* The present CPUs are initially just the boot cpu (CPU 0). */
111 for (id = 0; id < NR_CPUS; id++) {
112 set_cpu_possible(id, id == 0);
113 set_cpu_present(id, id == 0);
116 __cpu_number_map[coreid] = 0;
117 __cpu_logical_map[0] = coreid;
119 /* The present CPUs get the lowest CPU numbers. */
121 for (id = 0; id < NR_CPUS; id++) {
122 if ((id != coreid) && (core_mask & (1 << id))) {
123 set_cpu_possible(cpus, true);
124 set_cpu_present(cpus, true);
125 __cpu_number_map[id] = cpus;
126 __cpu_logical_map[cpus] = id;
131 #ifdef CONFIG_HOTPLUG_CPU
133 * The possible CPUs are all those present on the chip. We
134 * will assign CPU numbers for possible cores as well. Cores
135 * are always consecutively numberd from 0.
137 for (id = 0; id < num_cores && id < NR_CPUS; id++) {
138 if (!(core_mask & (1 << id))) {
139 set_cpu_possible(cpus, true);
140 __cpu_number_map[id] = cpus;
141 __cpu_logical_map[cpus] = id;
147 octeon_smp_hotplug_setup();
151 * Firmware CPU startup hook
154 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
158 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
159 cpu_logical_map(cpu));
161 octeon_processor_sp = __KSTK_TOS(idle);
162 octeon_processor_gp = (unsigned long)(task_thread_info(idle));
163 octeon_processor_boot = cpu_logical_map(cpu);
167 while (octeon_processor_sp && count) {
168 /* Waiting for processor to get the SP and GP */
173 pr_err("Secondary boot timeout\n");
177 * After we've done initial boot, this function is called to allow the
178 * board code to clean up state, if needed
180 static void octeon_init_secondary(void)
182 const int coreid = cvmx_get_core_num();
183 union cvmx_ciu_intx_sum0 interrupt_enable;
185 #ifdef CONFIG_HOTPLUG_CPU
186 unsigned int cur_exception_base;
188 cur_exception_base = cvmx_read64_uint32(
189 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
190 LABI_ADDR_IN_BOOTLOADER +
191 offsetof(struct linux_app_boot_info,
192 cur_exception_base)));
193 /* cur_exception_base is incremented in bootloader after setting */
194 write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
196 octeon_check_cpu_bist();
197 octeon_init_cvmcount();
199 pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
201 /* Enable Mailbox interrupts to this core. These are the only
202 interrupts allowed on line 3 */
203 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
204 interrupt_enable.u64 = 0;
205 interrupt_enable.s.mbox = 0x3;
206 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
207 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
208 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
209 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
210 /* Enable core interrupt processing for 2,3 and 7 */
211 set_c0_status(0x8c01);
215 * Callout to firmware before smp_init
218 void octeon_prepare_cpus(unsigned int max_cpus)
220 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
221 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
222 "mailbox0", mailbox_interrupt)) {
223 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
225 if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,
226 "mailbox1", mailbox_interrupt)) {
227 panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
232 * Last chance for the board code to finish SMP initialization before
233 * the CPU is "online".
235 static void octeon_smp_finish(void)
237 #ifdef CONFIG_CAVIUM_GDB
239 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
240 to be not masked by this core so we know the signal is received by
242 asm volatile ("dmfc0 %0, $22\n"
243 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
246 octeon_user_io_init();
248 /* to generate the first CPU timer interrupt */
249 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
253 * Hook for after all CPUs are online
255 static void octeon_cpus_done(void)
257 #ifdef CONFIG_CAVIUM_GDB
259 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
260 to be not masked by this core so we know the signal is received by
262 asm volatile ("dmfc0 %0, $22\n"
263 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
267 #ifdef CONFIG_HOTPLUG_CPU
269 /* State of each CPU. */
270 DEFINE_PER_CPU(int, cpu_state);
272 extern void fixup_irqs(void);
274 static DEFINE_SPINLOCK(smp_reserve_lock);
276 static int octeon_cpu_disable(void)
278 unsigned int cpu = smp_processor_id();
283 spin_lock(&smp_reserve_lock);
285 cpu_clear(cpu, cpu_online_map);
286 cpu_clear(cpu, cpu_callin_map);
292 local_flush_tlb_all();
294 spin_unlock(&smp_reserve_lock);
299 static void octeon_cpu_die(unsigned int cpu)
301 int coreid = cpu_logical_map(cpu);
302 uint32_t avail_coremask;
303 struct cvmx_bootmem_named_block_desc *block_desc;
305 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
309 * This is a bit complicated strategics of getting/settig available
310 * cores mask, copied from bootloader
312 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
313 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
317 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
318 LABI_ADDR_IN_BOOTLOADER +
320 (struct linux_app_boot_info,
322 } else { /* alternative, already initialized */
324 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
325 block_desc->base_addr +
326 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
329 avail_coremask |= 1 << coreid;
331 /* Setting avail_coremask for bootoct binary */
333 cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
334 LABI_ADDR_IN_BOOTLOADER +
335 offsetof(struct linux_app_boot_info,
339 cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
340 block_desc->base_addr +
341 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
345 pr_info("Reset core %d. Available Coremask = %x\n", coreid,
347 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
348 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
353 int coreid = cvmx_get_core_num();
356 octeon_processor_boot = 0xff;
357 per_cpu(cpu_state, coreid) = CPU_DEAD;
359 while (1) /* core will be reset here */
363 extern void kernel_entry(unsigned long arg1, ...);
365 static void start_after_reset(void)
367 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
370 int octeon_update_boot_vector(unsigned int cpu)
373 int coreid = cpu_logical_map(cpu);
374 unsigned int avail_coremask;
375 struct cvmx_bootmem_named_block_desc *block_desc;
376 struct boot_init_vector *boot_vect =
377 (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
378 BOOTLOADER_BOOT_VECTOR);
380 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
384 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
385 LABI_ADDR_IN_BOOTLOADER +
386 offsetof(struct linux_app_boot_info,
388 } else { /* alternative, already initialized */
390 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
391 block_desc->base_addr +
392 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
395 if (!(avail_coremask & (1 << coreid))) {
396 /* core not available, assume, that catched by simple-executive */
397 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
398 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
401 boot_vect[coreid].app_start_func_addr =
402 (uint32_t) (unsigned long) start_after_reset;
403 boot_vect[coreid].code_addr = InitTLBStart_addr;
407 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
412 static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
413 unsigned long action, void *hcpu)
415 unsigned int cpu = (unsigned long)hcpu;
419 octeon_update_boot_vector(cpu);
422 pr_info("Cpu %d online\n", cpu);
431 static int __cpuinit register_cavium_notifier(void)
433 hotcpu_notifier(octeon_cpu_callback, 0);
436 late_initcall(register_cavium_notifier);
438 #endif /* CONFIG_HOTPLUG_CPU */
440 struct plat_smp_ops octeon_smp_ops = {
441 .send_ipi_single = octeon_send_ipi_single,
442 .send_ipi_mask = octeon_send_ipi_mask,
443 .init_secondary = octeon_init_secondary,
444 .smp_finish = octeon_smp_finish,
445 .cpus_done = octeon_cpus_done,
446 .boot_secondary = octeon_boot_secondary,
447 .smp_setup = octeon_smp_setup,
448 .prepare_cpus = octeon_prepare_cpus,
449 #ifdef CONFIG_HOTPLUG_CPU
450 .cpu_disable = octeon_cpu_disable,
451 .cpu_die = octeon_cpu_die,