2 * BRIEF MODULE DESCRIPTION
3 * Au1xx0 Power Management routines.
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Some of the routines are right out of init/main.c, whose
9 * copyrights apply here.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/init.h>
34 #include <linux/sysctl.h>
35 #include <linux/jiffies.h>
37 #include <asm/uaccess.h>
38 #include <asm/mach-au1x00/au1000.h>
39 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
46 * We need to save/restore a bunch of core registers that are
47 * either volatile or reset to some state across a processor sleep.
48 * If reading a register doesn't provide a proper result for a
49 * later restore, we have to provide a function for loading that
50 * register and save a copy.
52 * We only have to save/restore registers that aren't otherwise
53 * done as part of a driver pm_* function.
55 static unsigned int sleep_uart0_inten;
56 static unsigned int sleep_uart0_fifoctl;
57 static unsigned int sleep_uart0_linectl;
58 static unsigned int sleep_uart0_clkdiv;
59 static unsigned int sleep_uart0_enable;
60 static unsigned int sleep_usb[2];
61 static unsigned int sleep_sys_clocks[5];
62 static unsigned int sleep_sys_pinfunc;
63 static unsigned int sleep_static_memctlr[4][3];
66 static void save_core_regs(void)
68 extern void save_au1xxx_intctl(void);
69 extern void pm_eth0_shutdown(void);
72 * Do the serial ports.....these really should be a pm_*
73 * registered function by the driver......but of course the
74 * standard serial driver doesn't understand our Au1xxx
77 sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
78 sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
79 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
80 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
81 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
84 #ifndef CONFIG_SOC_AU1200
85 /* Shutdown USB host/device. */
86 sleep_usb[0] = au_readl(USB_HOST_CONFIG);
88 /* There appears to be some undocumented reset register.... */
89 au_writel(0, 0xb0100004);
91 au_writel(0, USB_HOST_CONFIG);
94 sleep_usb[1] = au_readl(USBD_ENABLE);
95 au_writel(0, USBD_ENABLE);
100 /* enable access to OTG mmio so we can save OTG CAP/MUX.
101 * FIXME: write an OTG driver and move this stuff there!
103 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
105 sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
106 sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
109 /* Clocks and PLLs. */
110 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
111 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
112 sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
113 sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
114 sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
117 sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
119 /* Save the static memory controller configuration. */
120 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
121 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
122 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
123 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
124 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
125 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
126 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
127 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
128 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
129 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
130 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
131 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
133 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
134 au1xxx_dbdma_suspend();
138 static void restore_core_regs(void)
140 /* restore clock configuration. Writing CPUPLL last will
141 * stall a bit and stabilize other clocks (unless this is
142 * one of those Au1000 with a write-only PLL, where we dont
143 * have a valid value)
145 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
146 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
147 au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
148 au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
149 if (!au1xxx_cpu_has_pll_wo())
150 au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
153 au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
156 #ifndef CONFIG_SOC_AU1200
157 au_writel(sleep_usb[0], USB_HOST_CONFIG);
158 au_writel(sleep_usb[1], USBD_ENABLE);
161 /* enable accces to OTG memory */
162 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
165 /* restore OTG caps and port mux. */
166 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
168 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
172 /* Restore the static memory controller configuration. */
173 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
174 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
175 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
176 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
177 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
178 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
179 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
180 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
181 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
182 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
183 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
184 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
187 * Enable the UART if it was enabled before sleep.
188 * I guess I should define module control bits........
190 if (sleep_uart0_enable & 0x02) {
191 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
192 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
193 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
194 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
195 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
196 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
197 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
200 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
201 au1xxx_dbdma_resume();
208 au1xxx_save_and_sleep();
212 #endif /* CONFIG_PM */