2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
30 #include <asm/processor.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/byteorder.h>
36 static DEFINE_SPINLOCK(hose_spinlock);
39 /* XXX kill that some day ... */
40 static int global_phb_number; /* Global phb counter */
42 /* ISA Memory physical address */
43 resource_size_t isa_mem_base;
45 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
46 unsigned int pci_flags;
48 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
50 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
52 pci_dma_ops = dma_ops;
55 struct dma_map_ops *get_pci_dma_ops(void)
59 EXPORT_SYMBOL(get_pci_dma_ops);
61 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
63 return dma_set_mask(&dev->dev, mask);
66 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
70 rc = dma_set_mask(&dev->dev, mask);
71 dev->dev.coherent_dma_mask = dev->dma_mask;
76 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
78 struct pci_controller *phb;
80 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
83 spin_lock(&hose_spinlock);
84 phb->global_number = global_phb_number++;
85 list_add_tail(&phb->list_node, &hose_list);
86 spin_unlock(&hose_spinlock);
88 phb->is_dynamic = mem_init_done;
92 void pcibios_free_controller(struct pci_controller *phb)
94 spin_lock(&hose_spinlock);
95 list_del(&phb->list_node);
96 spin_unlock(&hose_spinlock);
102 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
104 return hose->io_resource.end - hose->io_resource.start + 1;
107 int pcibios_vaddr_is_ioport(void __iomem *address)
110 struct pci_controller *hose;
111 resource_size_t size;
113 spin_lock(&hose_spinlock);
114 list_for_each_entry(hose, &hose_list, list_node) {
115 size = pcibios_io_size(hose);
116 if (address >= hose->io_base_virt &&
117 address < (hose->io_base_virt + size)) {
122 spin_unlock(&hose_spinlock);
126 unsigned long pci_address_to_pio(phys_addr_t address)
128 struct pci_controller *hose;
129 resource_size_t size;
130 unsigned long ret = ~0;
132 spin_lock(&hose_spinlock);
133 list_for_each_entry(hose, &hose_list, list_node) {
134 size = pcibios_io_size(hose);
135 if (address >= hose->io_base_phys &&
136 address < (hose->io_base_phys + size)) {
138 (unsigned long)hose->io_base_virt - _IO_BASE;
139 ret = base + (address - hose->io_base_phys);
143 spin_unlock(&hose_spinlock);
147 EXPORT_SYMBOL_GPL(pci_address_to_pio);
150 * Return the domain number for this bus.
152 int pci_domain_nr(struct pci_bus *bus)
154 struct pci_controller *hose = pci_bus_to_host(bus);
156 return hose->global_number;
158 EXPORT_SYMBOL(pci_domain_nr);
160 /* This routine is meant to be used early during boot, when the
161 * PCI bus numbers have not yet been assigned, and you need to
162 * issue PCI config cycles to an OF device.
163 * It could also be used to "fix" RTAS config cycles if you want
164 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
167 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
170 struct pci_controller *hose, *tmp;
171 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
172 if (hose->dn == node)
179 static ssize_t pci_show_devspec(struct device *dev,
180 struct device_attribute *attr, char *buf)
182 struct pci_dev *pdev;
183 struct device_node *np;
185 pdev = to_pci_dev(dev);
186 np = pci_device_to_OF_node(pdev);
187 if (np == NULL || np->full_name == NULL)
189 return sprintf(buf, "%s", np->full_name);
191 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
193 /* Add sysfs properties */
194 int pcibios_add_platform_entries(struct pci_dev *pdev)
196 return device_create_file(&pdev->dev, &dev_attr_devspec);
199 char __devinit *pcibios_setup(char *str)
205 * Reads the interrupt pin to determine if interrupt is use by card.
206 * If the interrupt is used, then gets the interrupt line from the
207 * openfirmware and sets it in the pci_dev and pci_config line.
209 int pci_read_irq_line(struct pci_dev *pci_dev)
214 /* The current device-tree that iSeries generates from the HV
215 * PCI informations doesn't contain proper interrupt routing,
216 * and all the fallback would do is print out crap, so we
217 * don't attempt to resolve the interrupts here at all, some
218 * iSeries specific fixup does it.
220 * In the long run, we will hopefully fix the generated device-tree
223 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
226 memset(&oirq, 0xff, sizeof(oirq));
228 /* Try to get a mapping from the device-tree */
229 if (of_irq_map_pci(pci_dev, &oirq)) {
232 /* If that fails, lets fallback to what is in the config
233 * space and map that through the default controller. We
234 * also set the type to level low since that's what PCI
235 * interrupts are. If your platform does differently, then
236 * either provide a proper interrupt tree or don't use this
239 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
243 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
244 line == 0xff || line == 0) {
247 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
250 virq = irq_create_mapping(NULL, line);
252 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
254 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
255 oirq.size, oirq.specifier[0], oirq.specifier[1],
256 oirq.controller ? oirq.controller->full_name :
259 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
262 if (virq == NO_IRQ) {
263 pr_debug(" Failed to map !\n");
267 pr_debug(" Mapped to linux irq %d\n", virq);
273 EXPORT_SYMBOL(pci_read_irq_line);
276 * Platform support for /proc/bus/pci/X/Y mmap()s,
277 * modelled on the sparc64 implementation by Dave Miller.
282 * Adjust vm_pgoff of VMA such that it is the physical page offset
283 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
285 * Basically, the user finds the base address for his device which he wishes
286 * to mmap. They read the 32-bit value from the config space base register,
287 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
288 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
290 * Returns negative error code on failure, zero on success.
292 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
293 resource_size_t *offset,
294 enum pci_mmap_state mmap_state)
296 struct pci_controller *hose = pci_bus_to_host(dev->bus);
297 unsigned long io_offset = 0;
301 return NULL; /* should never happen */
303 /* If memory, add on the PCI bridge address offset */
304 if (mmap_state == pci_mmap_mem) {
305 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
306 *offset += hose->pci_mem_offset;
308 res_bit = IORESOURCE_MEM;
310 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
311 *offset += io_offset;
312 res_bit = IORESOURCE_IO;
316 * Check that the offset requested corresponds to one of the
317 * resources of the device.
319 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
320 struct resource *rp = &dev->resource[i];
321 int flags = rp->flags;
323 /* treat ROM as memory (should be already) */
324 if (i == PCI_ROM_RESOURCE)
325 flags |= IORESOURCE_MEM;
327 /* Active and same type? */
328 if ((flags & res_bit) == 0)
331 /* In the range of this resource? */
332 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
335 /* found it! construct the final physical address */
336 if (mmap_state == pci_mmap_io)
337 *offset += hose->io_base_phys - io_offset;
345 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
348 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
350 enum pci_mmap_state mmap_state,
353 pgprot_t prot = protection;
355 /* Write combine is always 0 on non-memory space mappings. On
356 * memory space, if the user didn't pass 1, we check for a
357 * "prefetchable" resource. This is a bit hackish, but we use
358 * this to workaround the inability of /sysfs to provide a write
361 if (mmap_state != pci_mmap_mem)
363 else if (write_combine == 0) {
364 if (rp->flags & IORESOURCE_PREFETCH)
368 return pgprot_noncached(prot);
372 * This one is used by /dev/mem and fbdev who have no clue about the
373 * PCI device, it tries to find the PCI device first and calls the
376 pgprot_t pci_phys_mem_access_prot(struct file *file,
381 struct pci_dev *pdev = NULL;
382 struct resource *found = NULL;
383 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
386 if (page_is_ram(pfn))
389 prot = pgprot_noncached(prot);
390 for_each_pci_dev(pdev) {
391 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
392 struct resource *rp = &pdev->resource[i];
393 int flags = rp->flags;
395 /* Active and same type? */
396 if ((flags & IORESOURCE_MEM) == 0)
398 /* In the range of this resource? */
399 if (offset < (rp->start & PAGE_MASK) ||
409 if (found->flags & IORESOURCE_PREFETCH)
410 prot = pgprot_noncached_wc(prot);
414 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
415 (unsigned long long)offset, pgprot_val(prot));
421 * Perform the actual remap of the pages for a PCI device mapping, as
422 * appropriate for this architecture. The region in the process to map
423 * is described by vm_start and vm_end members of VMA, the base physical
424 * address is found in vm_pgoff.
425 * The pci device structure is provided so that architectures may make mapping
426 * decisions on a per-device or per-bus basis.
428 * Returns a negative error code on failure, zero on success.
430 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
431 enum pci_mmap_state mmap_state, int write_combine)
433 resource_size_t offset =
434 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
438 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
442 vma->vm_pgoff = offset >> PAGE_SHIFT;
443 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
445 mmap_state, write_combine);
447 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
448 vma->vm_end - vma->vm_start, vma->vm_page_prot);
453 /* This provides legacy IO read access on a bus */
454 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
456 unsigned long offset;
457 struct pci_controller *hose = pci_bus_to_host(bus);
458 struct resource *rp = &hose->io_resource;
461 /* Check if port can be supported by that bus. We only check
462 * the ranges of the PHB though, not the bus itself as the rules
463 * for forwarding legacy cycles down bridges are not our problem
464 * here. So if the host bridge supports it, we do it.
466 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
469 if (!(rp->flags & IORESOURCE_IO))
471 if (offset < rp->start || (offset + size) > rp->end)
473 addr = hose->io_base_virt + port;
477 *((u8 *)val) = in_8(addr);
482 *((u16 *)val) = in_le16(addr);
487 *((u32 *)val) = in_le32(addr);
493 /* This provides legacy IO write access on a bus */
494 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
496 unsigned long offset;
497 struct pci_controller *hose = pci_bus_to_host(bus);
498 struct resource *rp = &hose->io_resource;
501 /* Check if port can be supported by that bus. We only check
502 * the ranges of the PHB though, not the bus itself as the rules
503 * for forwarding legacy cycles down bridges are not our problem
504 * here. So if the host bridge supports it, we do it.
506 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
509 if (!(rp->flags & IORESOURCE_IO))
511 if (offset < rp->start || (offset + size) > rp->end)
513 addr = hose->io_base_virt + port;
515 /* WARNING: The generic code is idiotic. It gets passed a pointer
516 * to what can be a 1, 2 or 4 byte quantity and always reads that
517 * as a u32, which means that we have to correct the location of
518 * the data read within those 32 bits for size 1 and 2
522 out_8(addr, val >> 24);
527 out_le16(addr, val >> 16);
538 /* This provides legacy IO or memory mmap access on a bus */
539 int pci_mmap_legacy_page_range(struct pci_bus *bus,
540 struct vm_area_struct *vma,
541 enum pci_mmap_state mmap_state)
543 struct pci_controller *hose = pci_bus_to_host(bus);
544 resource_size_t offset =
545 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
546 resource_size_t size = vma->vm_end - vma->vm_start;
549 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
550 pci_domain_nr(bus), bus->number,
551 mmap_state == pci_mmap_mem ? "MEM" : "IO",
552 (unsigned long long)offset,
553 (unsigned long long)(offset + size - 1));
555 if (mmap_state == pci_mmap_mem) {
558 * Because X is lame and can fail starting if it gets an error
559 * trying to mmap legacy_mem (instead of just moving on without
560 * legacy memory access) we fake it here by giving it anonymous
561 * memory, effectively behaving just like /dev/zero
563 if ((offset + size) > hose->isa_mem_size) {
566 "Process %s (pid:%d) mapped non-existing PCI"
567 "legacy memory for 0%04x:%02x\n",
568 current->comm, current->pid, pci_domain_nr(bus),
571 if (vma->vm_flags & VM_SHARED)
572 return shmem_zero_setup(vma);
575 offset += hose->isa_mem_phys;
577 unsigned long io_offset = (unsigned long)hose->io_base_virt - \
579 unsigned long roffset = offset + io_offset;
580 rp = &hose->io_resource;
581 if (!(rp->flags & IORESOURCE_IO))
583 if (roffset < rp->start || (roffset + size) > rp->end)
585 offset += hose->io_base_phys;
587 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
589 vma->vm_pgoff = offset >> PAGE_SHIFT;
590 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
591 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
592 vma->vm_end - vma->vm_start,
596 void pci_resource_to_user(const struct pci_dev *dev, int bar,
597 const struct resource *rsrc,
598 resource_size_t *start, resource_size_t *end)
600 struct pci_controller *hose = pci_bus_to_host(dev->bus);
601 resource_size_t offset = 0;
606 if (rsrc->flags & IORESOURCE_IO)
607 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
609 /* We pass a fully fixed up address to userland for MMIO instead of
610 * a BAR value because X is lame and expects to be able to use that
611 * to pass to /dev/mem !
613 * That means that we'll have potentially 64 bits values where some
614 * userland apps only expect 32 (like X itself since it thinks only
615 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
618 * Hopefully, the sysfs insterface is immune to that gunk. Once X
619 * has been fixed (and the fix spread enough), we can re-enable the
620 * 2 lines below and pass down a BAR value to userland. In that case
621 * we'll also have to re-enable the matching code in
622 * __pci_mmap_make_offset().
627 else if (rsrc->flags & IORESOURCE_MEM)
628 offset = hose->pci_mem_offset;
631 *start = rsrc->start - offset;
632 *end = rsrc->end - offset;
636 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
637 * @hose: newly allocated pci_controller to be setup
638 * @dev: device node of the host bridge
639 * @primary: set if primary bus (32 bits only, soon to be deprecated)
641 * This function will parse the "ranges" property of a PCI host bridge device
642 * node and setup the resource mapping of a pci controller based on its
645 * Life would be boring if it wasn't for a few issues that we have to deal
648 * - We can only cope with one IO space range and up to 3 Memory space
649 * ranges. However, some machines (thanks Apple !) tend to split their
650 * space into lots of small contiguous ranges. So we have to coalesce.
652 * - We can only cope with all memory ranges having the same offset
653 * between CPU addresses and PCI addresses. Unfortunately, some bridges
654 * are setup for a large 1:1 mapping along with a small "window" which
655 * maps PCI address 0 to some arbitrary high address of the CPU space in
656 * order to give access to the ISA memory hole.
657 * The way out of here that I've chosen for now is to always set the
658 * offset based on the first resource found, then override it if we
659 * have a different offset and the previous was set by an ISA hole.
661 * - Some busses have IO space not starting at 0, which causes trouble with
662 * the way we do our IO resource renumbering. The code somewhat deals with
663 * it for 64 bits but I would expect problems on 32 bits.
665 * - Some 32 bits platforms such as 4xx can have physical space larger than
666 * 32 bits so we need to use 64 bits values for the parsing
668 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
669 struct device_node *dev,
674 int pna = of_n_addr_cells(dev);
676 int memno = 0, isa_hole = -1;
678 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
679 unsigned long long isa_mb = 0;
680 struct resource *res;
682 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
683 dev->full_name, primary ? "(primary)" : "");
685 /* Get ranges property */
686 ranges = of_get_property(dev, "ranges", &rlen);
691 pr_debug("Parsing ranges property...\n");
692 while ((rlen -= np * 4) >= 0) {
693 /* Read next ranges element */
694 pci_space = ranges[0];
695 pci_addr = of_read_number(ranges + 1, 2);
696 cpu_addr = of_translate_address(dev, ranges + 3);
697 size = of_read_number(ranges + pna + 3, 2);
699 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
700 "cpu_addr:0x%016llx size:0x%016llx\n",
701 pci_space, pci_addr, cpu_addr, size);
705 /* If we failed translation or got a zero-sized region
706 * (some FW try to feed us with non sensical zero sized regions
707 * such as power3 which look like some kind of attempt
708 * at exposing the VGA memory hole)
710 if (cpu_addr == OF_BAD_ADDR || size == 0)
713 /* Now consume following elements while they are contiguous */
714 for (; rlen >= np * sizeof(u32);
715 ranges += np, rlen -= np * 4) {
716 if (ranges[0] != pci_space)
718 pci_next = of_read_number(ranges + 1, 2);
719 cpu_next = of_translate_address(dev, ranges + 3);
720 if (pci_next != pci_addr + size ||
721 cpu_next != cpu_addr + size)
723 size += of_read_number(ranges + pna + 3, 2);
726 /* Act based on address space type */
728 switch ((pci_space >> 24) & 0x3) {
729 case 1: /* PCI IO space */
731 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
732 cpu_addr, cpu_addr + size - 1, pci_addr);
734 /* We support only one IO range */
735 if (hose->pci_io_size) {
737 " \\--> Skipped (too many) !\n");
740 /* On 32 bits, limit I/O space to 16MB */
741 if (size > 0x01000000)
744 /* 32 bits needs to map IOs here */
745 hose->io_base_virt = ioremap(cpu_addr, size);
747 /* Expect trouble if pci_addr is not 0 */
750 (unsigned long)hose->io_base_virt;
751 /* pci_io_size and io_base_phys always represent IO
752 * space starting at 0 so we factor in pci_addr
754 hose->pci_io_size = pci_addr + size;
755 hose->io_base_phys = cpu_addr - pci_addr;
758 res = &hose->io_resource;
759 res->flags = IORESOURCE_IO;
760 res->start = pci_addr;
762 case 2: /* PCI Memory space */
763 case 3: /* PCI 64 bits Memory space */
765 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
766 cpu_addr, cpu_addr + size - 1, pci_addr,
767 (pci_space & 0x40000000) ? "Prefetch" : "");
769 /* We support only 3 memory ranges */
772 " \\--> Skipped (too many) !\n");
775 /* Handles ISA memory hole space here */
779 if (primary || isa_mem_base == 0)
780 isa_mem_base = cpu_addr;
781 hose->isa_mem_phys = cpu_addr;
782 hose->isa_mem_size = size;
785 /* We get the PCI/Mem offset from the first range or
786 * the, current one if the offset came from an ISA
787 * hole. If they don't match, bugger.
790 (isa_hole >= 0 && pci_addr != 0 &&
791 hose->pci_mem_offset == isa_mb))
792 hose->pci_mem_offset = cpu_addr - pci_addr;
793 else if (pci_addr != 0 &&
794 hose->pci_mem_offset != cpu_addr - pci_addr) {
796 " \\--> Skipped (offset mismatch) !\n");
801 res = &hose->mem_resources[memno++];
802 res->flags = IORESOURCE_MEM;
803 if (pci_space & 0x40000000)
804 res->flags |= IORESOURCE_PREFETCH;
805 res->start = cpu_addr;
809 res->name = dev->full_name;
810 res->end = res->start + size - 1;
817 /* If there's an ISA hole and the pci_mem_offset is -not- matching
818 * the ISA hole offset, then we need to remove the ISA hole from
819 * the resource list for that brige
821 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
822 unsigned int next = isa_hole + 1;
823 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
825 memmove(&hose->mem_resources[isa_hole],
826 &hose->mem_resources[next],
827 sizeof(struct resource) * (memno - next));
828 hose->mem_resources[--memno].flags = 0;
832 /* Decide whether to display the domain number in /proc */
833 int pci_proc_domain(struct pci_bus *bus)
835 struct pci_controller *hose = pci_bus_to_host(bus);
837 if (!(pci_flags & PCI_ENABLE_PROC_DOMAINS))
839 if (pci_flags & PCI_COMPAT_DOMAIN_0)
840 return hose->global_number != 0;
844 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
845 struct resource *res)
847 resource_size_t offset = 0, mask = (resource_size_t)-1;
848 struct pci_controller *hose = pci_bus_to_host(dev->bus);
852 if (res->flags & IORESOURCE_IO) {
853 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
855 } else if (res->flags & IORESOURCE_MEM)
856 offset = hose->pci_mem_offset;
858 region->start = (res->start - offset) & mask;
859 region->end = (res->end - offset) & mask;
861 EXPORT_SYMBOL(pcibios_resource_to_bus);
863 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
864 struct pci_bus_region *region)
866 resource_size_t offset = 0, mask = (resource_size_t)-1;
867 struct pci_controller *hose = pci_bus_to_host(dev->bus);
871 if (res->flags & IORESOURCE_IO) {
872 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
874 } else if (res->flags & IORESOURCE_MEM)
875 offset = hose->pci_mem_offset;
876 res->start = (region->start + offset) & mask;
877 res->end = (region->end + offset) & mask;
879 EXPORT_SYMBOL(pcibios_bus_to_resource);
881 /* Fixup a bus resource into a linux resource */
882 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
884 struct pci_controller *hose = pci_bus_to_host(dev->bus);
885 resource_size_t offset = 0, mask = (resource_size_t)-1;
887 if (res->flags & IORESOURCE_IO) {
888 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
890 } else if (res->flags & IORESOURCE_MEM)
891 offset = hose->pci_mem_offset;
893 res->start = (res->start + offset) & mask;
894 res->end = (res->end + offset) & mask;
897 /* This header fixup will do the resource fixup for all devices as they are
898 * probed, but not for bridge ranges
900 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
902 struct pci_controller *hose = pci_bus_to_host(dev->bus);
906 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
910 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
911 struct resource *res = dev->resource + i;
914 /* On platforms that have PCI_PROBE_ONLY set, we don't
915 * consider 0 as an unassigned BAR value. It's technically
916 * a valid value, but linux doesn't like it... so when we can
917 * re-assign things, we do so, but if we can't, we keep it
918 * around and hope for the best...
920 if (res->start == 0 && !(pci_flags & PCI_PROBE_ONLY)) {
921 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
924 (unsigned long long)res->start,
925 (unsigned long long)res->end,
926 (unsigned int)res->flags);
927 res->end -= res->start;
929 res->flags |= IORESOURCE_UNSET;
933 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
935 (unsigned long long)res->start,\
936 (unsigned long long)res->end,
937 (unsigned int)res->flags);
939 fixup_resource(res, dev);
941 pr_debug("PCI:%s %016llx-%016llx\n",
943 (unsigned long long)res->start,
944 (unsigned long long)res->end);
947 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
949 /* This function tries to figure out if a bridge resource has been initialized
950 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
951 * things go more smoothly when it gets it right. It should covers cases such
952 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
954 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
955 struct resource *res)
957 struct pci_controller *hose = pci_bus_to_host(bus);
958 struct pci_dev *dev = bus->self;
959 resource_size_t offset;
963 /* We don't do anything if PCI_PROBE_ONLY is set */
964 if (pci_flags & PCI_PROBE_ONLY)
967 /* Job is a bit different between memory and IO */
968 if (res->flags & IORESOURCE_MEM) {
969 /* If the BAR is non-0 (res != pci_mem_offset) then it's
970 * probably been initialized by somebody
972 if (res->start != hose->pci_mem_offset)
975 /* The BAR is 0, let's check if memory decoding is enabled on
976 * the bridge. If not, we consider it unassigned
978 pci_read_config_word(dev, PCI_COMMAND, &command);
979 if ((command & PCI_COMMAND_MEMORY) == 0)
982 /* Memory decoding is enabled and the BAR is 0. If any of
983 * the bridge resources covers that starting address (0 then
984 * it's good enough for us for memory
986 for (i = 0; i < 3; i++) {
987 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
988 hose->mem_resources[i].start == hose->pci_mem_offset)
992 /* Well, it starts at 0 and we know it will collide so we may as
993 * well consider it as unassigned. That covers the Apple case.
997 /* If the BAR is non-0, then we consider it assigned */
998 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
999 if (((res->start - offset) & 0xfffffffful) != 0)
1002 /* Here, we are a bit different than memory as typically IO
1003 * space starting at low addresses -is- valid. What we do
1004 * instead if that we consider as unassigned anything that
1005 * doesn't have IO enabled in the PCI command register,
1008 pci_read_config_word(dev, PCI_COMMAND, &command);
1009 if (command & PCI_COMMAND_IO)
1012 /* It's starting at 0 and IO is disabled in the bridge, consider
1019 /* Fixup resources of a PCI<->PCI bridge */
1020 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1022 struct resource *res;
1025 struct pci_dev *dev = bus->self;
1027 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1028 res = bus->resource[i];
1033 if (i >= 3 && bus->self->transparent)
1036 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1038 (unsigned long long)res->start,\
1039 (unsigned long long)res->end,
1040 (unsigned int)res->flags);
1043 fixup_resource(res, dev);
1045 /* Try to detect uninitialized P2P bridge resources,
1046 * and clear them out so they get re-assigned later
1048 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1050 pr_debug("PCI:%s (unassigned)\n",
1053 pr_debug("PCI:%s %016llx-%016llx\n",
1055 (unsigned long long)res->start,
1056 (unsigned long long)res->end);
1061 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1063 /* Fix up the bus resources for P2P bridges */
1064 if (bus->self != NULL)
1065 pcibios_fixup_bridge(bus);
1068 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1070 struct pci_dev *dev;
1072 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1073 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1075 list_for_each_entry(dev, &bus->devices, bus_list) {
1076 struct dev_archdata *sd = &dev->dev.archdata;
1078 /* Setup OF node pointer in archdata */
1079 sd->of_node = pci_device_to_OF_node(dev);
1081 /* Fixup NUMA node as it may not be setup yet by the generic
1082 * code and is needed by the DMA init
1084 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1086 /* Hook up default DMA ops */
1087 sd->dma_ops = pci_dma_ops;
1088 sd->dma_data = (void *)PCI_DRAM_OFFSET;
1090 /* Read default IRQs and fixup if necessary */
1091 pci_read_irq_line(dev);
1095 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1097 /* When called from the generic PCI probe, read PCI<->PCI bridge
1098 * bases. This is -not- called when generating the PCI tree from
1099 * the OF device-tree.
1101 if (bus->self != NULL)
1102 pci_read_bridge_bases(bus);
1104 /* Now fixup the bus bus */
1105 pcibios_setup_bus_self(bus);
1107 /* Now fixup devices on that bus */
1108 pcibios_setup_bus_devices(bus);
1110 EXPORT_SYMBOL(pcibios_fixup_bus);
1112 static int skip_isa_ioresource_align(struct pci_dev *dev)
1114 if ((pci_flags & PCI_CAN_SKIP_ISA_ALIGN) &&
1115 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1121 * We need to avoid collisions with `mirrored' VGA ports
1122 * and other strange ISA hardware, so we always want the
1123 * addresses to be allocated in the 0x000-0x0ff region
1126 * Why? Because some silly external IO cards only decode
1127 * the low 10 bits of the IO address. The 0x00-0xff region
1128 * is reserved for motherboard devices that decode all 16
1129 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1130 * but we want to try to avoid allocating at 0x2900-0x2bff
1131 * which might have be mirrored at 0x0100-0x03ff..
1133 void pcibios_align_resource(void *data, struct resource *res,
1134 resource_size_t size, resource_size_t align)
1136 struct pci_dev *dev = data;
1138 if (res->flags & IORESOURCE_IO) {
1139 resource_size_t start = res->start;
1141 if (skip_isa_ioresource_align(dev))
1143 if (start & 0x300) {
1144 start = (start + 0x3ff) & ~0x3ff;
1149 EXPORT_SYMBOL(pcibios_align_resource);
1152 * Reparent resource children of pr that conflict with res
1153 * under res, and make res replace those children.
1155 static int __init reparent_resources(struct resource *parent,
1156 struct resource *res)
1158 struct resource *p, **pp;
1159 struct resource **firstpp = NULL;
1161 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1162 if (p->end < res->start)
1164 if (res->end < p->start)
1166 if (p->start < res->start || p->end > res->end)
1167 return -1; /* not completely contained */
1168 if (firstpp == NULL)
1171 if (firstpp == NULL)
1172 return -1; /* didn't find any conflicting entries? */
1173 res->parent = parent;
1174 res->child = *firstpp;
1178 for (p = res->child; p != NULL; p = p->sibling) {
1180 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1182 (unsigned long long)p->start,
1183 (unsigned long long)p->end, res->name);
1189 * Handle resources of PCI devices. If the world were perfect, we could
1190 * just allocate all the resource regions and do nothing more. It isn't.
1191 * On the other hand, we cannot just re-allocate all devices, as it would
1192 * require us to know lots of host bridge internals. So we attempt to
1193 * keep as much of the original configuration as possible, but tweak it
1194 * when it's found to be wrong.
1196 * Known BIOS problems we have to work around:
1197 * - I/O or memory regions not configured
1198 * - regions configured, but not enabled in the command register
1199 * - bogus I/O addresses above 64K used
1200 * - expansion ROMs left enabled (this may sound harmless, but given
1201 * the fact the PCI specs explicitly allow address decoders to be
1202 * shared between expansion ROMs and other resource regions, it's
1203 * at least dangerous)
1206 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1207 * This gives us fixed barriers on where we can allocate.
1208 * (2) Allocate resources for all enabled devices. If there is
1209 * a collision, just mark the resource as unallocated. Also
1210 * disable expansion ROMs during this step.
1211 * (3) Try to allocate resources for disabled devices. If the
1212 * resources were assigned correctly, everything goes well,
1213 * if they weren't, they won't disturb allocation of other
1215 * (4) Assign new addresses to resources which were either
1216 * not configured at all or misconfigured. If explicitly
1217 * requested by the user, configure expansion ROM address
1221 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1225 struct resource *res, *pr;
1227 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1228 pci_domain_nr(bus), bus->number);
1230 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1231 res = bus->resource[i];
1232 if (!res || !res->flags
1233 || res->start > res->end || res->parent)
1235 if (bus->parent == NULL)
1236 pr = (res->flags & IORESOURCE_IO) ?
1237 &ioport_resource : &iomem_resource;
1239 /* Don't bother with non-root busses when
1240 * re-assigning all resources. We clear the
1241 * resource flags as if they were colliding
1242 * and as such ensure proper re-allocation
1245 if (pci_flags & PCI_REASSIGN_ALL_RSRC)
1246 goto clear_resource;
1247 pr = pci_find_parent_resource(bus->self, res);
1249 /* this happens when the generic PCI
1250 * code (wrongly) decides that this
1251 * bridge is transparent -- paulus
1257 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1258 "[0x%x], parent %p (%s)\n",
1259 bus->self ? pci_name(bus->self) : "PHB",
1261 (unsigned long long)res->start,
1262 (unsigned long long)res->end,
1263 (unsigned int)res->flags,
1264 pr, (pr && pr->name) ? pr->name : "nil");
1266 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1267 if (request_resource(pr, res) == 0)
1270 * Must be a conflict with an existing entry.
1271 * Move that entry (or entries) under the
1272 * bridge resource and try again.
1274 if (reparent_resources(pr, res) == 0)
1277 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1278 "%d of PCI bridge %d, will remap\n", i, bus->number);
1283 list_for_each_entry(b, &bus->children, node)
1284 pcibios_allocate_bus_resources(b);
1287 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1289 struct resource *pr, *r = &dev->resource[idx];
1291 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1293 (unsigned long long)r->start,
1294 (unsigned long long)r->end,
1295 (unsigned int)r->flags);
1297 pr = pci_find_parent_resource(dev, r);
1298 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1299 request_resource(pr, r) < 0) {
1300 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1301 " of device %s, will remap\n", idx, pci_name(dev));
1303 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1305 (unsigned long long)pr->start,
1306 (unsigned long long)pr->end,
1307 (unsigned int)pr->flags);
1308 /* We'll assign a new address later */
1309 r->flags |= IORESOURCE_UNSET;
1315 static void __init pcibios_allocate_resources(int pass)
1317 struct pci_dev *dev = NULL;
1322 for_each_pci_dev(dev) {
1323 pci_read_config_word(dev, PCI_COMMAND, &command);
1324 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1325 r = &dev->resource[idx];
1326 if (r->parent) /* Already allocated */
1328 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1329 continue; /* Not assigned at all */
1330 /* We only allocate ROMs on pass 1 just in case they
1331 * have been screwed up by firmware
1333 if (idx == PCI_ROM_RESOURCE)
1335 if (r->flags & IORESOURCE_IO)
1336 disabled = !(command & PCI_COMMAND_IO);
1338 disabled = !(command & PCI_COMMAND_MEMORY);
1339 if (pass == disabled)
1340 alloc_resource(dev, idx);
1344 r = &dev->resource[PCI_ROM_RESOURCE];
1346 /* Turn the ROM off, leave the resource region,
1347 * but keep it unregistered.
1350 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1351 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1352 pr_debug("PCI: Switching off ROM of %s\n",
1354 r->flags &= ~IORESOURCE_ROM_ENABLE;
1355 pci_write_config_dword(dev, dev->rom_base_reg,
1356 reg & ~PCI_ROM_ADDRESS_ENABLE);
1362 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1364 struct pci_controller *hose = pci_bus_to_host(bus);
1365 resource_size_t offset;
1366 struct resource *res, *pres;
1369 pr_debug("Reserving legacy ranges for domain %04x\n",
1370 pci_domain_nr(bus));
1373 if (!(hose->io_resource.flags & IORESOURCE_IO))
1375 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1376 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1377 BUG_ON(res == NULL);
1378 res->name = "Legacy IO";
1379 res->flags = IORESOURCE_IO;
1380 res->start = offset;
1381 res->end = (offset + 0xfff) & 0xfffffffful;
1382 pr_debug("Candidate legacy IO: %pR\n", res);
1383 if (request_resource(&hose->io_resource, res)) {
1385 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1386 pci_domain_nr(bus), bus->number, res);
1391 /* Check for memory */
1392 offset = hose->pci_mem_offset;
1393 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1394 for (i = 0; i < 3; i++) {
1395 pres = &hose->mem_resources[i];
1396 if (!(pres->flags & IORESOURCE_MEM))
1398 pr_debug("hose mem res: %pR\n", pres);
1399 if ((pres->start - offset) <= 0xa0000 &&
1400 (pres->end - offset) >= 0xbffff)
1405 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1406 BUG_ON(res == NULL);
1407 res->name = "Legacy VGA memory";
1408 res->flags = IORESOURCE_MEM;
1409 res->start = 0xa0000 + offset;
1410 res->end = 0xbffff + offset;
1411 pr_debug("Candidate VGA memory: %pR\n", res);
1412 if (request_resource(pres, res)) {
1414 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1415 pci_domain_nr(bus), bus->number, res);
1420 void __init pcibios_resource_survey(void)
1424 /* Allocate and assign resources. If we re-assign everything, then
1425 * we skip the allocate phase
1427 list_for_each_entry(b, &pci_root_buses, node)
1428 pcibios_allocate_bus_resources(b);
1430 if (!(pci_flags & PCI_REASSIGN_ALL_RSRC)) {
1431 pcibios_allocate_resources(0);
1432 pcibios_allocate_resources(1);
1435 /* Before we start assigning unassigned resource, we try to reserve
1436 * the low IO area and the VGA memory area if they intersect the
1437 * bus available resources to avoid allocating things on top of them
1439 if (!(pci_flags & PCI_PROBE_ONLY)) {
1440 list_for_each_entry(b, &pci_root_buses, node)
1441 pcibios_reserve_legacy_regions(b);
1444 /* Now, if the platform didn't decide to blindly trust the firmware,
1445 * we proceed to assigning things that were left unassigned
1447 if (!(pci_flags & PCI_PROBE_ONLY)) {
1448 pr_debug("PCI: Assigning unassigned resources...\n");
1449 pci_assign_unassigned_resources();
1453 #ifdef CONFIG_HOTPLUG
1455 /* This is used by the PCI hotplug driver to allocate resource
1456 * of newly plugged busses. We can try to consolidate with the
1457 * rest of the code later, for now, keep it as-is as our main
1458 * resource allocation function doesn't deal with sub-trees yet.
1460 void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1462 struct pci_dev *dev;
1463 struct pci_bus *child_bus;
1465 list_for_each_entry(dev, &bus->devices, bus_list) {
1468 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1469 struct resource *r = &dev->resource[i];
1471 if (r->parent || !r->start || !r->flags)
1474 pr_debug("PCI: Claiming %s: "
1475 "Resource %d: %016llx..%016llx [%x]\n",
1477 (unsigned long long)r->start,
1478 (unsigned long long)r->end,
1479 (unsigned int)r->flags);
1481 pci_claim_resource(dev, i);
1485 list_for_each_entry(child_bus, &bus->children, node)
1486 pcibios_claim_one_bus(child_bus);
1488 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1491 /* pcibios_finish_adding_to_bus
1493 * This is to be called by the hotplug code after devices have been
1494 * added to a bus, this include calling it for a PHB that is just
1497 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1499 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1500 pci_domain_nr(bus), bus->number);
1502 /* Allocate bus and devices resources */
1503 pcibios_allocate_bus_resources(bus);
1504 pcibios_claim_one_bus(bus);
1506 /* Add new devices to global lists. Register in proc, sysfs. */
1507 pci_bus_add_devices(bus);
1510 eeh_add_device_tree_late(bus);
1512 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1514 #endif /* CONFIG_HOTPLUG */
1516 int pcibios_enable_device(struct pci_dev *dev, int mask)
1518 return pci_enable_resources(dev, mask);
1521 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1523 struct pci_bus *bus = hose->bus;
1524 struct resource *res;
1527 /* Hookup PHB IO resource */
1528 bus->resource[0] = res = &hose->io_resource;
1531 printk(KERN_WARNING "PCI: I/O resource not set for host"
1532 " bridge %s (domain %d)\n",
1533 hose->dn->full_name, hose->global_number);
1534 /* Workaround for lack of IO resource only on 32-bit */
1535 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1536 res->end = res->start + IO_SPACE_LIMIT;
1537 res->flags = IORESOURCE_IO;
1540 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1541 (unsigned long long)res->start,
1542 (unsigned long long)res->end,
1543 (unsigned long)res->flags);
1545 /* Hookup PHB Memory resources */
1546 for (i = 0; i < 3; ++i) {
1547 res = &hose->mem_resources[i];
1551 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1552 "host bridge %s (domain %d)\n",
1553 hose->dn->full_name, hose->global_number);
1555 /* Workaround for lack of MEM resource only on 32-bit */
1556 res->start = hose->pci_mem_offset;
1557 res->end = (resource_size_t)-1LL;
1558 res->flags = IORESOURCE_MEM;
1561 bus->resource[i+1] = res;
1563 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1564 i, (unsigned long long)res->start,
1565 (unsigned long long)res->end,
1566 (unsigned long)res->flags);
1569 pr_debug("PCI: PHB MEM offset = %016llx\n",
1570 (unsigned long long)hose->pci_mem_offset);
1571 pr_debug("PCI: PHB IO offset = %08lx\n",
1572 (unsigned long)hose->io_base_virt - _IO_BASE);
1576 * Null PCI config access functions, for the case when we can't
1579 #define NULL_PCI_OP(rw, size, type) \
1581 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1583 return PCIBIOS_DEVICE_NOT_FOUND; \
1587 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1590 return PCIBIOS_DEVICE_NOT_FOUND;
1594 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1597 return PCIBIOS_DEVICE_NOT_FOUND;
1600 static struct pci_ops null_pci_ops = {
1601 .read = null_read_config,
1602 .write = null_write_config,
1606 * These functions are used early on before PCI scanning is done
1607 * and all of the pci_dev and pci_bus structures have been created.
1609 static struct pci_bus *
1610 fake_pci_bus(struct pci_controller *hose, int busnr)
1612 static struct pci_bus bus;
1615 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1619 bus.ops = hose ? hose->ops : &null_pci_ops;
1623 #define EARLY_PCI_OP(rw, size, type) \
1624 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1625 int devfn, int offset, type value) \
1627 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1628 devfn, offset, value); \
1631 EARLY_PCI_OP(read, byte, u8 *)
1632 EARLY_PCI_OP(read, word, u16 *)
1633 EARLY_PCI_OP(read, dword, u32 *)
1634 EARLY_PCI_OP(write, byte, u8)
1635 EARLY_PCI_OP(write, word, u16)
1636 EARLY_PCI_OP(write, dword, u32)
1638 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1641 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);