2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
4 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
5 * based on v850 version which was
6 * Copyright (C) 2001,02,03 NEC Electronics Corporation
7 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file COPYING in the main directory of this
11 * archive for more details.
15 #ifndef _ASM_MICROBLAZE_CACHEFLUSH_H
16 #define _ASM_MICROBLAZE_CACHEFLUSH_H
18 /* Somebody depends on this; sigh... */
21 /* Look at Documentation/cachetlb.txt */
24 * Cache handling functions.
25 * Microblaze has a write-through data cache, meaning that the data cache
26 * never needs to be flushed. The only flushing operations that are
27 * implemented are to invalidate the instruction cache. These are called
28 * after loading a user application into memory, we must invalidate the
29 * instruction cache to make sure we don't fetch old, bad code.
32 /* struct cache, d=dcache, i=icache, fl = flush, iv = invalidate,
36 void (*ie)(void); /* enable */
37 void (*id)(void); /* disable */
38 void (*ifl)(void); /* flush */
39 void (*iflr)(unsigned long a, unsigned long b);
40 void (*iin)(void); /* invalidate */
41 void (*iinr)(unsigned long a, unsigned long b);
43 void (*de)(void); /* enable */
44 void (*dd)(void); /* disable */
45 void (*dfl)(void); /* flush */
46 void (*dflr)(unsigned long a, unsigned long b);
47 void (*din)(void); /* invalidate */
48 void (*dinr)(unsigned long a, unsigned long b);
51 /* microblaze cache */
52 extern struct scache *mbc;
54 void microblaze_cache_init(void);
56 #define enable_icache() mbc->ie();
57 #define disable_icache() mbc->id();
58 #define flush_icache() mbc->ifl();
59 #define flush_icache_range(start, end) mbc->iflr(start, end);
60 #define invalidate_icache() mbc->iin();
61 #define invalidate_icache_range(start, end) mbc->iinr(start, end);
64 #define flush_icache_user_range(vma, pg, adr, len) flush_icache();
65 #define flush_icache_page(vma, pg) do { } while (0)
67 #define enable_dcache() mbc->de();
68 #define disable_dcache() mbc->dd();
69 /* FIXME for LL-temac driver */
70 #define invalidate_dcache() mbc->din();
71 #define invalidate_dcache_range(start, end) mbc->dinr(start, end);
72 #define flush_dcache() mbc->dfl();
73 #define flush_dcache_range(start, end) mbc->dflr(start, end);
75 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
76 /* D-cache aliasing problem can't happen - cache is between MMU and ram */
77 #define flush_dcache_page(page) do { } while (0)
78 #define flush_dcache_mmap_lock(mapping) do { } while (0)
79 #define flush_dcache_mmap_unlock(mapping) do { } while (0)
82 #define flush_cache_dup_mm(mm) do { } while (0)
83 #define flush_cache_vmap(start, end) do { } while (0)
84 #define flush_cache_vunmap(start, end) do { } while (0)
85 #define flush_cache_mm(mm) do { } while (0)
86 #define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
88 /* MS: kgdb code use this macro, wrong len with FLASH */
90 #define flush_cache_range(vma, start, len) { \
91 flush_icache_range((unsigned) (start), (unsigned) (start) + (len)); \
92 flush_dcache_range((unsigned) (start), (unsigned) (start) + (len)); \
96 #define flush_cache_range(vma, start, len) do { } while (0)
98 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
100 memcpy((dst), (src), (len)); \
101 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
104 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
106 memcpy((dst), (src), (len)); \
109 #endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */