4 * General interrupt controller code for the many ColdFire cores that use
5 * interrupt controllers with 63 interrupt sources, organized as 56 fully-
6 * programmable + 7 fixed-level interrupt sources. This includes the 523x
7 * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
8 * controllers, and the 547x and 548x families which have only one of them.
10 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
23 #include <asm/coldfire.h>
24 #include <asm/mcfsim.h>
25 #include <asm/traps.h>
28 * Bit definitions for the ICR family of registers.
30 #define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
31 #define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
34 * Each vector needs a unique priority and level associated with it.
35 * We don't really care so much what they are, we don't rely on the
36 * traditional priority interrupt scheme of the m68k/ColdFire.
38 static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
46 static void intc_irq_mask(unsigned int irq)
48 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
49 unsigned long imraddr;
52 irq -= MCFINT_VECBASE;
55 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
57 imraddr += MCFICM_INTC0;
59 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
60 imrbit = 0x1 << (irq & 0x1f);
62 val = __raw_readl(imraddr);
63 __raw_writel(val | imrbit, imraddr);
67 static void intc_irq_unmask(unsigned int irq)
69 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
70 unsigned long intaddr, imraddr, icraddr;
73 irq -= MCFINT_VECBASE;
76 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
78 intaddr += MCFICM_INTC0;
80 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
81 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
82 imrbit = 0x1 << (irq & 0x1f);
84 /* Don't set the "maskall" bit! */
85 if ((irq & 0x20) == 0)
88 if (__raw_readb(icraddr) == 0)
89 __raw_writeb(intc_intpri--, icraddr);
91 val = __raw_readl(imraddr);
92 __raw_writel(val & ~imrbit, imraddr);
96 static int intc_irq_set_type(unsigned int irq, unsigned int type)
101 static struct irq_chip intc_irq_chip = {
103 .mask = intc_irq_mask,
104 .unmask = intc_irq_unmask,
105 .set_type = intc_irq_set_type,
108 void __init init_IRQ(void)
114 /* Mask all interrupt sources */
115 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
117 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
120 for (irq = 0; (irq < NR_IRQS); irq++) {
121 set_irq_chip(irq, &intc_irq_chip);
122 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
123 set_irq_handler(irq, handle_level_irq);