1 /***************************************************************************/
4 * linux/arch/m68knommu/platform/532x/config.c
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
9 * Copyright Freescale Semiconductor, Inc 2006
10 * Copyright (c) 2006, emlix, Sebastian Hess <sh@emlix.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
18 /***************************************************************************/
20 #include <linux/kernel.h>
21 #include <linux/param.h>
22 #include <linux/init.h>
24 #include <asm/machdep.h>
25 #include <asm/coldfire.h>
26 #include <asm/mcfsim.h>
27 #include <asm/mcfuart.h>
28 #include <asm/mcfdma.h>
29 #include <asm/mcfwdebug.h>
31 /***************************************************************************/
33 static struct mcf_platform_uart m532x_uart_platform[] = {
35 .mapbase = MCFUART_BASE1,
36 .irq = MCFINT_VECBASE + MCFINT_UART0,
39 .mapbase = MCFUART_BASE2,
40 .irq = MCFINT_VECBASE + MCFINT_UART1,
43 .mapbase = MCFUART_BASE3,
44 .irq = MCFINT_VECBASE + MCFINT_UART2,
49 static struct platform_device m532x_uart = {
52 .dev.platform_data = m532x_uart_platform,
55 static struct resource m532x_fec_resources[] = {
59 .flags = IORESOURCE_MEM,
64 .flags = IORESOURCE_IRQ,
69 .flags = IORESOURCE_IRQ,
74 .flags = IORESOURCE_IRQ,
78 static struct platform_device m532x_fec = {
81 .num_resources = ARRAY_SIZE(m532x_fec_resources),
82 .resource = m532x_fec_resources,
85 static struct platform_device *m532x_devices[] __initdata = {
90 /***************************************************************************/
92 static void __init m532x_uart_init_line(int line, int irq)
95 /* GPIO initialization */
96 MCF_GPIO_PAR_UART |= 0x000F;
97 } else if (line == 1) {
98 /* GPIO initialization */
99 MCF_GPIO_PAR_UART |= 0x0FF0;
103 static void __init m532x_uarts_init(void)
105 const int nrlines = ARRAY_SIZE(m532x_uart_platform);
108 for (line = 0; (line < nrlines); line++)
109 m532x_uart_init_line(line, m532x_uart_platform[line].irq);
111 /***************************************************************************/
113 static void __init m532x_fec_init(void)
115 /* Set multi-function pins to ethernet mode for fec0 */
116 MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
117 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
118 MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
119 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
122 /***************************************************************************/
124 static void m532x_cpu_reset(void)
127 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
130 /***************************************************************************/
132 void __init config_BSP(char *commandp, int size)
134 #if !defined(CONFIG_BOOTPARAM)
135 /* Copy command line from FLASH to local buffer... */
136 memcpy(commandp, (char *) 0x4000, 4);
137 if(strncmp(commandp, "kcl ", 4) == 0){
138 memcpy(commandp, (char *) 0x4004, size);
139 commandp[size-1] = 0;
141 memset(commandp, 0, size);
145 #ifdef CONFIG_BDM_DISABLE
147 * Disable the BDM clocking. This also turns off most of the rest of
148 * the BDM device. This is good for EMC reasons. This option is not
149 * incompatible with the memory protection option.
151 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
155 /***************************************************************************/
157 static int __init init_BSP(void)
161 platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices));
165 arch_initcall(init_BSP);
167 /***************************************************************************/
168 /* Board initialization */
169 /***************************************************************************/
171 * PLL min/max specifications
173 #define MAX_FVCO 500000 /* KHz */
174 #define MAX_FSYS 80000 /* KHz */
175 #define MIN_FSYS 58333 /* KHz */
176 #define FREF 16000 /* KHz */
179 #define MAX_MFD 135 /* Multiplier */
180 #define MIN_MFD 88 /* Multiplier */
181 #define BUSDIV 6 /* Divider */
184 * Low Power Divider specifications
186 #define MIN_LPD (1 << 0) /* Divider (not encoded) */
187 #define MAX_LPD (1 << 15) /* Divider (not encoded) */
188 #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
190 #define SYS_CLK_KHZ 80000
191 #define SYSTEM_PERIOD 12.5
193 * SDRAM Timing Parameters
195 #define SDRAM_BL 8 /* # of beats in a burst */
196 #define SDRAM_TWR 2 /* in clocks */
197 #define SDRAM_CASL 2.5 /* CASL in clocks */
198 #define SDRAM_TRCD 2 /* in clocks */
199 #define SDRAM_TRP 2 /* in clocks */
200 #define SDRAM_TRFC 7 /* in clocks */
201 #define SDRAM_TREFI 7800 /* in ns */
203 #define EXT_SRAM_ADDRESS (0xC0000000)
204 #define FLASH_ADDRESS (0x00000000)
205 #define SDRAM_ADDRESS (0x40000000)
207 #define NAND_FLASH_ADDRESS (0xD0000000)
214 void gpio_init(void);
215 void fbcs_init(void);
216 void sdramc_init(void);
217 int clock_pll (int fsys, int flags);
218 int clock_limp (int);
219 int clock_exit_limp (void);
220 int get_sys_clock (void);
222 asmlinkage void __init sysinit(void)
224 sys_clk_khz = clock_pll(0, 0);
225 sys_clk_mhz = sys_clk_khz/1000;
236 /* Disable watchdog timer */
240 #define MCF_SCM_BCR_GBW (0x00000100)
241 #define MCF_SCM_BCR_GBR (0x00000200)
245 /* All masters are trusted */
246 MCF_SCM_MPR = 0x77777777;
248 /* Allow supervisor/user, read/write, and trusted/untrusted
249 access to all slaves */
258 MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
264 MCF_GPIO_PAR_CS = 0x0000003E;
266 /* Latch chip select */
267 MCF_FBCS1_CSAR = 0x10080000;
269 MCF_FBCS1_CSCR = 0x002A3780;
270 MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
272 /* Initialize latch to drive signals to inactive states */
273 *((u16 *)(0x10080000)) = 0xFFFF;
276 MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
277 MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
280 | MCF_FBCS_CSCR_WS(1));
281 MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
284 /* Boot Flash connected to FBCS0 */
285 MCF_FBCS0_CSAR = FLASH_ADDRESS;
286 MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
290 | MCF_FBCS_CSCR_WS(7));
291 MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
295 void sdramc_init(void)
298 * Check to see if the SDRAM has already been initialized
299 * by a run control tool
301 if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
302 /* SDRAM chip select initialization */
304 /* Initialize SDRAM chip select */
305 MCF_SDRAMC_SDCS0 = (0
306 | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
307 | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
310 * Basic configuration and initialization
312 MCF_SDRAMC_SDCFG1 = (0
313 | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
314 | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
315 | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
316 | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
317 | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
318 | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
319 | MCF_SDRAMC_SDCFG1_WTLAT(3));
320 MCF_SDRAMC_SDCFG2 = (0
321 | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
322 | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
323 | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
324 | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
328 * Precharge and enable write to SDMR
331 | MCF_SDRAMC_SDCR_MODE_EN
332 | MCF_SDRAMC_SDCR_CKE
333 | MCF_SDRAMC_SDCR_DDR
334 | MCF_SDRAMC_SDCR_MUX(1)
335 | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
336 | MCF_SDRAMC_SDCR_PS_16
337 | MCF_SDRAMC_SDCR_IPALL);
340 * Write extended mode register
343 | MCF_SDRAMC_SDMR_BNKAD_LEMR
344 | MCF_SDRAMC_SDMR_AD(0x0)
345 | MCF_SDRAMC_SDMR_CMD);
348 * Write mode register and reset DLL
351 | MCF_SDRAMC_SDMR_BNKAD_LMR
352 | MCF_SDRAMC_SDMR_AD(0x163)
353 | MCF_SDRAMC_SDMR_CMD);
356 * Execute a PALL command
358 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
361 * Perform two REF cycles
363 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
364 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
367 * Write mode register and clear reset DLL
370 | MCF_SDRAMC_SDMR_BNKAD_LMR
371 | MCF_SDRAMC_SDMR_AD(0x063)
372 | MCF_SDRAMC_SDMR_CMD);
375 * Enable auto refresh and lock SDMR
377 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
378 MCF_SDRAMC_SDCR |= (0
379 | MCF_SDRAMC_SDCR_REF
380 | MCF_SDRAMC_SDCR_DQS_OE(0xC));
386 /* Enable UART0 pins */
387 MCF_GPIO_PAR_UART = ( 0
388 | MCF_GPIO_PAR_UART_PAR_URXD0
389 | MCF_GPIO_PAR_UART_PAR_UTXD0);
391 /* Initialize TIN3 as a GPIO output to enable the write
393 MCF_GPIO_PAR_TIMER = 0x00;
394 __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
395 __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
399 int clock_pll(int fsys, int flags)
401 int fref, temp, fout, mfd;
407 /* Return current PLL output */
410 return (fref * mfd / (BUSDIV * 4));
413 /* Check bounds of requested system clock */
419 /* Multiplying by 100 when calculating the temp value,
420 and then dividing by 100 to calculate the mfd allows
421 for exact values without needing to include floating
423 temp = 100 * fsys / fref;
424 mfd = 4 * BUSDIV * temp / 100;
426 /* Determine the output frequency for selected values */
427 fout = (fref * mfd / (BUSDIV * 4));
430 * Check to see if the SDRAM has already been initialized.
431 * If it has then the SDRAM needs to be put into self refresh
432 * mode before reprogramming the PLL.
434 if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
435 /* Put SDRAM into self refresh mode */
436 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
439 * Initialize the PLL to generate the new system clock frequency.
440 * The device must be put into LIMP mode to reprogram the PLL.
443 /* Enter LIMP mode */
444 clock_limp(DEFAULT_LPD);
446 /* Reprogram PLL for desired fsys */
448 | MCF_PLL_PODR_CPUDIV(BUSDIV/3)
449 | MCF_PLL_PODR_BUSDIV(BUSDIV));
457 * Return the SDRAM to normal operation if it is in use.
459 if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
460 /* Exit self refresh mode */
461 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
463 /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
464 MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
466 /* wait for DQS logic to relock */
467 for (i = 0; i < 0x200; i++)
473 int clock_limp(int div)
477 /* Check bounds of divider */
483 /* Save of the current value of the SSIDIV so we don't
484 overwrite the value*/
485 temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
487 /* Apply the divider to the system clock */
489 | MCF_CCM_CDR_LPDIV(div)
490 | MCF_CCM_CDR_SSIDIV(temp));
492 MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
494 return (FREF/(3*(1 << div)));
497 int clock_exit_limp(void)
502 MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
504 /* Wait for PLL to lock */
505 while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
508 fout = get_sys_clock();
513 int get_sys_clock(void)
517 /* Test to see if device is in LIMP mode */
518 if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
519 divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
520 return (FREF/(2 << divider));
523 return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));