1 /***************************************************************************/
4 * linux/arch/m68knommu/platform/5307/config.c
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
10 /***************************************************************************/
12 #include <linux/kernel.h>
13 #include <linux/param.h>
14 #include <linux/init.h>
16 #include <asm/machdep.h>
17 #include <asm/coldfire.h>
18 #include <asm/mcfsim.h>
19 #include <asm/mcfuart.h>
20 #include <asm/mcfwdebug.h>
22 /***************************************************************************/
25 * Some platforms need software versions of the GPIO data registers.
27 unsigned short ppdata;
28 unsigned char ledbank = 0xff;
30 /***************************************************************************/
32 static struct mcf_platform_uart m5307_uart_platform[] = {
34 .mapbase = MCF_MBAR + MCFUART_BASE1,
38 .mapbase = MCF_MBAR + MCFUART_BASE2,
44 static struct platform_device m5307_uart = {
47 .dev.platform_data = m5307_uart_platform,
50 static struct platform_device *m5307_devices[] __initdata = {
54 /***************************************************************************/
56 static void __init m5307_uart_init_line(int line, int irq)
59 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
60 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
61 mcf_clrimr(MCFINTC_UART0);
62 } else if (line == 1) {
63 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
64 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
65 mcf_clrimr(MCFINTC_UART1);
69 static void __init m5307_uarts_init(void)
71 const int nrlines = ARRAY_SIZE(m5307_uart_platform);
74 for (line = 0; (line < nrlines); line++)
75 m5307_uart_init_line(line, m5307_uart_platform[line].irq);
78 /***************************************************************************/
80 static void __init m5307_timers_init(void)
82 /* Timer1 is always used as system timer */
83 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
84 MCF_MBAR + MCFSIM_TIMER1ICR);
86 #ifdef CONFIG_HIGHPROFILE
87 /* Timer2 is to be used as a high speed profile timer */
88 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
89 MCF_MBAR + MCFSIM_TIMER2ICR);
93 /***************************************************************************/
95 void m5307_cpu_reset(void)
98 /* Set watchdog to soft reset, and enabled */
99 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
101 /* wait for watchdog to timeout */;
104 /***************************************************************************/
106 void __init config_BSP(char *commandp, int size)
108 #if defined(CONFIG_NETtel) || \
109 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
110 /* Copy command line from FLASH to local buffer... */
111 memcpy(commandp, (char *) 0xf0004000, size);
112 commandp[size-1] = 0;
115 mach_reset = m5307_cpu_reset;
118 #ifdef CONFIG_BDM_DISABLE
120 * Disable the BDM clocking. This also turns off most of the rest of
121 * the BDM device. This is good for EMC reasons. This option is not
122 * incompatible with the memory protection option.
124 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
128 /***************************************************************************/
130 static int __init init_BSP(void)
133 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
137 arch_initcall(init_BSP);
139 /***************************************************************************/