1 /***************************************************************************/
4 * linux/arch/m68knommu/platform/520x/config.c
6 * Copyright (C) 2005, Freescale (www.freescale.com)
7 * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
8 * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
9 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
12 /***************************************************************************/
14 #include <linux/kernel.h>
15 #include <linux/param.h>
16 #include <linux/init.h>
18 #include <asm/machdep.h>
19 #include <asm/coldfire.h>
20 #include <asm/mcfsim.h>
21 #include <asm/mcfuart.h>
23 /***************************************************************************/
25 static struct mcf_platform_uart m520x_uart_platform[] = {
27 .mapbase = MCF_MBAR + MCFUART_BASE1,
28 .irq = MCFINT_VECBASE + MCFINT_UART0,
31 .mapbase = MCF_MBAR + MCFUART_BASE2,
32 .irq = MCFINT_VECBASE + MCFINT_UART1,
35 .mapbase = MCF_MBAR + MCFUART_BASE3,
36 .irq = MCFINT_VECBASE + MCFINT_UART2,
41 static struct platform_device m520x_uart = {
44 .dev.platform_data = m520x_uart_platform,
47 static struct resource m520x_fec_resources[] = {
49 .start = MCF_MBAR + 0x30000,
50 .end = MCF_MBAR + 0x30000 + 0x7ff,
51 .flags = IORESOURCE_MEM,
56 .flags = IORESOURCE_IRQ,
61 .flags = IORESOURCE_IRQ,
66 .flags = IORESOURCE_IRQ,
70 static struct platform_device m520x_fec = {
73 .num_resources = ARRAY_SIZE(m520x_fec_resources),
74 .resource = m520x_fec_resources,
77 static struct platform_device *m520x_devices[] __initdata = {
82 /***************************************************************************/
84 #define INTC0 (MCF_MBAR + MCFICM_INTC0)
86 static void __init m520x_uart_init_line(int line, int irq)
91 writeb(0x03, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
95 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
96 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
97 MCF_GPIO_PAR_UART_PAR_URXD0;
98 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
101 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
102 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
103 MCF_GPIO_PAR_UART_PAR_URXD1;
104 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
107 par2 = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
109 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
110 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
111 writeb(par2, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
116 static void __init m520x_uarts_init(void)
118 const int nrlines = ARRAY_SIZE(m520x_uart_platform);
121 for (line = 0; (line < nrlines); line++)
122 m520x_uart_init_line(line, m520x_uart_platform[line].irq);
125 /***************************************************************************/
127 static void __init m520x_fec_init(void)
131 /* Unmask FEC interrupts at ColdFire interrupt controller */
132 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 36);
133 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 40);
134 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 42);
136 /* Set multi-function pins to ethernet mode */
137 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
138 writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
140 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
141 writeb(v | 0x0f, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
144 /***************************************************************************/
146 static void m520x_cpu_reset(void)
149 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
152 /***************************************************************************/
154 void __init config_BSP(char *commandp, int size)
156 mach_reset = m520x_cpu_reset;
161 /***************************************************************************/
163 static int __init init_BSP(void)
165 platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices));
169 arch_initcall(init_BSP);
171 /***************************************************************************/