1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
15 #include <asm/immap.h>
16 #include <asm/processor.h>
19 #include <linux/compiler.h>
21 #if defined(CONFIG_CMD_NET)
29 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
31 #if !defined(CONFIG_SERIAL_BOOT)
32 #if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
33 out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
34 out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
35 out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
39 #if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
40 /* Latch chipselect */
41 out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
42 out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
43 out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
46 #if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
47 out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
48 out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
49 out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
52 #if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
53 out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
54 out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
55 out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
58 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
59 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
60 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
61 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
64 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
65 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
66 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
67 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
72 void cfspi_port_conf(void)
74 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
76 #ifdef CONFIG_MCF5441x
77 pm_t *pm = (pm_t *)MMAP_PM;
79 out_8(&gpio->par_dspi0,
80 GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
81 GPIO_PAR_DSPI0_SCK_DSPI0SCK);
82 out_8(&gpio->srcr_dspiow, 3);
85 out_8(&pm->pmcr0, 23);
91 * Breath some life into the CPU...
93 * Set up the memory map,
94 * initialize a bunch of registers,
95 * initialize the UPM's
99 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
101 #ifdef CONFIG_MCF5441x
102 scm_t *scm = (scm_t *) MMAP_SCM;
103 pm_t *pm = (pm_t *) MMAP_PM;
106 *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
108 /* Disable core watchdog */
109 out_be16(&scm->cwcr, 0);
110 out_8(&gpio->par_fbctl,
111 GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
112 GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
113 GPIO_PAR_FBCTL_TA_TA);
115 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
116 GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
119 out_8(&pm->pmcr0, 17);
122 out_8(&pm->pmcr0, 18);
123 out_8(&pm->pmcr0, 19);
124 out_8(&pm->pmcr0, 20);
127 out_8(&pm->pmcr0, 22);
128 out_8(&pm->pmcr1, 4);
129 out_8(&pm->pmcr1, 7);
132 out_8(&pm->pmcr0, 28);
133 out_8(&pm->pmcr0, 29);
134 out_8(&pm->pmcr0, 30);
135 out_8(&pm->pmcr0, 31);
138 out_8(&pm->pmcr0, 32);
139 out_8(&pm->pmcr0, 33);
140 out_8(&pm->pmcr0, 34);
141 out_8(&pm->pmcr0, 35);
144 out_8(&pm->pmcr0, 36);
145 out_8(&pm->pmcr0, 37);
148 out_8(&pm->pmcr0, 44);
150 out_8(&pm->pmcr0, 45);
153 out_8(&pm->pmcr0, 51);
156 out_8(&pm->pmcr0, 53);
157 out_8(&pm->pmcr0, 54);
160 out_8(&pm->pmcr0, 63);
162 #ifdef CONFIG_SYS_I2C_0
163 out_8(&gpio->par_cani2c, 0xF0);
165 out_be16(&gpio->pcr_b, 0x003C);
167 out_8(&gpio->srcr_cani2c, 0x03);
169 #ifdef CONFIG_SYS_I2C_2
171 out_8(&gpio->par_ssi0h, 0xA0);
173 out_8(&gpio->par_ssi0h, 0xA8);
175 out_8(&gpio->par_ssi0l, 0x2);
177 out_8(&gpio->par_cani2c, 0xAA);
179 out_8(&gpio->par_uart0, 0xAF);
181 out_8(&gpio->par_uart1, 0xAF);
183 out_8(&gpio->par_uart2, 0xAF);
185 out_be16(&gpio->pcr_h, 0xF000);
187 #ifdef CONFIG_SYS_I2C_5
189 out_8(&gpio->par_uart1, 0x0A);
191 out_be16(&gpio->pcr_e, 0x0003);
192 out_be16(&gpio->pcr_f, 0xC000);
195 /* Lowest slew rate for UART0,1,2 */
196 out_8(&gpio->srcr_uart, 0x00);
198 #ifdef CONFIG_FSL_ESDHC_IMX
199 /* eSDHC pin as faster speed */
200 out_8(&gpio->srcr_sdhc, 0x03);
202 /* All esdhc pins as SD */
203 out_8(&gpio->par_sdhch, 0xff);
204 out_8(&gpio->par_sdhcl, 0xff);
206 #endif /* CONFIG_MCF5441x */
208 /* FlexBus Chipselect */
211 #ifdef CFG_SYS_CS0_BASE
213 * now the flash base address is no longer at 0 (Newer ColdFire family
214 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
215 * also move to the new location.
217 if (CFG_SYS_CS0_BASE != 0)
218 setvbr(CFG_SYS_CS0_BASE);
225 * initialize higher level parts of CPU like timers
230 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
231 rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
233 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
234 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
240 void uart_port_conf(int port)
242 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
243 #ifdef CONFIG_MCF5441x
244 pm_t *pm = (pm_t *) MMAP_PM;
249 #ifdef CONFIG_MCF5441x
252 out_8(&pm->pmcr0, 24);
253 clrbits_8(&gpio->par_uart0,
254 ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
255 setbits_8(&gpio->par_uart0,
256 GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
260 out_8(&pm->pmcr0, 25);
261 clrbits_8(&gpio->par_uart1,
262 ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
263 setbits_8(&gpio->par_uart1,
264 GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
268 out_8(&pm->pmcr0, 26);
269 clrbits_8(&gpio->par_uart2,
270 ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
271 setbits_8(&gpio->par_uart2,
272 GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
276 out_8(&pm->pmcr0, 27);
277 clrbits_8(&gpio->par_dspi0,
278 ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
279 setbits_8(&gpio->par_dspi0,
280 GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
284 out_8(&pm->pmcr1, 24);
285 clrbits_8(&gpio->par_uart0,
286 ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
287 setbits_8(&gpio->par_uart0,
288 GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
292 out_8(&pm->pmcr1, 25);
293 clrbits_8(&gpio->par_uart1,
294 ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
295 setbits_8(&gpio->par_uart1,
296 GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
300 out_8(&pm->pmcr1, 26);
301 clrbits_8(&gpio->par_uart2,
302 ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
303 setbits_8(&gpio->par_uart2,
304 GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
308 out_8(&pm->pmcr1, 27);
309 clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
310 clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
311 setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
312 setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
316 out_8(&pm->pmcr0, 28);
317 clrbits_8(&gpio->par_cani2c,
318 ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
319 setbits_8(&gpio->par_cani2c,
320 GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
324 out_8(&pm->pmcr1, 29);
325 clrbits_8(&gpio->par_cani2c,
326 ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
327 setbits_8(&gpio->par_cani2c,
328 GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
334 #if defined(CONFIG_CMD_NET)
335 int fecpin_setclear(fec_info_t *info, int setclear)
337 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
340 if (fec_get_base_addr(0, &fec0_base))
343 #ifdef CONFIG_MCF5441x
345 out_8(&gpio->par_fec, 0x03);
346 out_8(&gpio->srcr_fec, 0x0F);
347 clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
348 GPIO_PAR_SIMP0H_DAT_GPIO);
349 clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
350 GPIO_PDDR_G4_OUTPUT);
351 clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
354 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);