1 // SPDX-License-Identifier: GPL-2.0+
4 * Josef Baumgartner <josef.baumgartner@telex.de>
8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
11 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
13 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
21 #include <asm/immap.h>
26 DECLARE_GLOBAL_DATA_PTR;
29 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
31 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
35 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
37 /* we don't return! */
41 #if defined(CONFIG_DISPLAY_CPUINFO)
42 int print_cpuinfo(void)
44 char buf1[32], buf2[32];
46 printf("CPU: Freescale Coldfire MCF5208\n"
47 " CPU CLK %s MHz BUS CLK %s MHz\n",
48 strmhz(buf1, gd->cpu_clk),
49 strmhz(buf2, gd->bus_clk));
52 #endif /* CONFIG_DISPLAY_CPUINFO */
54 #if defined(CONFIG_WATCHDOG)
55 /* Called by macro WATCHDOG_RESET */
56 void watchdog_reset(void)
58 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
60 out_be16(&wdt->sr, 0x5555);
61 out_be16(&wdt->sr, 0xaaaa);
64 int watchdog_disable(void)
66 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
68 /* reset watchdog counter */
69 out_be16(&wdt->sr, 0x5555);
70 out_be16(&wdt->sr, 0xaaaa);
71 /* disable watchdog timer */
72 out_be16(&wdt->cr, 0);
74 puts("WATCHDOG:disabled\n");
78 int watchdog_init(void)
80 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
82 /* disable watchdog */
83 out_be16(&wdt->cr, 0);
85 /* set timeout and enable watchdog */
87 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
89 /* reset watchdog counter */
90 out_be16(&wdt->sr, 0x5555);
91 out_be16(&wdt->sr, 0xaaaa);
93 puts("WATCHDOG:enabled\n");
96 #endif /* #ifdef CONFIG_WATCHDOG */
97 #endif /* #ifdef CONFIG_M5208 */
100 #if defined(CONFIG_DISPLAY_CPUINFO)
102 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
103 * determine which one we are running on, based on the Chip Identification
106 int print_cpuinfo(void)
109 unsigned short cir; /* Chip Identification Register */
110 unsigned short pin; /* Part identification number */
111 unsigned char prn; /* Part revision number */
114 cir = mbar_readShort(MCF_CCM_CIR);
115 pin = cir >> MCF_CCM_CIR_PIN_LEN;
116 prn = cir & MCF_CCM_CIR_PRN_MASK;
119 case MCF_CCM_CIR_PIN_MCF5270:
122 case MCF_CCM_CIR_PIN_MCF5271:
131 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
132 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
134 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
135 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
136 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
140 #endif /* CONFIG_DISPLAY_CPUINFO */
142 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
144 /* Call the board specific reset actions first. */
149 mbar_writeByte(MCF_RCM_RCR,
150 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
154 #if defined(CONFIG_WATCHDOG)
155 void watchdog_reset(void)
157 mbar_writeShort(MCF_WTM_WSR, 0x5555);
158 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
161 int watchdog_disable(void)
163 mbar_writeShort(MCF_WTM_WCR, 0);
167 int watchdog_init(void)
169 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
172 #endif /* #ifdef CONFIG_WATCHDOG */
177 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
179 wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
181 out_be16(&wdp->wdog_wrrr, 0);
184 /* enable watchdog, set timeout to 0 and wait */
185 out_be16(&wdp->wdog_wrrr, 1);
188 /* we don't return! */
192 #if defined(CONFIG_DISPLAY_CPUINFO)
193 int print_cpuinfo(void)
195 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
200 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
210 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
215 printf("Freescale MCF5272 %s\n", suf);
218 #endif /* CONFIG_DISPLAY_CPUINFO */
220 #if defined(CONFIG_WATCHDOG)
221 /* Called by macro WATCHDOG_RESET */
222 void watchdog_reset(void)
224 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
226 out_be16(&wdt->wdog_wcr, 0);
229 int watchdog_disable(void)
231 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
233 /* reset watchdog counter */
234 out_be16(&wdt->wdog_wcr, 0);
235 /* disable watchdog interrupt */
236 out_be16(&wdt->wdog_wirr, 0);
237 /* disable watchdog timer */
238 out_be16(&wdt->wdog_wrrr, 0);
240 puts("WATCHDOG:disabled\n");
244 int watchdog_init(void)
246 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
248 /* disable watchdog interrupt */
249 out_be16(&wdt->wdog_wirr, 0);
251 /* set timeout and enable watchdog */
252 out_be16(&wdt->wdog_wrrr,
253 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
255 /* reset watchdog counter */
256 out_be16(&wdt->wdog_wcr, 0);
258 puts("WATCHDOG:enabled\n");
261 #endif /* #ifdef CONFIG_WATCHDOG */
263 #endif /* #ifdef CONFIG_M5272 */
266 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
268 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
272 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
274 /* we don't return! */
278 #if defined(CONFIG_DISPLAY_CPUINFO)
279 int print_cpuinfo(void)
283 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
284 strmhz(buf, CONFIG_SYS_CLK));
287 #endif /* CONFIG_DISPLAY_CPUINFO */
289 #if defined(CONFIG_WATCHDOG)
290 /* Called by macro WATCHDOG_RESET */
291 void watchdog_reset(void)
293 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
295 out_be16(&wdt->wsr, 0x5555);
296 out_be16(&wdt->wsr, 0xaaaa);
299 int watchdog_disable(void)
301 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
303 /* reset watchdog counter */
304 out_be16(&wdt->wsr, 0x5555);
305 out_be16(&wdt->wsr, 0xaaaa);
307 /* disable watchdog timer */
308 out_be16(&wdt->wcr, 0);
310 puts("WATCHDOG:disabled\n");
314 int watchdog_init(void)
316 wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
318 /* disable watchdog */
319 out_be16(&wdt->wcr, 0);
321 /* set timeout and enable watchdog */
323 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
325 /* reset watchdog counter */
326 out_be16(&wdt->wsr, 0x5555);
327 out_be16(&wdt->wsr, 0xaaaa);
329 puts("WATCHDOG:enabled\n");
332 #endif /* #ifdef CONFIG_WATCHDOG */
334 #endif /* #ifdef CONFIG_M5275 */
337 #if defined(CONFIG_DISPLAY_CPUINFO)
338 int print_cpuinfo(void)
340 unsigned char resetsource = MCFRESET_RSR;
342 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
343 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
344 printf("Reset:%s%s%s%s%s%s%s\n",
345 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
346 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
347 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
348 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
349 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
350 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
351 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
354 #endif /* CONFIG_DISPLAY_CPUINFO */
356 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
358 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
364 #if defined(CONFIG_DISPLAY_CPUINFO)
365 int print_cpuinfo(void)
369 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
370 strmhz(buf, CONFIG_SYS_CLK));
373 #endif /* CONFIG_DISPLAY_CPUINFO */
375 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
377 /* enable watchdog, set timeout to 0 and wait */
378 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
381 /* we don't return! */
387 #if defined(CONFIG_DISPLAY_CPUINFO)
388 int print_cpuinfo(void)
392 unsigned char resetsource = mbar_readLong(SIM_RSR);
393 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
394 strmhz(buf, CONFIG_SYS_CLK));
396 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
397 printf("Reset:%s%s\n",
398 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
400 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
405 #endif /* CONFIG_DISPLAY_CPUINFO */
407 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
409 /* enable watchdog, set timeout to 0 and wait */
410 mbar_writeByte(SIM_SYPCR, 0xc0);
413 /* we don't return! */
418 #if defined(CONFIG_MCFFEC)
419 /* Default initializations for MCFFEC controllers. To override,
420 * create a board-specific function called:
421 * int board_eth_init(bd_t *bis)
424 int cpu_eth_init(bd_t *bis)
426 return mcffec_initialize(bis);