2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/bitmap.h>
13 #include <asm/sn/sn_sal.h>
14 #include <asm/sn/addrs.h>
15 #include <asm/sn/io.h>
16 #include <asm/sn/pcidev.h>
17 #include <asm/sn/pcibus_provider_defs.h>
18 #include <asm/sn/tioca_provider.h>
21 EXPORT_SYMBOL(tioca_gart_found); /* used by agp-sgi */
23 LIST_HEAD(tioca_list);
24 EXPORT_SYMBOL(tioca_list); /* used by agp-sgi */
26 static int tioca_gart_init(struct tioca_kernel *);
29 * tioca_gart_init - Initialize SGI TIOCA GART
30 * @tioca_common: ptr to common prom/kernel struct identifying the
32 * If the indicated tioca has devices present, initialize its associated
33 * GART MMR's and kernel memory.
36 tioca_gart_init(struct tioca_kernel *tioca_kern)
41 struct tioca_common *tioca_common;
42 struct tioca __iomem *ca_base;
44 tioca_common = tioca_kern->ca_common;
45 ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
47 if (list_empty(tioca_kern->ca_devices))
53 * Validate aperature size
56 switch (CA_APERATURE_SIZE >> 20) {
58 ap_reg |= (0x3ff << CA_GART_AP_SIZE_SHFT); /* 4MB */
61 ap_reg |= (0x3fe << CA_GART_AP_SIZE_SHFT); /* 8MB */
64 ap_reg |= (0x3fc << CA_GART_AP_SIZE_SHFT); /* 16MB */
67 ap_reg |= (0x3f8 << CA_GART_AP_SIZE_SHFT); /* 32 MB */
70 ap_reg |= (0x3f0 << CA_GART_AP_SIZE_SHFT); /* 64 MB */
73 ap_reg |= (0x3e0 << CA_GART_AP_SIZE_SHFT); /* 128 MB */
76 ap_reg |= (0x3c0 << CA_GART_AP_SIZE_SHFT); /* 256 MB */
79 ap_reg |= (0x380 << CA_GART_AP_SIZE_SHFT); /* 512 MB */
82 ap_reg |= (0x300 << CA_GART_AP_SIZE_SHFT); /* 1GB */
85 ap_reg |= (0x200 << CA_GART_AP_SIZE_SHFT); /* 2GB */
88 ap_reg |= (0x000 << CA_GART_AP_SIZE_SHFT); /* 4 GB */
91 printk(KERN_ERR "%s: Invalid CA_APERATURE_SIZE "
92 "0x%lx\n", __func__, (ulong) CA_APERATURE_SIZE);
97 * Set up other aperature parameters
100 if (PAGE_SIZE >= 16384) {
101 tioca_kern->ca_ap_pagesize = 16384;
102 ap_reg |= CA_GART_PAGE_SIZE;
104 tioca_kern->ca_ap_pagesize = 4096;
107 tioca_kern->ca_ap_size = CA_APERATURE_SIZE;
108 tioca_kern->ca_ap_bus_base = CA_APERATURE_BASE;
109 tioca_kern->ca_gart_entries =
110 tioca_kern->ca_ap_size / tioca_kern->ca_ap_pagesize;
112 ap_reg |= (CA_GART_AP_ENB_AGP | CA_GART_AP_ENB_PCI);
113 ap_reg |= tioca_kern->ca_ap_bus_base;
116 * Allocate and set up the GART
119 tioca_kern->ca_gart_size = tioca_kern->ca_gart_entries * sizeof(u64);
121 alloc_pages_node(tioca_kern->ca_closest_node,
122 GFP_KERNEL | __GFP_ZERO,
123 get_order(tioca_kern->ca_gart_size));
126 printk(KERN_ERR "%s: Could not allocate "
127 "%llu bytes (order %d) for GART\n",
129 tioca_kern->ca_gart_size,
130 get_order(tioca_kern->ca_gart_size));
134 tioca_kern->ca_gart = page_address(tmp);
135 tioca_kern->ca_gart_coretalk_addr =
136 PHYS_TO_TIODMA(virt_to_phys(tioca_kern->ca_gart));
139 * Compute PCI/AGP convenience fields
142 offset = CA_PCI32_MAPPED_BASE - CA_APERATURE_BASE;
143 tioca_kern->ca_pciap_base = CA_PCI32_MAPPED_BASE;
144 tioca_kern->ca_pciap_size = CA_PCI32_MAPPED_SIZE;
145 tioca_kern->ca_pcigart_start = offset / tioca_kern->ca_ap_pagesize;
146 tioca_kern->ca_pcigart_base =
147 tioca_kern->ca_gart_coretalk_addr + offset;
148 tioca_kern->ca_pcigart =
149 &tioca_kern->ca_gart[tioca_kern->ca_pcigart_start];
150 tioca_kern->ca_pcigart_entries =
151 tioca_kern->ca_pciap_size / tioca_kern->ca_ap_pagesize;
152 tioca_kern->ca_pcigart_pagemap =
153 kzalloc(tioca_kern->ca_pcigart_entries / 8, GFP_KERNEL);
154 if (!tioca_kern->ca_pcigart_pagemap) {
155 free_pages((unsigned long)tioca_kern->ca_gart,
156 get_order(tioca_kern->ca_gart_size));
160 offset = CA_AGP_MAPPED_BASE - CA_APERATURE_BASE;
161 tioca_kern->ca_gfxap_base = CA_AGP_MAPPED_BASE;
162 tioca_kern->ca_gfxap_size = CA_AGP_MAPPED_SIZE;
163 tioca_kern->ca_gfxgart_start = offset / tioca_kern->ca_ap_pagesize;
164 tioca_kern->ca_gfxgart_base =
165 tioca_kern->ca_gart_coretalk_addr + offset;
166 tioca_kern->ca_gfxgart =
167 &tioca_kern->ca_gart[tioca_kern->ca_gfxgart_start];
168 tioca_kern->ca_gfxgart_entries =
169 tioca_kern->ca_gfxap_size / tioca_kern->ca_ap_pagesize;
172 * various control settings:
173 * use agp op-combining
174 * use GET semantics to fetch memory
175 * participate in coherency domain
176 * DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029
179 __sn_setq_relaxed(&ca_base->ca_control1,
180 CA_AGPDMA_OP_ENB_COMBDELAY); /* PV895469 ? */
181 __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
182 __sn_setq_relaxed(&ca_base->ca_control2,
183 (0x2ull << CA_GART_MEM_PARAM_SHFT));
184 tioca_kern->ca_gart_iscoherent = 1;
185 __sn_clrq_relaxed(&ca_base->ca_control2,
186 (CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB));
189 * Unmask GART fetch error interrupts. Clear residual errors first.
192 writeq(CA_GART_FETCH_ERR, &ca_base->ca_int_status_alias);
193 writeq(CA_GART_FETCH_ERR, &ca_base->ca_mult_error_alias);
194 __sn_clrq_relaxed(&ca_base->ca_int_mask, CA_GART_FETCH_ERR);
197 * Program the aperature and gart registers in TIOCA
200 writeq(ap_reg, &ca_base->ca_gart_aperature);
201 writeq(tioca_kern->ca_gart_coretalk_addr|1, &ca_base->ca_gart_ptr_table);
207 * tioca_fastwrite_enable - enable AGP FW for a tioca and its functions
208 * @tioca_kernel: structure representing the CA
210 * Given a CA, scan all attached functions making sure they all support
211 * FastWrite. If so, enable FastWrite for all functions and the CA itself.
215 tioca_fastwrite_enable(struct tioca_kernel *tioca_kern)
219 struct tioca __iomem *tioca_base;
220 struct pci_dev *pdev;
221 struct tioca_common *common;
223 common = tioca_kern->ca_common;
226 * Scan all vga controllers on this bus making sure they all
227 * support FW. If not, return.
230 list_for_each_entry(pdev, tioca_kern->ca_devices, bus_list) {
231 if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
234 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
236 return; /* no AGP CAP means no FW */
238 pci_read_config_dword(pdev, cap_ptr + PCI_AGP_STATUS, ®);
239 if (!(reg & PCI_AGP_STATUS_FW))
240 return; /* function doesn't support FW */
244 * Set fw for all vga fn's
247 list_for_each_entry(pdev, tioca_kern->ca_devices, bus_list) {
248 if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
251 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
252 pci_read_config_dword(pdev, cap_ptr + PCI_AGP_COMMAND, ®);
253 reg |= PCI_AGP_COMMAND_FW;
254 pci_write_config_dword(pdev, cap_ptr + PCI_AGP_COMMAND, reg);
258 * Set ca's fw to match
261 tioca_base = (struct tioca __iomem*)common->ca_common.bs_base;
262 __sn_setq_relaxed(&tioca_base->ca_control1, CA_AGP_FW_ENABLE);
265 EXPORT_SYMBOL(tioca_fastwrite_enable); /* used by agp-sgi */
268 * tioca_dma_d64 - create a DMA mapping using 64-bit direct mode
269 * @paddr: system physical address
271 * Map @paddr into 64-bit CA bus space. No device context is necessary.
272 * Bits 53:0 come from the coretalk address. We just need to mask in the
273 * following optional bits of the 64-bit pci address:
275 * 63:60 - Coretalk Packet Type - 0x1 for Mem Get/Put (coherent)
276 * 0x2 for PIO (non-coherent)
277 * We will always use 0x1
278 * 55:55 - Swap bytes Currently unused
281 tioca_dma_d64(unsigned long paddr)
285 bus_addr = PHYS_TO_TIODMA(paddr);
288 BUG_ON(bus_addr >> 54);
290 /* Set upper nibble to Cache Coherent Memory op */
291 bus_addr |= (1UL << 60);
297 * tioca_dma_d48 - create a DMA mapping using 48-bit direct mode
298 * @pdev: linux pci_dev representing the function
299 * @paddr: system physical address
301 * Map @paddr into 64-bit bus space of the CA associated with @pcidev_info.
303 * The CA agp 48 bit direct address falls out as follows:
305 * When direct mapping AGP addresses, the 48 bit AGP address is
306 * constructed as follows:
308 * [47:40] - Low 8 bits of the page Node ID extracted from coretalk
309 * address [47:40]. The upper 8 node bits are fixed
310 * and come from the xxx register bits [5:0]
311 * [39:38] - Chiplet ID extracted from coretalk address [39:38]
312 * [37:00] - node offset extracted from coretalk address [37:00]
314 * Since the node id in general will be non-zero, and the chiplet id
315 * will always be non-zero, it follows that the device must support
316 * a dma mask of at least 0xffffffffff (40 bits) to target node 0
317 * and in general should be 0xffffffffffff (48 bits) to target nodes
318 * up to 255. Nodes above 255 need the support of the xxx register,
319 * and so a given CA can only directly target nodes in the range
323 tioca_dma_d48(struct pci_dev *pdev, u64 paddr)
325 struct tioca_common *tioca_common;
326 struct tioca __iomem *ca_base;
331 struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
333 tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
334 ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
336 ct_addr = PHYS_TO_TIODMA(paddr);
340 bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffffUL);
341 node_upper = ct_addr >> 48;
343 if (node_upper > 64) {
344 printk(KERN_ERR "%s: coretalk addr 0x%p node id out "
345 "of range\n", __func__, (void *)ct_addr);
349 agp_dma_extn = __sn_readq_relaxed(&ca_base->ca_agp_dma_addr_extn);
350 if (node_upper != (agp_dma_extn >> CA_AGP_DMA_NODE_ID_SHFT)) {
351 printk(KERN_ERR "%s: coretalk upper node (%u) "
352 "mismatch with ca_agp_dma_addr_extn (%llu)\n",
354 node_upper, (agp_dma_extn >> CA_AGP_DMA_NODE_ID_SHFT));
362 * tioca_dma_mapped - create a DMA mapping using a CA GART
363 * @pdev: linux pci_dev representing the function
364 * @paddr: host physical address to map
365 * @req_size: len (bytes) to map
367 * Map @paddr into CA address space using the GART mechanism. The mapped
368 * dma_addr_t is guaranteed to be contiguous in CA bus space.
371 tioca_dma_mapped(struct pci_dev *pdev, unsigned long paddr, size_t req_size)
373 int ps, ps_shift, entry, entries, mapsize;
374 u64 xio_addr, end_xio_addr;
375 struct tioca_common *tioca_common;
376 struct tioca_kernel *tioca_kern;
377 dma_addr_t bus_addr = 0;
378 struct tioca_dmamap *ca_dmamap;
381 struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
383 tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
384 tioca_kern = (struct tioca_kernel *)tioca_common->ca_kernel_private;
386 xio_addr = PHYS_TO_TIODMA(paddr);
390 spin_lock_irqsave(&tioca_kern->ca_lock, flags);
393 * allocate a map struct
396 ca_dmamap = kzalloc(sizeof(struct tioca_dmamap), GFP_ATOMIC);
401 * Locate free entries that can hold req_size. Account for
402 * unaligned start/length when allocating.
405 ps = tioca_kern->ca_ap_pagesize; /* will be power of 2 */
406 ps_shift = ffs(ps) - 1;
407 end_xio_addr = xio_addr + req_size - 1;
409 entries = (end_xio_addr >> ps_shift) - (xio_addr >> ps_shift) + 1;
411 map = tioca_kern->ca_pcigart_pagemap;
412 mapsize = tioca_kern->ca_pcigart_entries;
414 entry = bitmap_find_next_zero_area(map, mapsize, 0, entries, 0);
415 if (entry >= mapsize) {
420 bitmap_set(map, entry, entries);
422 bus_addr = tioca_kern->ca_pciap_base + (entry * ps);
424 ca_dmamap->cad_dma_addr = bus_addr;
425 ca_dmamap->cad_gart_size = entries;
426 ca_dmamap->cad_gart_entry = entry;
427 list_add(&ca_dmamap->cad_list, &tioca_kern->ca_dmamaps);
430 tioca_kern->ca_pcigart[entry] = tioca_paddr_to_gart(xio_addr);
431 bus_addr += xio_addr & (ps - 1);
432 xio_addr &= ~(ps - 1);
437 while (xio_addr < end_xio_addr) {
438 tioca_kern->ca_pcigart[entry] = tioca_paddr_to_gart(xio_addr);
443 tioca_tlbflush(tioca_kern);
446 spin_unlock_irqrestore(&tioca_kern->ca_lock, flags);
451 * tioca_dma_unmap - release CA mapping resources
452 * @pdev: linux pci_dev representing the function
453 * @bus_addr: bus address returned by an earlier tioca_dma_map
454 * @dir: mapping direction (unused)
456 * Locate mapping resources associated with @bus_addr and release them.
457 * For mappings created using the direct modes (64 or 48) there are no
458 * resources to release.
461 tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
464 struct tioca_common *tioca_common;
465 struct tioca_kernel *tioca_kern;
466 struct tioca_dmamap *map;
467 struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
470 tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
471 tioca_kern = (struct tioca_kernel *)tioca_common->ca_kernel_private;
473 /* return straight away if this isn't be a mapped address */
475 if (bus_addr < tioca_kern->ca_pciap_base ||
476 bus_addr >= (tioca_kern->ca_pciap_base + tioca_kern->ca_pciap_size))
479 spin_lock_irqsave(&tioca_kern->ca_lock, flags);
481 list_for_each_entry(map, &tioca_kern->ca_dmamaps, cad_list)
482 if (map->cad_dma_addr == bus_addr)
487 entry = map->cad_gart_entry;
489 for (i = 0; i < map->cad_gart_size; i++, entry++) {
490 clear_bit(entry, tioca_kern->ca_pcigart_pagemap);
491 tioca_kern->ca_pcigart[entry] = 0;
493 tioca_tlbflush(tioca_kern);
495 list_del(&map->cad_list);
496 spin_unlock_irqrestore(&tioca_kern->ca_lock, flags);
501 * tioca_dma_map - map pages for PCI DMA
502 * @pdev: linux pci_dev representing the function
503 * @paddr: host physical address to map
504 * @byte_count: bytes to map
506 * This is the main wrapper for mapping host physical pages to CA PCI space.
507 * The mapping mode used is based on the devices dma_mask. As a last resort
508 * use the GART mapped mode.
511 tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags)
516 * Not supported for now ...
518 if (dma_flags & SN_DMA_MSI)
522 * If card is 64 or 48 bit addressable, use a direct mapping. 32
523 * bit direct is so restrictive w.r.t. where the memory resides that
524 * we don't use it even though CA has some support.
527 if (pdev->dma_mask == ~0UL)
528 mapaddr = tioca_dma_d64(paddr);
529 else if (pdev->dma_mask == 0xffffffffffffUL)
530 mapaddr = tioca_dma_d48(pdev, paddr);
534 /* Last resort ... use PCI portion of CA GART */
537 mapaddr = tioca_dma_mapped(pdev, paddr, byte_count);
543 * tioca_error_intr_handler - SGI TIO CA error interrupt handler
545 * @arg: pointer to tioca_common struct for the given CA
547 * Handle a CA error interrupt. Simply a wrapper around a SAL call which
548 * defers processing to the SGI prom.
551 tioca_error_intr_handler(int irq, void *arg)
553 struct tioca_common *soft = arg;
554 struct ia64_sal_retval ret_stuff;
557 ret_stuff.status = 0;
560 segment = soft->ca_common.bs_persist_segment;
561 busnum = soft->ca_common.bs_persist_busnum;
563 SAL_CALL_NOLOCK(ret_stuff,
564 (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
565 segment, busnum, 0, 0, 0, 0, 0);
571 * tioca_bus_fixup - perform final PCI fixup for a TIO CA bus
572 * @prom_bussoft: Common prom/kernel struct representing the bus
574 * Replicates the tioca_common pointed to by @prom_bussoft in kernel
575 * space. Allocates and initializes a kernel-only area for a given CA,
576 * and sets up an irq for handling CA error interrupts.
578 * On successful setup, returns the kernel version of tioca_common back to
582 tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
584 struct tioca_common *tioca_common;
585 struct tioca_kernel *tioca_kern;
588 /* sanity check prom rev */
590 if (is_shub1() && sn_sal_rev() < 0x0406) {
592 (KERN_ERR "%s: SGI prom rev 4.06 or greater required "
593 "for tioca support\n", __func__);
598 * Allocate kernel bus soft and copy from prom.
601 tioca_common = kzalloc(sizeof(struct tioca_common), GFP_KERNEL);
605 memcpy(tioca_common, prom_bussoft, sizeof(struct tioca_common));
606 tioca_common->ca_common.bs_base = (unsigned long)
607 ioremap(REGION_OFFSET(tioca_common->ca_common.bs_base),
608 sizeof(struct tioca_common));
610 /* init kernel-private area */
612 tioca_kern = kzalloc(sizeof(struct tioca_kernel), GFP_KERNEL);
618 tioca_kern->ca_common = tioca_common;
619 spin_lock_init(&tioca_kern->ca_lock);
620 INIT_LIST_HEAD(&tioca_kern->ca_dmamaps);
621 tioca_kern->ca_closest_node =
622 nasid_to_cnodeid(tioca_common->ca_closest_nasid);
623 tioca_common->ca_kernel_private = (u64) tioca_kern;
625 bus = pci_find_bus(tioca_common->ca_common.bs_persist_segment,
626 tioca_common->ca_common.bs_persist_busnum);
628 tioca_kern->ca_devices = &bus->devices;
632 if (tioca_gart_init(tioca_kern) < 0) {
639 list_add(&tioca_kern->ca_list, &tioca_list);
641 if (request_irq(SGI_TIOCA_ERROR,
642 tioca_error_intr_handler,
643 IRQF_SHARED, "TIOCA error", (void *)tioca_common))
645 "%s: Unable to get irq %d. "
646 "Error interrupts won't be routed for TIOCA bus %d\n",
647 __func__, SGI_TIOCA_ERROR,
648 (int)tioca_common->ca_common.bs_persist_busnum);
650 sn_set_err_irq_affinity(SGI_TIOCA_ERROR);
652 /* Setup locality information */
653 controller->node = tioca_kern->ca_closest_node;
657 static struct sn_pcibus_provider tioca_pci_interfaces = {
658 .dma_map = tioca_dma_map,
659 .dma_map_consistent = tioca_dma_map,
660 .dma_unmap = tioca_dma_unmap,
661 .bus_fixup = tioca_bus_fixup,
662 .force_interrupt = NULL,
663 .target_interrupt = NULL
667 * tioca_init_provider - init SN PCI provider ops for TIO CA
670 tioca_init_provider(void)
672 sn_pci_provider[PCIIO_ASIC_TYPE_TIOCA] = &tioca_pci_interfaces;