2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
25 #include <linux/module.h>
26 #include <linux/init.h>
28 #include <linux/acpi.h>
29 #include <linux/bootmem.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/reboot.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/string.h>
37 #include <linux/threads.h>
38 #include <linux/screen_info.h>
39 #include <linux/dmi.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
45 #include <linux/cpufreq.h>
46 #include <linux/kexec.h>
47 #include <linux/crash_dump.h>
50 #include <asm/machvec.h>
52 #include <asm/meminit.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
58 #include <asm/sections.h>
59 #include <asm/setup.h>
61 #include <asm/system.h>
62 #include <asm/tlbflush.h>
63 #include <asm/unistd.h>
64 #include <asm/hpsim.h>
66 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
67 # error "struct cpuinfo_ia64 too big!"
71 unsigned long __per_cpu_offset[NR_CPUS];
72 EXPORT_SYMBOL(__per_cpu_offset);
75 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
76 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
77 unsigned long ia64_cycles_per_usec;
78 struct ia64_boot_param *ia64_boot_param;
79 struct screen_info screen_info;
80 unsigned long vga_console_iobase;
81 unsigned long vga_console_membase;
83 static struct resource data_resource = {
84 .name = "Kernel data",
85 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
88 static struct resource code_resource = {
89 .name = "Kernel code",
90 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
93 static struct resource bss_resource = {
95 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
98 unsigned long ia64_max_cacheline_size;
100 int dma_get_cache_alignment(void)
102 return ia64_max_cacheline_size;
104 EXPORT_SYMBOL(dma_get_cache_alignment);
106 unsigned long ia64_iobase; /* virtual address for I/O accesses */
107 EXPORT_SYMBOL(ia64_iobase);
108 struct io_space io_space[MAX_IO_SPACES];
109 EXPORT_SYMBOL(io_space);
110 unsigned int num_io_spaces;
113 * "flush_icache_range()" needs to know what processor dependent stride size to use
114 * when it makes i-cache(s) coherent with d-caches.
116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
117 unsigned long ia64_i_cache_stride_shift = ~0;
120 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
121 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
122 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
123 * address of the second buffer must be aligned to (merge_mask+1) in order to be
124 * mergeable). By default, we assume there is no I/O MMU which can merge physically
125 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
128 unsigned long ia64_max_iommu_merge_mask = ~0UL;
129 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
132 * We use a special marker for the end of memory and it uses the extra (+1) slot
134 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
135 int num_rsvd_regions __initdata;
139 * Filter incoming memory segments based on the primitive map created from the boot
140 * parameters. Segments contained in the map are removed from the memory ranges. A
141 * caller-specified function is called with the memory ranges that remain after filtering.
142 * This routine does not assume the incoming segments are sorted.
145 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
147 unsigned long range_start, range_end, prev_start;
148 void (*func)(unsigned long, unsigned long, int);
152 if (start == PAGE_OFFSET) {
153 printk(KERN_WARNING "warning: skipping physical page 0\n");
155 if (start >= end) return 0;
159 * lowest possible address(walker uses virtual)
161 prev_start = PAGE_OFFSET;
164 for (i = 0; i < num_rsvd_regions; ++i) {
165 range_start = max(start, prev_start);
166 range_end = min(end, rsvd_region[i].start);
168 if (range_start < range_end)
169 call_pernode_memory(__pa(range_start), range_end - range_start, func);
171 /* nothing more available in this segment */
172 if (range_end == end) return 0;
174 prev_start = rsvd_region[i].end;
176 /* end of memory marker allows full processing inside loop body */
181 sort_regions (struct rsvd_region *rsvd_region, int max)
185 /* simple bubble sorting */
187 for (j = 0; j < max; ++j) {
188 if (rsvd_region[j].start > rsvd_region[j+1].start) {
189 struct rsvd_region tmp;
190 tmp = rsvd_region[j];
191 rsvd_region[j] = rsvd_region[j + 1];
192 rsvd_region[j + 1] = tmp;
199 * Request address space for all standard resources
201 static int __init register_memory(void)
203 code_resource.start = ia64_tpa(_text);
204 code_resource.end = ia64_tpa(_etext) - 1;
205 data_resource.start = ia64_tpa(_etext);
206 data_resource.end = ia64_tpa(_edata) - 1;
207 bss_resource.start = ia64_tpa(__bss_start);
208 bss_resource.end = ia64_tpa(_end) - 1;
209 efi_initialize_iomem_resources(&code_resource, &data_resource,
215 __initcall(register_memory);
219 static void __init setup_crashkernel(unsigned long total, int *n)
221 unsigned long long base = 0, size = 0;
224 ret = parse_crashkernel(boot_command_line, total,
226 if (ret == 0 && size > 0) {
228 sort_regions(rsvd_region, *n);
229 base = kdump_find_rsvd_region(size,
233 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
234 "for crashkernel (System RAM: %ldMB)\n",
235 (unsigned long)(size >> 20),
236 (unsigned long)(base >> 20),
237 (unsigned long)(total >> 20));
238 rsvd_region[*n].start =
239 (unsigned long)__va(base);
240 rsvd_region[*n].end =
241 (unsigned long)__va(base + size);
243 crashk_res.start = base;
244 crashk_res.end = base + size - 1;
247 efi_memmap_res.start = ia64_boot_param->efi_memmap;
248 efi_memmap_res.end = efi_memmap_res.start +
249 ia64_boot_param->efi_memmap_size;
250 boot_param_res.start = __pa(ia64_boot_param);
251 boot_param_res.end = boot_param_res.start +
252 sizeof(*ia64_boot_param);
255 static inline void __init setup_crashkernel(unsigned long total, int *n)
260 * reserve_memory - setup reserved memory areas
262 * Setup the reserved memory areas set aside for the boot parameters,
263 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
264 * see include/asm-ia64/meminit.h if you need to define more.
267 reserve_memory (void)
270 unsigned long total_memory;
273 * none of the entries in this table overlap
275 rsvd_region[n].start = (unsigned long) ia64_boot_param;
276 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
279 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
280 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
283 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
284 rsvd_region[n].end = (rsvd_region[n].start
285 + strlen(__va(ia64_boot_param->command_line)) + 1);
288 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
289 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
292 #ifdef CONFIG_BLK_DEV_INITRD
293 if (ia64_boot_param->initrd_start) {
294 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
295 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
300 #ifdef CONFIG_PROC_VMCORE
301 if (reserve_elfcorehdr(&rsvd_region[n].start,
302 &rsvd_region[n].end) == 0)
306 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
309 setup_crashkernel(total_memory, &n);
311 /* end of memory marker */
312 rsvd_region[n].start = ~0UL;
313 rsvd_region[n].end = ~0UL;
316 num_rsvd_regions = n;
317 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
319 sort_regions(rsvd_region, num_rsvd_regions);
324 * find_initrd - get initrd parameters from the boot parameter structure
326 * Grab the initrd start and end from the boot parameter struct given us by
332 #ifdef CONFIG_BLK_DEV_INITRD
333 if (ia64_boot_param->initrd_start) {
334 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
335 initrd_end = initrd_start+ia64_boot_param->initrd_size;
337 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
338 initrd_start, ia64_boot_param->initrd_size);
346 unsigned long phys_iobase;
349 * Set `iobase' based on the EFI memory map or, failing that, the
350 * value firmware left in ar.k0.
352 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
353 * the port's virtual address, so ia32_load_state() loads it with a
354 * user virtual address. But in ia64 mode, glibc uses the
355 * *physical* address in ar.k0 to mmap the appropriate area from
356 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
357 * cases, user-mode can only use the legacy 0-64K I/O port space.
359 * ar.k0 is not involved in kernel I/O port accesses, which can use
360 * any of the I/O port spaces and are done via MMIO using the
361 * virtual mmio_base from the appropriate io_space[].
363 phys_iobase = efi_get_iobase();
365 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
366 printk(KERN_INFO "No I/O port range found in EFI memory map, "
367 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
369 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
370 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
372 /* setup legacy IO port space */
373 io_space[0].mmio_base = ia64_iobase;
374 io_space[0].sparse = 1;
379 * early_console_setup - setup debugging console
381 * Consoles started here require little enough setup that we can start using
382 * them very early in the boot process, either right after the machine
383 * vector initialization, or even before if the drivers can detect their hw.
385 * Returns non-zero if a console couldn't be setup.
387 static inline int __init
388 early_console_setup (char *cmdline)
392 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
394 extern int sn_serial_console_early_setup(void);
395 if (!sn_serial_console_early_setup())
399 #ifdef CONFIG_EFI_PCDP
400 if (!efi_setup_pcdp_console(cmdline))
403 if (!simcons_register())
406 return (earlycons) ? 0 : -1;
410 mark_bsp_online (void)
413 /* If we register an early console, allow CPU 0 to printk */
414 cpu_set(smp_processor_id(), cpu_online_map);
418 static __initdata int nomca;
419 static __init int setup_nomca(char *s)
424 early_param("nomca", setup_nomca);
426 #ifdef CONFIG_PROC_VMCORE
427 /* elfcorehdr= specifies the location of elf core header
428 * stored by the crashed kernel.
430 static int __init parse_elfcorehdr(char *arg)
435 elfcorehdr_addr = memparse(arg, &arg);
438 early_param("elfcorehdr", parse_elfcorehdr);
440 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end)
442 unsigned long length;
444 /* We get the address using the kernel command line,
445 * but the size is extracted from the EFI tables.
446 * Both address and size are required for reservation
450 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX)
453 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) {
454 elfcorehdr_addr = ELFCORE_ADDR_MAX;
458 *start = (unsigned long)__va(elfcorehdr_addr);
459 *end = *start + length;
463 #endif /* CONFIG_PROC_VMCORE */
466 setup_arch (char **cmdline_p)
470 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
472 *cmdline_p = __va(ia64_boot_param->command_line);
473 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
478 #ifdef CONFIG_IA64_GENERIC
479 /* machvec needs to be parsed from the command line
480 * before parse_early_param() is called to ensure
481 * that ia64_mv is initialised before any command line
482 * settings may cause console setup to occur
484 machvec_init_from_cmdline(*cmdline_p);
489 if (early_console_setup(*cmdline_p) == 0)
493 /* Initialize the ACPI boot-time table parser */
495 # ifdef CONFIG_ACPI_NUMA
497 per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ?
498 32 : cpus_weight(early_cpu_possible_map)), additional_cpus);
502 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
504 #endif /* CONFIG_APCI_BOOT */
508 /* process SAL system table: */
509 ia64_sal_init(__va(efi.sal_systab));
512 cpu_physical_id(0) = hard_smp_processor_id();
515 cpu_init(); /* initialize the bootstrap CPU */
516 mmu_context_init(); /* initialize context_id bitmap */
518 check_sal_cache_flush();
526 # if defined(CONFIG_DUMMY_CONSOLE)
527 conswitchp = &dummy_con;
529 # if defined(CONFIG_VGA_CONSOLE)
531 * Non-legacy systems may route legacy VGA MMIO range to system
532 * memory. vga_con probes the MMIO hole, so memory looks like
533 * a VGA device to it. The EFI memory map can tell us if it's
534 * memory so we can avoid this problem.
536 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
537 conswitchp = &vga_con;
542 /* enable IA-64 Machine Check Abort Handling unless disabled */
546 platform_setup(cmdline_p);
551 * Display cpu info for all CPUs.
554 show_cpuinfo (struct seq_file *m, void *v)
557 # define lpj c->loops_per_jiffy
558 # define cpunum c->cpu
560 # define lpj loops_per_jiffy
565 const char *feature_name;
567 { 1UL << 0, "branchlong" },
568 { 1UL << 1, "spontaneous deferral"},
569 { 1UL << 2, "16-byte atomic ops" }
571 char features[128], *cp, *sep;
572 struct cpuinfo_ia64 *c = v;
574 unsigned long proc_freq;
579 /* build the feature string: */
580 memcpy(features, "standard", 9);
582 size = sizeof(features);
584 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) {
585 if (mask & feature_bits[i].mask) {
586 cp += snprintf(cp, size, "%s%s", sep,
587 feature_bits[i].feature_name),
589 mask &= ~feature_bits[i].mask;
590 size = sizeof(features) - (cp - features);
593 if (mask && size > 1) {
594 /* print unknown features as a hex value */
595 snprintf(cp, size, "%s0x%lx", sep, mask);
598 proc_freq = cpufreq_quick_get(cpunum);
600 proc_freq = c->proc_freq / 1000;
614 "cpu MHz : %lu.%03lu\n"
615 "itc MHz : %lu.%06lu\n"
616 "BogoMIPS : %lu.%02lu\n",
617 cpunum, c->vendor, c->family, c->model,
618 c->model_name, c->revision, c->archrev,
619 features, c->ppn, c->number,
620 proc_freq / 1000, proc_freq % 1000,
621 c->itc_freq / 1000000, c->itc_freq % 1000000,
622 lpj*HZ/500000, (lpj*HZ/5000) % 100);
624 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
625 if (c->socket_id != -1)
626 seq_printf(m, "physical id: %u\n", c->socket_id);
627 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
631 c->core_id, c->thread_id);
639 c_start (struct seq_file *m, loff_t *pos)
642 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
645 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
649 c_next (struct seq_file *m, void *v, loff_t *pos)
652 return c_start(m, pos);
656 c_stop (struct seq_file *m, void *v)
660 const struct seq_operations cpuinfo_op = {
668 static char brandname[MAX_BRANDS][128];
670 static char * __cpuinit
671 get_model_name(__u8 family, __u8 model)
677 memcpy(brand, "Unknown", 8);
678 if (ia64_pal_get_brand_info(brand)) {
680 memcpy(brand, "Merced", 7);
681 else if (family == 0x1f) switch (model) {
682 case 0: memcpy(brand, "McKinley", 9); break;
683 case 1: memcpy(brand, "Madison", 8); break;
684 case 2: memcpy(brand, "Madison up to 9M cache", 23); break;
687 for (i = 0; i < MAX_BRANDS; i++)
688 if (strcmp(brandname[i], brand) == 0)
690 for (i = 0; i < MAX_BRANDS; i++)
691 if (brandname[i][0] == '\0')
692 return strcpy(brandname[i], brand);
695 "%s: Table overflow. Some processor model information will be missing\n",
700 static void __cpuinit
701 identify_cpu (struct cpuinfo_ia64 *c)
704 unsigned long bits[5];
710 u64 ppn; /* processor serial number */
714 unsigned revision : 8;
717 unsigned archrev : 8;
718 unsigned reserved : 24;
724 pal_vm_info_1_u_t vm1;
725 pal_vm_info_2_u_t vm2;
727 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
729 for (i = 0; i < 5; ++i)
730 cpuid.bits[i] = ia64_get_cpuid(i);
732 memcpy(c->vendor, cpuid.field.vendor, 16);
734 c->cpu = smp_processor_id();
736 /* below default values will be overwritten by identify_siblings()
737 * for Multi-Threading/Multi-Core capable CPUs
739 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
742 identify_siblings(c);
744 if (c->threads_per_core > smp_num_siblings)
745 smp_num_siblings = c->threads_per_core;
747 c->ppn = cpuid.field.ppn;
748 c->number = cpuid.field.number;
749 c->revision = cpuid.field.revision;
750 c->model = cpuid.field.model;
751 c->family = cpuid.field.family;
752 c->archrev = cpuid.field.archrev;
753 c->features = cpuid.field.features;
754 c->model_name = get_model_name(c->family, c->model);
756 status = ia64_pal_vm_summary(&vm1, &vm2);
757 if (status == PAL_STATUS_SUCCESS) {
758 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
759 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
761 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
762 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
766 setup_per_cpu_areas (void)
768 /* start_kernel() requires this... */
769 #ifdef CONFIG_ACPI_HOTPLUG_CPU
770 prefill_possible_map();
775 * Calculate the max. cache line size.
777 * In addition, the minimum of the i-cache stride sizes is calculated for
778 * "flush_icache_range()".
780 static void __cpuinit
781 get_max_cacheline_size (void)
783 unsigned long line_size, max = 1;
784 u64 l, levels, unique_caches;
785 pal_cache_config_info_t cci;
788 status = ia64_pal_cache_summary(&levels, &unique_caches);
790 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
792 max = SMP_CACHE_BYTES;
793 /* Safest setup for "flush_icache_range()" */
794 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
798 for (l = 0; l < levels; ++l) {
799 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
803 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
804 __func__, l, status);
805 max = SMP_CACHE_BYTES;
806 /* The safest setup for "flush_icache_range()" */
807 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
808 cci.pcci_unified = 1;
810 line_size = 1 << cci.pcci_line_size;
813 if (!cci.pcci_unified) {
814 status = ia64_pal_cache_config_info(l,
815 /* cache_type (instruction)= */ 1,
819 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
820 __func__, l, status);
821 /* The safest setup for "flush_icache_range()" */
822 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
825 if (cci.pcci_stride < ia64_i_cache_stride_shift)
826 ia64_i_cache_stride_shift = cci.pcci_stride;
829 if (max > ia64_max_cacheline_size)
830 ia64_max_cacheline_size = max;
834 * cpu_init() initializes state that is per-CPU. This function acts
835 * as a 'CPU state barrier', nothing should get across.
840 extern void __cpuinit ia64_mmu_init (void *);
841 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG;
842 unsigned long num_phys_stacked;
843 pal_vm_info_2_u_t vmi;
844 unsigned int max_ctx;
845 struct cpuinfo_ia64 *cpu_info;
848 cpu_data = per_cpu_init();
851 * insert boot cpu into sibling and core mapes
852 * (must be done after per_cpu area is setup)
854 if (smp_processor_id() == 0) {
855 cpu_set(0, per_cpu(cpu_sibling_map, 0));
856 cpu_set(0, cpu_core_map[0]);
861 * We set ar.k3 so that assembly code in MCA handler can compute
862 * physical addresses of per cpu variables with a simple:
863 * phys = ar.k3 + &per_cpu_var
865 ia64_set_kr(IA64_KR_PER_CPU_DATA,
866 ia64_tpa(cpu_data) - (long) __per_cpu_start);
868 get_max_cacheline_size();
871 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
872 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
873 * depends on the data returned by identify_cpu(). We break the dependency by
874 * accessing cpu_data() through the canonical per-CPU address.
876 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
877 identify_cpu(cpu_info);
879 #ifdef CONFIG_MCKINLEY
881 # define FEATURE_SET 16
882 struct ia64_pal_retval iprv;
884 if (cpu_info->family == 0x1f) {
885 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
886 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
887 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
888 (iprv.v1 | 0x80), FEATURE_SET, 0);
893 /* Clear the stack memory reserved for pt_regs: */
894 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
896 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
899 * Initialize the page-table base register to a global
900 * directory with all zeroes. This ensure that we can handle
901 * TLB-misses to user address-space even before we created the
902 * first user address-space. This may happen, e.g., due to
903 * aggressive use of lfetch.fault.
905 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
908 * Initialize default control register to defer speculative faults except
909 * for those arising from TLB misses, which are not deferred. The
910 * kernel MUST NOT depend on a particular setting of these bits (in other words,
911 * the kernel must have recovery code for all speculative accesses). Turn on
912 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
913 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
916 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
917 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
918 atomic_inc(&init_mm.mm_count);
919 current->active_mm = &init_mm;
923 ia64_mmu_init(ia64_imva(cpu_data));
924 ia64_mca_cpu_init(ia64_imva(cpu_data));
926 #ifdef CONFIG_IA32_SUPPORT
930 /* Clear ITC to eliminate sched_clock() overflows in human time. */
933 /* disable all local interrupt sources: */
934 ia64_set_itv(1 << 16);
935 ia64_set_lrr0(1 << 16);
936 ia64_set_lrr1(1 << 16);
937 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
938 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
940 /* clear TPR & XTP to enable all interrupt classes: */
941 ia64_setreg(_IA64_REG_CR_TPR, 0);
943 /* Clear any pending interrupts left by SAL/EFI */
944 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR)
951 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
952 if (ia64_pal_vm_summary(NULL, &vmi) == 0) {
953 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
954 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL);
956 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
957 max_ctx = (1U << 15) - 1; /* use architected minimum */
959 while (max_ctx < ia64_ctx.max_ctx) {
960 unsigned int old = ia64_ctx.max_ctx;
961 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
965 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
966 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
968 num_phys_stacked = 96;
970 /* size of physical stacked register partition plus 8 bytes: */
971 if (num_phys_stacked > max_num_phys_stacked) {
972 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8);
973 max_num_phys_stacked = num_phys_stacked;
976 pm_idle = default_idle;
982 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
983 (unsigned long) __end___mckinley_e9_bundles);
986 static int __init run_dmi_scan(void)
991 core_initcall(run_dmi_scan);