2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/bitmap.h>
21 /* aperture is up to 256MB but BIOS may reserve less */
22 #define MMCONFIG_APER_MIN (2 * 1024*1024)
23 #define MMCONFIG_APER_MAX (256 * 1024*1024)
25 /* Verify the first 16 busses. We assume that systems with more busses
27 #define PCI_MMCFG_MAX_CHECK_BUS 16
29 DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
31 /* K8 systems have some devices (typically in the builtin northbridge)
32 that are only accessible using type1
33 Normally this can be expressed in the MCFG by not listing them
34 and assigning suitable _SEGs, but this isn't implemented in some BIOS.
35 Instead try to discover all devices on bus 0 that are unreachable using MM
36 and fallback for them. */
37 static __init void unreachable_devices(void)
40 /* Use the max bus number from ACPI here? */
41 for (k = 0; k < PCI_MMCFG_MAX_CHECK_BUS; k++) {
42 for (i = 0; i < 32; i++) {
45 pci_conf1_read(0, k, PCI_DEVFN(i,0), 0, 4, &val1);
46 if (val1 == 0xffffffff)
49 raw_pci_ops->read(0, k, PCI_DEVFN(i, 0), 0, 4, &val2);
51 set_bit(i + 32*k, pci_mmcfg_fallback_slots);
52 printk(KERN_NOTICE "PCI: No mmconfig possible"
53 " on device %02x:%02x\n", k, i);
59 static __init const char *pci_mmcfg_e7520(void)
62 pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);
64 pci_mmcfg_config_num = 1;
65 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
66 if (!pci_mmcfg_config)
68 pci_mmcfg_config[0].address = (win & 0xf000) << 16;
69 pci_mmcfg_config[0].pci_segment = 0;
70 pci_mmcfg_config[0].start_bus_number = 0;
71 pci_mmcfg_config[0].end_bus_number = 255;
73 return "Intel Corporation E7520 Memory Controller Hub";
76 static __init const char *pci_mmcfg_intel_945(void)
78 u32 pciexbar, mask = 0, len = 0;
80 pci_mmcfg_config_num = 1;
82 pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);
86 pci_mmcfg_config_num = 0;
89 switch ((pciexbar >> 1) & 3) {
103 pci_mmcfg_config_num = 0;
106 /* Errata #2, things break when not aligned on a 256Mb boundary */
107 /* Can only happen in 64M/128M mode */
109 if ((pciexbar & mask) & 0x0fffffffU)
110 pci_mmcfg_config_num = 0;
112 if (pci_mmcfg_config_num) {
113 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
114 if (!pci_mmcfg_config)
116 pci_mmcfg_config[0].address = pciexbar & mask;
117 pci_mmcfg_config[0].pci_segment = 0;
118 pci_mmcfg_config[0].start_bus_number = 0;
119 pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
122 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
125 struct pci_mmcfg_hostbridge_probe {
128 const char *(*probe)(void);
131 static __initdata struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] = {
132 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
133 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
136 static int __init pci_mmcfg_check_hostbridge(void)
143 pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0, 4, &l);
145 device = (l >> 16) & 0xffff;
147 pci_mmcfg_config_num = 0;
148 pci_mmcfg_config = NULL;
151 for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++)
152 if ((pci_mmcfg_probes[i].vendor == PCI_ANY_ID ||
153 pci_mmcfg_probes[i].vendor == vendor) &&
154 (pci_mmcfg_probes[i].device == PCI_ANY_ID ||
155 pci_mmcfg_probes[i].device == device))
156 name = pci_mmcfg_probes[i].probe();
159 if (pci_mmcfg_config_num)
160 printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n", name);
162 printk(KERN_INFO "PCI: Found %s without MMCONFIG support.\n",
169 static __init void pci_mmcfg_insert_resources(void)
171 #define PCI_MMCFG_RESOURCE_NAME_LEN 19
173 struct resource *res;
177 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
178 pci_mmcfg_config_num, GFP_KERNEL);
181 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
185 names = (void *)&res[pci_mmcfg_config_num];
186 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
187 num_buses = pci_mmcfg_config[i].end_bus_number -
188 pci_mmcfg_config[i].start_bus_number + 1;
190 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
191 pci_mmcfg_config[i].pci_segment);
192 res->start = pci_mmcfg_config[i].address;
193 res->end = res->start + (num_buses << 20) - 1;
194 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
195 insert_resource(&iomem_resource, res);
196 names += PCI_MMCFG_RESOURCE_NAME_LEN;
200 static void __init pci_mmcfg_reject_broken(void)
202 typeof(pci_mmcfg_config[0]) *cfg = &pci_mmcfg_config[0];
205 * Handle more broken MCFG tables on Asus etc.
206 * They only contain a single entry for bus 0-0.
208 if (pci_mmcfg_config_num == 1 &&
209 cfg->pci_segment == 0 &&
210 (cfg->start_bus_number | cfg->end_bus_number) == 0) {
211 kfree(pci_mmcfg_config);
212 pci_mmcfg_config = NULL;
213 pci_mmcfg_config_num = 0;
215 printk(KERN_ERR "PCI: start and end of bus number is 0. "
216 "Rejected as broken MCFG.");
220 void __init pci_mmcfg_init(int type)
222 int known_bridge = 0;
224 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
227 if (type == 1 && pci_mmcfg_check_hostbridge())
231 acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
232 pci_mmcfg_reject_broken();
235 if ((pci_mmcfg_config_num == 0) ||
236 (pci_mmcfg_config == NULL) ||
237 (pci_mmcfg_config[0].address == 0))
240 /* Only do this check when type 1 works. If it doesn't work
241 assume we run on a Mac and always use MCFG */
242 if (type == 1 && !known_bridge &&
243 !e820_all_mapped(pci_mmcfg_config[0].address,
244 pci_mmcfg_config[0].address + MMCONFIG_APER_MIN,
246 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not E820-reserved\n",
247 pci_mmcfg_config[0].address);
248 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
252 if (pci_mmcfg_arch_init()) {
254 unreachable_devices();
256 pci_mmcfg_insert_resources();
257 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;