arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/compiler.h>
  32 #include <linux/acpi.h>
  33 #include <linux/module.h>
  34 #include <linux/sysdev.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40 #include <asm/i8259.h>
  41 #include <asm/nmi.h>
  42
  43 #include <mach_apic.h>
  44
  45 #include "io_ports.h"
  46
  47 int (*ioapic_renumber_irq)(int ioapic, int irq);
  48 atomic_t irq_mis_count;
  49
  50 /* Where if anywhere is the i8259 connect in external int mode */
  51 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  52
  53 static DEFINE_SPINLOCK(ioapic_lock);
  54 static DEFINE_SPINLOCK(vector_lock);
  55
  56 int timer_over_8254 __initdata = 1;
  57
  58 /*
  59  *      Is the SiS APIC rmw bug present ?
  60  *      -1 = don't know, 0 = no, 1 = yes
  61  */
  62 int sis_apic_bug = -1;
  63
  64 /*
  65  * # of IRQ routing registers
  66  */
  67 int nr_ioapic_registers[MAX_IO_APICS];
  68
  69 int disable_timer_pin_1 __initdata;
  70
  71 /*
  72  * Rough estimation of how many shared IRQs there are, can
  73  * be changed anytime.
  74  */
  75 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  76 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  77
  78 /*
  79  * This is performance-critical, we want to do it O(1)
  80  *
  81  * the indexing order of this array favors 1:1 mappings
  82  * between pins and IRQs.
  83  */
  84
  85 static struct irq_pin_list {
  86         int apic, pin, next;
  87 } irq_2_pin[PIN_MAP_SIZE];
  88
  89 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  90 #ifdef CONFIG_PCI_MSI
  91 #define vector_to_irq(vector)   \
  92         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  93 #else
  94 #define vector_to_irq(vector)   (vector)
  95 #endif
  96
  97 /*
  98  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  99  * shared ISA-space IRQs, so we have to support them. We are super
 100  * fast in the common case, and fast for shared ISA-space IRQs.
 101  */
 102 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 103 {
 104         static int first_free_entry = NR_IRQS;
 105         struct irq_pin_list *entry = irq_2_pin + irq;
 106
 107         while (entry->next)
 108                 entry = irq_2_pin + entry->next;
 109
 110         if (entry->pin != -1) {
 111                 entry->next = first_free_entry;
 112                 entry = irq_2_pin + entry->next;
 113                 if (++first_free_entry >= PIN_MAP_SIZE)
 114                         panic("io_apic.c: whoops");
 115         }
 116         entry->apic = apic;
 117         entry->pin = pin;
 118 }
 119
 120 /*
 121  * Reroute an IRQ to a different pin.
 122  */
 123 static void __init replace_pin_at_irq(unsigned int irq,
 124                                       int oldapic, int oldpin,
 125                                       int newapic, int newpin)
 126 {
 127         struct irq_pin_list *entry = irq_2_pin + irq;
 128
 129         while (1) {
 130                 if (entry->apic == oldapic && entry->pin == oldpin) {
 131                         entry->apic = newapic;
 132                         entry->pin = newpin;
 133                 }
 134                 if (!entry->next)
 135                         break;
 136                 entry = irq_2_pin + entry->next;
 137         }
 138 }
 139
 140 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 141 {
 142         struct irq_pin_list *entry = irq_2_pin + irq;
 143         unsigned int pin, reg;
 144
 145         for (;;) {
 146                 pin = entry->pin;
 147                 if (pin == -1)
 148                         break;
 149                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 150                 reg &= ~disable;
 151                 reg |= enable;
 152                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 153                 if (!entry->next)
 154                         break;
 155                 entry = irq_2_pin + entry->next;
 156         }
 157 }
 158
 159 /* mask = 1 */
 160 static void __mask_IO_APIC_irq (unsigned int irq)
 161 {
 162         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 163 }
 164
 165 /* mask = 0 */
 166 static void __unmask_IO_APIC_irq (unsigned int irq)
 167 {
 168         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 169 }
 170
 171 /* mask = 1, trigger = 0 */
 172 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 173 {
 174         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 175 }
 176
 177 /* mask = 0, trigger = 1 */
 178 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 179 {
 180         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 181 }
 182
 183 static void mask_IO_APIC_irq (unsigned int irq)
 184 {
 185         unsigned long flags;
 186
 187         spin_lock_irqsave(&ioapic_lock, flags);
 188         __mask_IO_APIC_irq(irq);
 189         spin_unlock_irqrestore(&ioapic_lock, flags);
 190 }
 191
 192 static void unmask_IO_APIC_irq (unsigned int irq)
 193 {
 194         unsigned long flags;
 195
 196         spin_lock_irqsave(&ioapic_lock, flags);
 197         __unmask_IO_APIC_irq(irq);
 198         spin_unlock_irqrestore(&ioapic_lock, flags);
 199 }
 200
 201 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 202 {
 203         struct IO_APIC_route_entry entry;
 204         unsigned long flags;
 205
 206         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 207         spin_lock_irqsave(&ioapic_lock, flags);
 208         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 209         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 210         spin_unlock_irqrestore(&ioapic_lock, flags);
 211         if (entry.delivery_mode == dest_SMI)
 212                 return;
 213
 214         /*
 215          * Disable it in the IO-APIC irq-routing table:
 216          */
 217         memset(&entry, 0, sizeof(entry));
 218         entry.mask = 1;
 219         spin_lock_irqsave(&ioapic_lock, flags);
 220         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 221         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 222         spin_unlock_irqrestore(&ioapic_lock, flags);
 223 }
 224
 225 static void clear_IO_APIC (void)
 226 {
 227         int apic, pin;
 228
 229         for (apic = 0; apic < nr_ioapics; apic++)
 230                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 231                         clear_IO_APIC_pin(apic, pin);
 232 }
 233
 234 #ifdef CONFIG_SMP
 235 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 236 {
 237         unsigned long flags;
 238         int pin;
 239         struct irq_pin_list *entry = irq_2_pin + irq;
 240         unsigned int apicid_value;
 241         cpumask_t tmp;
 242
 243         cpus_and(tmp, cpumask, cpu_online_map);
 244         if (cpus_empty(tmp))
 245                 tmp = TARGET_CPUS;
 246
 247         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 248
 249         apicid_value = cpu_mask_to_apicid(cpumask);
 250         /* Prepare to do the io_apic_write */
 251         apicid_value = apicid_value << 24;
 252         spin_lock_irqsave(&ioapic_lock, flags);
 253         for (;;) {
 254                 pin = entry->pin;
 255                 if (pin == -1)
 256                         break;
 257                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 258                 if (!entry->next)
 259                         break;
 260                 entry = irq_2_pin + entry->next;
 261         }
 262         set_irq_info(irq, cpumask);
 263         spin_unlock_irqrestore(&ioapic_lock, flags);
 264 }
 265
 266 #if defined(CONFIG_IRQBALANCE)
 267 # include <asm/processor.h>     /* kernel_thread() */
 268 # include <linux/kernel_stat.h> /* kstat */
 269 # include <linux/slab.h>                /* kmalloc() */
 270 # include <linux/timer.h>       /* time_after() */
 271
 272 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 273 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 274 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 275 # else
 276 #  define TDprintk(x...)
 277 #  define Dprintk(x...)
 278 # endif
 279
 280 #define IRQBALANCE_CHECK_ARCH -999
 281 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 282 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 283 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 284 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 285
 286 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 287 static int physical_balance __read_mostly;
 288 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 289
 290 static struct irq_cpu_info {
 291         unsigned long * last_irq;
 292         unsigned long * irq_delta;
 293         unsigned long irq;
 294 } irq_cpu_data[NR_CPUS];
 295
 296 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 297 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 298 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 299
 300 #define IDLE_ENOUGH(cpu,now) \
 301         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 302
 303 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 304
 305 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 306
 307 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 308         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 309 };
 310
 311 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 312 {
 313         balance_irq_affinity[irq] = mask;
 314 }
 315
 316 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 317                         unsigned long now, int direction)
 318 {
 319         int search_idle = 1;
 320         int cpu = curr_cpu;
 321
 322         goto inside;
 323
 324         do {
 325                 if (unlikely(cpu == curr_cpu))
 326                         search_idle = 0;
 327 inside:
 328                 if (direction == 1) {
 329                         cpu++;
 330                         if (cpu >= NR_CPUS)
 331                                 cpu = 0;
 332                 } else {
 333                         cpu--;
 334                         if (cpu == -1)
 335                                 cpu = NR_CPUS-1;
 336                 }
 337         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 338                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 339
 340         return cpu;
 341 }
 342
 343 static inline void balance_irq(int cpu, int irq)
 344 {
 345         unsigned long now = jiffies;
 346         cpumask_t allowed_mask;
 347         unsigned int new_cpu;
 348
 349         if (irqbalance_disabled)
 350                 return;
 351
 352         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 353         new_cpu = move(cpu, allowed_mask, now, 1);
 354         if (cpu != new_cpu) {
 355                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 356         }
 357 }
 358
 359 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 360 {
 361         int i, j;
 362         Dprintk("Rotating IRQs among CPUs.\n");
 363         for_each_online_cpu(i) {
 364                 for (j = 0; j < NR_IRQS; j++) {
 365                         if (!irq_desc[j].action)
 366                                 continue;
 367                         /* Is it a significant load ?  */
 368                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 369                                                 useful_load_threshold)
 370                                 continue;
 371                         balance_irq(i, j);
 372                 }
 373         }
 374         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 375                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 376         return;
 377 }
 378
 379 static void do_irq_balance(void)
 380 {
 381         int i, j;
 382         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 383         unsigned long move_this_load = 0;
 384         int max_loaded = 0, min_loaded = 0;
 385         int load;
 386         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 387         int selected_irq;
 388         int tmp_loaded, first_attempt = 1;
 389         unsigned long tmp_cpu_irq;
 390         unsigned long imbalance = 0;
 391         cpumask_t allowed_mask, target_cpu_mask, tmp;
 392
 393         for_each_possible_cpu(i) {
 394                 int package_index;
 395                 CPU_IRQ(i) = 0;
 396                 if (!cpu_online(i))
 397                         continue;
 398                 package_index = CPU_TO_PACKAGEINDEX(i);
 399                 for (j = 0; j < NR_IRQS; j++) {
 400                         unsigned long value_now, delta;
 401                         /* Is this an active IRQ? */
 402                         if (!irq_desc[j].action)
 403                                 continue;
 404                         if ( package_index == i )
 405                                 IRQ_DELTA(package_index,j) = 0;
 406                         /* Determine the total count per processor per IRQ */
 407                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 408
 409                         /* Determine the activity per processor per IRQ */
 410                         delta = value_now - LAST_CPU_IRQ(i,j);
 411
 412                         /* Update last_cpu_irq[][] for the next time */
 413                         LAST_CPU_IRQ(i,j) = value_now;
 414
 415                         /* Ignore IRQs whose rate is less than the clock */
 416                         if (delta < useful_load_threshold)
 417                                 continue;
 418                         /* update the load for the processor or package total */
 419                         IRQ_DELTA(package_index,j) += delta;
 420
 421                         /* Keep track of the higher numbered sibling as well */
 422                         if (i != package_index)
 423                                 CPU_IRQ(i) += delta;
 424                         /*
 425                          * We have sibling A and sibling B in the package
 426                          *
 427                          * cpu_irq[A] = load for cpu A + load for cpu B
 428                          * cpu_irq[B] = load for cpu B
 429                          */
 430                         CPU_IRQ(package_index) += delta;
 431                 }
 432         }
 433         /* Find the least loaded processor package */
 434         for_each_online_cpu(i) {
 435                 if (i != CPU_TO_PACKAGEINDEX(i))
 436                         continue;
 437                 if (min_cpu_irq > CPU_IRQ(i)) {
 438                         min_cpu_irq = CPU_IRQ(i);
 439                         min_loaded = i;
 440                 }
 441         }
 442         max_cpu_irq = ULONG_MAX;
 443
 444 tryanothercpu:
 445         /* Look for heaviest loaded processor.
 446          * We may come back to get the next heaviest loaded processor.
 447          * Skip processors with trivial loads.
 448          */
 449         tmp_cpu_irq = 0;
 450         tmp_loaded = -1;
 451         for_each_online_cpu(i) {
 452                 if (i != CPU_TO_PACKAGEINDEX(i))
 453                         continue;
 454                 if (max_cpu_irq <= CPU_IRQ(i))
 455                         continue;
 456                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 457                         tmp_cpu_irq = CPU_IRQ(i);
 458                         tmp_loaded = i;
 459                 }
 460         }
 461
 462         if (tmp_loaded == -1) {
 463          /* In the case of small number of heavy interrupt sources,
 464           * loading some of the cpus too much. We use Ingo's original
 465           * approach to rotate them around.
 466           */
 467                 if (!first_attempt && imbalance >= useful_load_threshold) {
 468                         rotate_irqs_among_cpus(useful_load_threshold);
 469                         return;
 470                 }
 471                 goto not_worth_the_effort;
 472         }
 473
 474         first_attempt = 0;              /* heaviest search */
 475         max_cpu_irq = tmp_cpu_irq;      /* load */
 476         max_loaded = tmp_loaded;        /* processor */
 477         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 478
 479         Dprintk("max_loaded cpu = %d\n", max_loaded);
 480         Dprintk("min_loaded cpu = %d\n", min_loaded);
 481         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 482         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 483         Dprintk("load imbalance = %lu\n", imbalance);
 484
 485         /* if imbalance is less than approx 10% of max load, then
 486          * observe diminishing returns action. - quit
 487          */
 488         if (imbalance < (max_cpu_irq >> 3)) {
 489                 Dprintk("Imbalance too trivial\n");
 490                 goto not_worth_the_effort;
 491         }
 492
 493 tryanotherirq:
 494         /* if we select an IRQ to move that can't go where we want, then
 495          * see if there is another one to try.
 496          */
 497         move_this_load = 0;
 498         selected_irq = -1;
 499         for (j = 0; j < NR_IRQS; j++) {
 500                 /* Is this an active IRQ? */
 501                 if (!irq_desc[j].action)
 502                         continue;
 503                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 504                         continue;
 505                 /* Try to find the IRQ that is closest to the imbalance
 506                  * without going over.
 507                  */
 508                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 509                         move_this_load = IRQ_DELTA(max_loaded,j);
 510                         selected_irq = j;
 511                 }
 512         }
 513         if (selected_irq == -1) {
 514                 goto tryanothercpu;
 515         }
 516
 517         imbalance = move_this_load;
 518
 519         /* For physical_balance case, we accumlated both load
 520          * values in the one of the siblings cpu_irq[],
 521          * to use the same code for physical and logical processors
 522          * as much as possible.
 523          *
 524          * NOTE: the cpu_irq[] array holds the sum of the load for
 525          * sibling A and sibling B in the slot for the lowest numbered
 526          * sibling (A), _AND_ the load for sibling B in the slot for
 527          * the higher numbered sibling.
 528          *
 529          * We seek the least loaded sibling by making the comparison
 530          * (A+B)/2 vs B
 531          */
 532         load = CPU_IRQ(min_loaded) >> 1;
 533         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 534                 if (load > CPU_IRQ(j)) {
 535                         /* This won't change cpu_sibling_map[min_loaded] */
 536                         load = CPU_IRQ(j);
 537                         min_loaded = j;
 538                 }
 539         }
 540
 541         cpus_and(allowed_mask,
 542                 cpu_online_map,
 543                 balance_irq_affinity[selected_irq]);
 544         target_cpu_mask = cpumask_of_cpu(min_loaded);
 545         cpus_and(tmp, target_cpu_mask, allowed_mask);
 546
 547         if (!cpus_empty(tmp)) {
 548
 549                 Dprintk("irq = %d moved to cpu = %d\n",
 550                                 selected_irq, min_loaded);
 551                 /* mark for change destination */
 552                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 553
 554                 /* Since we made a change, come back sooner to
 555                  * check for more variation.
 556                  */
 557                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 558                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 559                 return;
 560         }
 561         goto tryanotherirq;
 562
 563 not_worth_the_effort:
 564         /*
 565          * if we did not find an IRQ to move, then adjust the time interval
 566          * upward
 567          */
 568         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 569                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 570         Dprintk("IRQ worth rotating not found\n");
 571         return;
 572 }
 573
 574 static int balanced_irq(void *unused)
 575 {
 576         int i;
 577         unsigned long prev_balance_time = jiffies;
 578         long time_remaining = balanced_irq_interval;
 579
 580         daemonize("kirqd");
 581
 582         /* push everything to CPU 0 to give us a starting point.  */
 583         for (i = 0 ; i < NR_IRQS ; i++) {
 584                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 585                 set_pending_irq(i, cpumask_of_cpu(0));
 586         }
 587
 588         for ( ; ; ) {
 589                 time_remaining = schedule_timeout_interruptible(time_remaining);
 590                 try_to_freeze();
 591                 if (time_after(jiffies,
 592                                 prev_balance_time+balanced_irq_interval)) {
 593                         preempt_disable();
 594                         do_irq_balance();
 595                         prev_balance_time = jiffies;
 596                         time_remaining = balanced_irq_interval;
 597                         preempt_enable();
 598                 }
 599         }
 600         return 0;
 601 }
 602
 603 static int __init balanced_irq_init(void)
 604 {
 605         int i;
 606         struct cpuinfo_x86 *c;
 607         cpumask_t tmp;
 608
 609         cpus_shift_right(tmp, cpu_online_map, 2);
 610         c = &boot_cpu_data;
 611         /* When not overwritten by the command line ask subarchitecture. */
 612         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 613                 irqbalance_disabled = NO_BALANCE_IRQ;
 614         if (irqbalance_disabled)
 615                 return 0;
 616
 617          /* disable irqbalance completely if there is only one processor online */
 618         if (num_online_cpus() < 2) {
 619                 irqbalance_disabled = 1;
 620                 return 0;
 621         }
 622         /*
 623          * Enable physical balance only if more than 1 physical processor
 624          * is present
 625          */
 626         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 627                 physical_balance = 1;
 628
 629         for_each_online_cpu(i) {
 630                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 631                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 632                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 633                         printk(KERN_ERR "balanced_irq_init: out of memory");
 634                         goto failed;
 635                 }
 636                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 637                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 638         }
 639
 640         printk(KERN_INFO "Starting balanced_irq\n");
 641         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 642                 return 0;
 643         else
 644                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 645 failed:
 646         for_each_possible_cpu(i) {
 647                 kfree(irq_cpu_data[i].irq_delta);
 648                 irq_cpu_data[i].irq_delta = NULL;
 649                 kfree(irq_cpu_data[i].last_irq);
 650                 irq_cpu_data[i].last_irq = NULL;
 651         }
 652         return 0;
 653 }
 654
 655 int __init irqbalance_disable(char *str)
 656 {
 657         irqbalance_disabled = 1;
 658         return 1;
 659 }
 660
 661 __setup("noirqbalance", irqbalance_disable);
 662
 663 late_initcall(balanced_irq_init);
 664 #endif /* CONFIG_IRQBALANCE */
 665 #endif /* CONFIG_SMP */
 666
 667 #ifndef CONFIG_SMP
 668 void fastcall send_IPI_self(int vector)
 669 {
 670         unsigned int cfg;
 671
 672         /*
 673          * Wait for idle.
 674          */
 675         apic_wait_icr_idle();
 676         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 677         /*
 678          * Send the IPI. The write to APIC_ICR fires this off.
 679          */
 680         apic_write_around(APIC_ICR, cfg);
 681 }
 682 #endif /* !CONFIG_SMP */
 683
 684
 685 /*
 686  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 687  * specific CPU-side IRQs.
 688  */
 689
 690 #define MAX_PIRQS 8
 691 static int pirq_entries [MAX_PIRQS];
 692 static int pirqs_enabled;
 693 int skip_ioapic_setup;
 694
 695 static int __init ioapic_setup(char *str)
 696 {
 697         skip_ioapic_setup = 1;
 698         return 1;
 699 }
 700
 701 __setup("noapic", ioapic_setup);
 702
 703 static int __init ioapic_pirq_setup(char *str)
 704 {
 705         int i, max;
 706         int ints[MAX_PIRQS+1];
 707
 708         get_options(str, ARRAY_SIZE(ints), ints);
 709
 710         for (i = 0; i < MAX_PIRQS; i++)
 711                 pirq_entries[i] = -1;
 712
 713         pirqs_enabled = 1;
 714         apic_printk(APIC_VERBOSE, KERN_INFO
 715                         "PIRQ redirection, working around broken MP-BIOS.\n");
 716         max = MAX_PIRQS;
 717         if (ints[0] < MAX_PIRQS)
 718                 max = ints[0];
 719
 720         for (i = 0; i < max; i++) {
 721                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 722                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 723                 /*
 724                  * PIRQs are mapped upside down, usually.
 725                  */
 726                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 727         }
 728         return 1;
 729 }
 730
 731 __setup("pirq=", ioapic_pirq_setup);
 732
 733 /*
 734  * Find the IRQ entry number of a certain pin.
 735  */
 736 static int find_irq_entry(int apic, int pin, int type)
 737 {
 738         int i;
 739
 740         for (i = 0; i < mp_irq_entries; i++)
 741                 if (mp_irqs[i].mpc_irqtype == type &&
 742                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 743                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 744                     mp_irqs[i].mpc_dstirq == pin)
 745                         return i;
 746
 747         return -1;
 748 }
 749
 750 /*
 751  * Find the pin to which IRQ[irq] (ISA) is connected
 752  */
 753 static int __init find_isa_irq_pin(int irq, int type)
 754 {
 755         int i;
 756
 757         for (i = 0; i < mp_irq_entries; i++) {
 758                 int lbus = mp_irqs[i].mpc_srcbus;
 759
 760                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 761                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 762                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 763                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 764                     ) &&
 765                     (mp_irqs[i].mpc_irqtype == type) &&
 766                     (mp_irqs[i].mpc_srcbusirq == irq))
 767
 768                         return mp_irqs[i].mpc_dstirq;
 769         }
 770         return -1;
 771 }
 772
 773 static int __init find_isa_irq_apic(int irq, int type)
 774 {
 775         int i;
 776
 777         for (i = 0; i < mp_irq_entries; i++) {
 778                 int lbus = mp_irqs[i].mpc_srcbus;
 779
 780                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 781                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 782                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 783                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 784                     ) &&
 785                     (mp_irqs[i].mpc_irqtype == type) &&
 786                     (mp_irqs[i].mpc_srcbusirq == irq))
 787                         break;
 788         }
 789         if (i < mp_irq_entries) {
 790                 int apic;
 791                 for(apic = 0; apic < nr_ioapics; apic++) {
 792                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 793                                 return apic;
 794                 }
 795         }
 796
 797         return -1;
 798 }
 799
 800 /*
 801  * Find a specific PCI IRQ entry.
 802  * Not an __init, possibly needed by modules
 803  */
 804 static int pin_2_irq(int idx, int apic, int pin);
 805
 806 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 807 {
 808         int apic, i, best_guess = -1;
 809
 810         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 811                 "slot:%d, pin:%d.\n", bus, slot, pin);
 812         if (mp_bus_id_to_pci_bus[bus] == -1) {
 813                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 814                 return -1;
 815         }
 816         for (i = 0; i < mp_irq_entries; i++) {
 817                 int lbus = mp_irqs[i].mpc_srcbus;
 818
 819                 for (apic = 0; apic < nr_ioapics; apic++)
 820                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 821                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 822                                 break;
 823
 824                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 825                     !mp_irqs[i].mpc_irqtype &&
 826                     (bus == lbus) &&
 827                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 828                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 829
 830                         if (!(apic || IO_APIC_IRQ(irq)))
 831                                 continue;
 832
 833                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 834                                 return irq;
 835                         /*
 836                          * Use the first all-but-pin matching entry as a
 837                          * best-guess fuzzy result for broken mptables.
 838                          */
 839                         if (best_guess < 0)
 840                                 best_guess = irq;
 841                 }
 842         }
 843         return best_guess;
 844 }
 845 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 846
 847 /*
 848  * This function currently is only a helper for the i386 smp boot process where
 849  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 850  * so mask in all cases should simply be TARGET_CPUS
 851  */
 852 #ifdef CONFIG_SMP
 853 void __init setup_ioapic_dest(void)
 854 {
 855         int pin, ioapic, irq, irq_entry;
 856
 857         if (skip_ioapic_setup == 1)
 858                 return;
 859
 860         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 861                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 862                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 863                         if (irq_entry == -1)
 864                                 continue;
 865                         irq = pin_2_irq(irq_entry, ioapic, pin);
 866                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 867                 }
 868
 869         }
 870 }
 871 #endif
 872
 873 /*
 874  * EISA Edge/Level control register, ELCR
 875  */
 876 static int EISA_ELCR(unsigned int irq)
 877 {
 878         if (irq < 16) {
 879                 unsigned int port = 0x4d0 + (irq >> 3);
 880                 return (inb(port) >> (irq & 7)) & 1;
 881         }
 882         apic_printk(APIC_VERBOSE, KERN_INFO
 883                         "Broken MPtable reports ISA irq %d\n", irq);
 884         return 0;
 885 }
 886
 887 /* EISA interrupts are always polarity zero and can be edge or level
 888  * trigger depending on the ELCR value.  If an interrupt is listed as
 889  * EISA conforming in the MP table, that means its trigger type must
 890  * be read in from the ELCR */
 891
 892 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 893 #define default_EISA_polarity(idx)      (0)
 894
 895 /* ISA interrupts are always polarity zero edge triggered,
 896  * when listed as conforming in the MP table. */
 897
 898 #define default_ISA_trigger(idx)        (0)
 899 #define default_ISA_polarity(idx)       (0)
 900
 901 /* PCI interrupts are always polarity one level triggered,
 902  * when listed as conforming in the MP table. */
 903
 904 #define default_PCI_trigger(idx)        (1)
 905 #define default_PCI_polarity(idx)       (1)
 906
 907 /* MCA interrupts are always polarity zero level triggered,
 908  * when listed as conforming in the MP table. */
 909
 910 #define default_MCA_trigger(idx)        (1)
 911 #define default_MCA_polarity(idx)       (0)
 912
 913 /* NEC98 interrupts are always polarity zero edge triggered,
 914  * when listed as conforming in the MP table. */
 915
 916 #define default_NEC98_trigger(idx)     (0)
 917 #define default_NEC98_polarity(idx)    (0)
 918
 919 static int __init MPBIOS_polarity(int idx)
 920 {
 921         int bus = mp_irqs[idx].mpc_srcbus;
 922         int polarity;
 923
 924         /*
 925          * Determine IRQ line polarity (high active or low active):
 926          */
 927         switch (mp_irqs[idx].mpc_irqflag & 3)
 928         {
 929                 case 0: /* conforms, ie. bus-type dependent polarity */
 930                 {
 931                         switch (mp_bus_id_to_type[bus])
 932                         {
 933                                 case MP_BUS_ISA: /* ISA pin */
 934                                 {
 935                                         polarity = default_ISA_polarity(idx);
 936                                         break;
 937                                 }
 938                                 case MP_BUS_EISA: /* EISA pin */
 939                                 {
 940                                         polarity = default_EISA_polarity(idx);
 941                                         break;
 942                                 }
 943                                 case MP_BUS_PCI: /* PCI pin */
 944                                 {
 945                                         polarity = default_PCI_polarity(idx);
 946                                         break;
 947                                 }
 948                                 case MP_BUS_MCA: /* MCA pin */
 949                                 {
 950                                         polarity = default_MCA_polarity(idx);
 951                                         break;
 952                                 }
 953                                 case MP_BUS_NEC98: /* NEC 98 pin */
 954                                 {
 955                                         polarity = default_NEC98_polarity(idx);
 956                                         break;
 957                                 }
 958                                 default:
 959                                 {
 960                                         printk(KERN_WARNING "broken BIOS!!\n");
 961                                         polarity = 1;
 962                                         break;
 963                                 }
 964                         }
 965                         break;
 966                 }
 967                 case 1: /* high active */
 968                 {
 969                         polarity = 0;
 970                         break;
 971                 }
 972                 case 2: /* reserved */
 973                 {
 974                         printk(KERN_WARNING "broken BIOS!!\n");
 975                         polarity = 1;
 976                         break;
 977                 }
 978                 case 3: /* low active */
 979                 {
 980                         polarity = 1;
 981                         break;
 982                 }
 983                 default: /* invalid */
 984                 {
 985                         printk(KERN_WARNING "broken BIOS!!\n");
 986                         polarity = 1;
 987                         break;
 988                 }
 989         }
 990         return polarity;
 991 }
 992
 993 static int MPBIOS_trigger(int idx)
 994 {
 995         int bus = mp_irqs[idx].mpc_srcbus;
 996         int trigger;
 997
 998         /*
 999          * Determine IRQ trigger mode (edge or level sensitive):
1000          */
1001         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1002         {
1003                 case 0: /* conforms, ie. bus-type dependent */
1004                 {
1005                         switch (mp_bus_id_to_type[bus])
1006                         {
1007                                 case MP_BUS_ISA: /* ISA pin */
1008                                 {
1009                                         trigger = default_ISA_trigger(idx);
1010                                         break;
1011                                 }
1012                                 case MP_BUS_EISA: /* EISA pin */
1013                                 {
1014                                         trigger = default_EISA_trigger(idx);
1015                                         break;
1016                                 }
1017                                 case MP_BUS_PCI: /* PCI pin */
1018                                 {
1019                                         trigger = default_PCI_trigger(idx);
1020                                         break;
1021                                 }
1022                                 case MP_BUS_MCA: /* MCA pin */
1023                                 {
1024                                         trigger = default_MCA_trigger(idx);
1025                                         break;
1026                                 }
1027                                 case MP_BUS_NEC98: /* NEC 98 pin */
1028                                 {
1029                                         trigger = default_NEC98_trigger(idx);
1030                                         break;
1031                                 }
1032                                 default:
1033                                 {
1034                                         printk(KERN_WARNING "broken BIOS!!\n");
1035                                         trigger = 1;
1036                                         break;
1037                                 }
1038                         }
1039                         break;
1040                 }
1041                 case 1: /* edge */
1042                 {
1043                         trigger = 0;
1044                         break;
1045                 }
1046                 case 2: /* reserved */
1047                 {
1048                         printk(KERN_WARNING "broken BIOS!!\n");
1049                         trigger = 1;
1050                         break;
1051                 }
1052                 case 3: /* level */
1053                 {
1054                         trigger = 1;
1055                         break;
1056                 }
1057                 default: /* invalid */
1058                 {
1059                         printk(KERN_WARNING "broken BIOS!!\n");
1060                         trigger = 0;
1061                         break;
1062                 }
1063         }
1064         return trigger;
1065 }
1066
1067 static inline int irq_polarity(int idx)
1068 {
1069         return MPBIOS_polarity(idx);
1070 }
1071
1072 static inline int irq_trigger(int idx)
1073 {
1074         return MPBIOS_trigger(idx);
1075 }
1076
1077 static int pin_2_irq(int idx, int apic, int pin)
1078 {
1079         int irq, i;
1080         int bus = mp_irqs[idx].mpc_srcbus;
1081
1082         /*
1083          * Debugging check, we are in big trouble if this message pops up!
1084          */
1085         if (mp_irqs[idx].mpc_dstirq != pin)
1086                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1087
1088         switch (mp_bus_id_to_type[bus])
1089         {
1090                 case MP_BUS_ISA: /* ISA pin */
1091                 case MP_BUS_EISA:
1092                 case MP_BUS_MCA:
1093                 case MP_BUS_NEC98:
1094                 {
1095                         irq = mp_irqs[idx].mpc_srcbusirq;
1096                         break;
1097                 }
1098                 case MP_BUS_PCI: /* PCI pin */
1099                 {
1100                         /*
1101                          * PCI IRQs are mapped in order
1102                          */
1103                         i = irq = 0;
1104                         while (i < apic)
1105                                 irq += nr_ioapic_registers[i++];
1106                         irq += pin;
1107
1108                         /*
1109                          * For MPS mode, so far only needed by ES7000 platform
1110                          */
1111                         if (ioapic_renumber_irq)
1112                                 irq = ioapic_renumber_irq(apic, irq);
1113
1114                         break;
1115                 }
1116                 default:
1117                 {
1118                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1119                         irq = 0;
1120                         break;
1121                 }
1122         }
1123
1124         /*
1125          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1126          */
1127         if ((pin >= 16) && (pin <= 23)) {
1128                 if (pirq_entries[pin-16] != -1) {
1129                         if (!pirq_entries[pin-16]) {
1130                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1131                                                 "disabling PIRQ%d\n", pin-16);
1132                         } else {
1133                                 irq = pirq_entries[pin-16];
1134                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1135                                                 "using PIRQ%d -> IRQ %d\n",
1136                                                 pin-16, irq);
1137                         }
1138                 }
1139         }
1140         return irq;
1141 }
1142
1143 static inline int IO_APIC_irq_trigger(int irq)
1144 {
1145         int apic, idx, pin;
1146
1147         for (apic = 0; apic < nr_ioapics; apic++) {
1148                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1149                         idx = find_irq_entry(apic,pin,mp_INT);
1150                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1151                                 return irq_trigger(idx);
1152                 }
1153         }
1154         /*
1155          * nonexistent IRQs are edge default
1156          */
1157         return 0;
1158 }
1159
1160 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1161 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1162
1163 int assign_irq_vector(int irq)
1164 {
1165         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1166         unsigned long flags;
1167         int vector;
1168
1169         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1170
1171         spin_lock_irqsave(&vector_lock, flags);
1172
1173         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1174                 spin_unlock_irqrestore(&vector_lock, flags);
1175                 return IO_APIC_VECTOR(irq);
1176         }
1177 next:
1178         current_vector += 8;
1179         if (current_vector == SYSCALL_VECTOR)
1180                 goto next;
1181
1182         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1183                 offset++;
1184                 if (!(offset%8)) {
1185                         spin_unlock_irqrestore(&vector_lock, flags);
1186                         return -ENOSPC;
1187                 }
1188                 current_vector = FIRST_DEVICE_VECTOR + offset;
1189         }
1190
1191         vector = current_vector;
1192         vector_irq[vector] = irq;
1193         if (irq != AUTO_ASSIGN)
1194                 IO_APIC_VECTOR(irq) = vector;
1195
1196         spin_unlock_irqrestore(&vector_lock, flags);
1197
1198         return vector;
1199 }
1200
1201 static struct hw_interrupt_type ioapic_level_type;
1202 static struct hw_interrupt_type ioapic_edge_type;
1203
1204 #define IOAPIC_AUTO     -1
1205 #define IOAPIC_EDGE     0
1206 #define IOAPIC_LEVEL    1
1207
1208 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1209 {
1210         unsigned idx;
1211
1212         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1213
1214         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1215                         trigger == IOAPIC_LEVEL)
1216                 irq_desc[idx].chip = &ioapic_level_type;
1217         else
1218                 irq_desc[idx].chip = &ioapic_edge_type;
1219         set_intr_gate(vector, interrupt[idx]);
1220 }
1221
1222 static void __init setup_IO_APIC_irqs(void)
1223 {
1224         struct IO_APIC_route_entry entry;
1225         int apic, pin, idx, irq, first_notcon = 1, vector;
1226         unsigned long flags;
1227
1228         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1229
1230         for (apic = 0; apic < nr_ioapics; apic++) {
1231         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1232
1233                 /*
1234                  * add it to the IO-APIC irq-routing table:
1235                  */
1236                 memset(&entry,0,sizeof(entry));
1237
1238                 entry.delivery_mode = INT_DELIVERY_MODE;
1239                 entry.dest_mode = INT_DEST_MODE;
1240                 entry.mask = 0;                         /* enable IRQ */
1241                 entry.dest.logical.logical_dest =
1242                                         cpu_mask_to_apicid(TARGET_CPUS);
1243
1244                 idx = find_irq_entry(apic,pin,mp_INT);
1245                 if (idx == -1) {
1246                         if (first_notcon) {
1247                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1248                                                 " IO-APIC (apicid-pin) %d-%d",
1249                                                 mp_ioapics[apic].mpc_apicid,
1250                                                 pin);
1251                                 first_notcon = 0;
1252                         } else
1253                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1254                                         mp_ioapics[apic].mpc_apicid, pin);
1255                         continue;
1256                 }
1257
1258                 entry.trigger = irq_trigger(idx);
1259                 entry.polarity = irq_polarity(idx);
1260
1261                 if (irq_trigger(idx)) {
1262                         entry.trigger = 1;
1263                         entry.mask = 1;
1264                 }
1265
1266                 irq = pin_2_irq(idx, apic, pin);
1267                 /*
1268                  * skip adding the timer int on secondary nodes, which causes
1269                  * a small but painful rift in the time-space continuum
1270                  */
1271                 if (multi_timer_check(apic, irq))
1272                         continue;
1273                 else
1274                         add_pin_to_irq(irq, apic, pin);
1275
1276                 if (!apic && !IO_APIC_IRQ(irq))
1277                         continue;
1278
1279                 if (IO_APIC_IRQ(irq)) {
1280                         vector = assign_irq_vector(irq);
1281                         entry.vector = vector;
1282                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1283
1284                         if (!apic && (irq < 16))
1285                                 disable_8259A_irq(irq);
1286                 }
1287                 spin_lock_irqsave(&ioapic_lock, flags);
1288                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1289                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1290                 set_native_irq_info(irq, TARGET_CPUS);
1291                 spin_unlock_irqrestore(&ioapic_lock, flags);
1292         }
1293         }
1294
1295         if (!first_notcon)
1296                 apic_printk(APIC_VERBOSE, " not connected.\n");
1297 }
1298
1299 /*
1300  * Set up the 8259A-master output pin:
1301  */
1302 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1303 {
1304         struct IO_APIC_route_entry entry;
1305         unsigned long flags;
1306
1307         memset(&entry,0,sizeof(entry));
1308
1309         disable_8259A_irq(0);
1310
1311         /* mask LVT0 */
1312         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1313
1314         /*
1315          * We use logical delivery to get the timer IRQ
1316          * to the first CPU.
1317          */
1318         entry.dest_mode = INT_DEST_MODE;
1319         entry.mask = 0;                                 /* unmask IRQ now */
1320         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1321         entry.delivery_mode = INT_DELIVERY_MODE;
1322         entry.polarity = 0;
1323         entry.trigger = 0;
1324         entry.vector = vector;
1325
1326         /*
1327          * The timer IRQ doesn't have to know that behind the
1328          * scene we have a 8259A-master in AEOI mode ...
1329          */
1330         irq_desc[0].chip = &ioapic_edge_type;
1331
1332         /*
1333          * Add it to the IO-APIC irq-routing table:
1334          */
1335         spin_lock_irqsave(&ioapic_lock, flags);
1336         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1337         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1338         spin_unlock_irqrestore(&ioapic_lock, flags);
1339
1340         enable_8259A_irq(0);
1341 }
1342
1343 static inline void UNEXPECTED_IO_APIC(void)
1344 {
1345 }
1346
1347 void __init print_IO_APIC(void)
1348 {
1349         int apic, i;
1350         union IO_APIC_reg_00 reg_00;
1351         union IO_APIC_reg_01 reg_01;
1352         union IO_APIC_reg_02 reg_02;
1353         union IO_APIC_reg_03 reg_03;
1354         unsigned long flags;
1355
1356         if (apic_verbosity == APIC_QUIET)
1357                 return;
1358
1359         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1360         for (i = 0; i < nr_ioapics; i++)
1361                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1362                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1363
1364         /*
1365          * We are a bit conservative about what we expect.  We have to
1366          * know about every hardware change ASAP.
1367          */
1368         printk(KERN_INFO "testing the IO APIC.......................\n");
1369
1370         for (apic = 0; apic < nr_ioapics; apic++) {
1371
1372         spin_lock_irqsave(&ioapic_lock, flags);
1373         reg_00.raw = io_apic_read(apic, 0);
1374         reg_01.raw = io_apic_read(apic, 1);
1375         if (reg_01.bits.version >= 0x10)
1376                 reg_02.raw = io_apic_read(apic, 2);
1377         if (reg_01.bits.version >= 0x20)
1378                 reg_03.raw = io_apic_read(apic, 3);
1379         spin_unlock_irqrestore(&ioapic_lock, flags);
1380
1381         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1382         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1383         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1384         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1385         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1386         if (reg_00.bits.ID >= get_physical_broadcast())
1387                 UNEXPECTED_IO_APIC();
1388         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1389                 UNEXPECTED_IO_APIC();
1390
1391         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1392         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1393         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1394                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1395                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1396                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1397                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1398                 (reg_01.bits.entries != 0x2E) &&
1399                 (reg_01.bits.entries != 0x3F)
1400         )
1401                 UNEXPECTED_IO_APIC();
1402
1403         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1404         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1405         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1406                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1407                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1408                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1409                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1410         )
1411                 UNEXPECTED_IO_APIC();
1412         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1413                 UNEXPECTED_IO_APIC();
1414
1415         /*
1416          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1417          * but the value of reg_02 is read as the previous read register
1418          * value, so ignore it if reg_02 == reg_01.
1419          */
1420         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1421                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1422                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1423                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1424                         UNEXPECTED_IO_APIC();
1425         }
1426
1427         /*
1428          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1429          * or reg_03, but the value of reg_0[23] is read as the previous read
1430          * register value, so ignore it if reg_03 == reg_0[12].
1431          */
1432         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1433             reg_03.raw != reg_01.raw) {
1434                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1435                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1436                 if (reg_03.bits.__reserved_1)
1437                         UNEXPECTED_IO_APIC();
1438         }
1439
1440         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1441
1442         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1443                           " Stat Dest Deli Vect:   \n");
1444
1445         for (i = 0; i <= reg_01.bits.entries; i++) {
1446                 struct IO_APIC_route_entry entry;
1447
1448                 spin_lock_irqsave(&ioapic_lock, flags);
1449                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1450                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1451                 spin_unlock_irqrestore(&ioapic_lock, flags);
1452
1453                 printk(KERN_DEBUG " %02x %03X %02X  ",
1454                         i,
1455                         entry.dest.logical.logical_dest,
1456                         entry.dest.physical.physical_dest
1457                 );
1458
1459                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1460                         entry.mask,
1461                         entry.trigger,
1462                         entry.irr,
1463                         entry.polarity,
1464                         entry.delivery_status,
1465                         entry.dest_mode,
1466                         entry.delivery_mode,
1467                         entry.vector
1468                 );
1469         }
1470         }
1471         if (use_pci_vector())
1472                 printk(KERN_INFO "Using vector-based indexing\n");
1473         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1474         for (i = 0; i < NR_IRQS; i++) {
1475                 struct irq_pin_list *entry = irq_2_pin + i;
1476                 if (entry->pin < 0)
1477                         continue;
1478                 if (use_pci_vector() && !platform_legacy_irq(i))
1479                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1480                 else
1481                         printk(KERN_DEBUG "IRQ%d ", i);
1482                 for (;;) {
1483                         printk("-> %d:%d", entry->apic, entry->pin);
1484                         if (!entry->next)
1485                                 break;
1486                         entry = irq_2_pin + entry->next;
1487                 }
1488                 printk("\n");
1489         }
1490
1491         printk(KERN_INFO ".................................... done.\n");
1492
1493         return;
1494 }
1495
1496 #if 0
1497
1498 static void print_APIC_bitfield (int base)
1499 {
1500         unsigned int v;
1501         int i, j;
1502
1503         if (apic_verbosity == APIC_QUIET)
1504                 return;
1505
1506         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1507         for (i = 0; i < 8; i++) {
1508                 v = apic_read(base + i*0x10);
1509                 for (j = 0; j < 32; j++) {
1510                         if (v & (1<<j))
1511                                 printk("1");
1512                         else
1513                                 printk("0");
1514                 }
1515                 printk("\n");
1516         }
1517 }
1518
1519 void /*__init*/ print_local_APIC(void * dummy)
1520 {
1521         unsigned int v, ver, maxlvt;
1522
1523         if (apic_verbosity == APIC_QUIET)
1524                 return;
1525
1526         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1527                 smp_processor_id(), hard_smp_processor_id());
1528         v = apic_read(APIC_ID);
1529         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1530         v = apic_read(APIC_LVR);
1531         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1532         ver = GET_APIC_VERSION(v);
1533         maxlvt = get_maxlvt();
1534
1535         v = apic_read(APIC_TASKPRI);
1536         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1537
1538         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1539                 v = apic_read(APIC_ARBPRI);
1540                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1541                         v & APIC_ARBPRI_MASK);
1542                 v = apic_read(APIC_PROCPRI);
1543                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1544         }
1545
1546         v = apic_read(APIC_EOI);
1547         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1548         v = apic_read(APIC_RRR);
1549         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1550         v = apic_read(APIC_LDR);
1551         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1552         v = apic_read(APIC_DFR);
1553         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1554         v = apic_read(APIC_SPIV);
1555         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1556
1557         printk(KERN_DEBUG "... APIC ISR field:\n");
1558         print_APIC_bitfield(APIC_ISR);
1559         printk(KERN_DEBUG "... APIC TMR field:\n");
1560         print_APIC_bitfield(APIC_TMR);
1561         printk(KERN_DEBUG "... APIC IRR field:\n");
1562         print_APIC_bitfield(APIC_IRR);
1563
1564         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1565                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1566                         apic_write(APIC_ESR, 0);
1567                 v = apic_read(APIC_ESR);
1568                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1569         }
1570
1571         v = apic_read(APIC_ICR);
1572         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1573         v = apic_read(APIC_ICR2);
1574         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1575
1576         v = apic_read(APIC_LVTT);
1577         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1578
1579         if (maxlvt > 3) {                       /* PC is LVT#4. */
1580                 v = apic_read(APIC_LVTPC);
1581                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1582         }
1583         v = apic_read(APIC_LVT0);
1584         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1585         v = apic_read(APIC_LVT1);
1586         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1587
1588         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1589                 v = apic_read(APIC_LVTERR);
1590                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1591         }
1592
1593         v = apic_read(APIC_TMICT);
1594         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1595         v = apic_read(APIC_TMCCT);
1596         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1597         v = apic_read(APIC_TDCR);
1598         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1599         printk("\n");
1600 }
1601
1602 void print_all_local_APICs (void)
1603 {
1604         on_each_cpu(print_local_APIC, NULL, 1, 1);
1605 }
1606
1607 void /*__init*/ print_PIC(void)
1608 {
1609         unsigned int v;
1610         unsigned long flags;
1611
1612         if (apic_verbosity == APIC_QUIET)
1613                 return;
1614
1615         printk(KERN_DEBUG "\nprinting PIC contents\n");
1616
1617         spin_lock_irqsave(&i8259A_lock, flags);
1618
1619         v = inb(0xa1) << 8 | inb(0x21);
1620         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1621
1622         v = inb(0xa0) << 8 | inb(0x20);
1623         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1624
1625         outb(0x0b,0xa0);
1626         outb(0x0b,0x20);
1627         v = inb(0xa0) << 8 | inb(0x20);
1628         outb(0x0a,0xa0);
1629         outb(0x0a,0x20);
1630
1631         spin_unlock_irqrestore(&i8259A_lock, flags);
1632
1633         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1634
1635         v = inb(0x4d1) << 8 | inb(0x4d0);
1636         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1637 }
1638
1639 #endif  /*  0  */
1640
1641 static void __init enable_IO_APIC(void)
1642 {
1643         union IO_APIC_reg_01 reg_01;
1644         int i8259_apic, i8259_pin;
1645         int i, apic;
1646         unsigned long flags;
1647
1648         for (i = 0; i < PIN_MAP_SIZE; i++) {
1649                 irq_2_pin[i].pin = -1;
1650                 irq_2_pin[i].next = 0;
1651         }
1652         if (!pirqs_enabled)
1653                 for (i = 0; i < MAX_PIRQS; i++)
1654                         pirq_entries[i] = -1;
1655
1656         /*
1657          * The number of IO-APIC IRQ registers (== #pins):
1658          */
1659         for (apic = 0; apic < nr_ioapics; apic++) {
1660                 spin_lock_irqsave(&ioapic_lock, flags);
1661                 reg_01.raw = io_apic_read(apic, 1);
1662                 spin_unlock_irqrestore(&ioapic_lock, flags);
1663                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1664         }
1665         for(apic = 0; apic < nr_ioapics; apic++) {
1666                 int pin;
1667                 /* See if any of the pins is in ExtINT mode */
1668                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1669                         struct IO_APIC_route_entry entry;
1670                         spin_lock_irqsave(&ioapic_lock, flags);
1671                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1672                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1673                         spin_unlock_irqrestore(&ioapic_lock, flags);
1674
1675
1676                         /* If the interrupt line is enabled and in ExtInt mode
1677                          * I have found the pin where the i8259 is connected.
1678                          */
1679                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1680                                 ioapic_i8259.apic = apic;
1681                                 ioapic_i8259.pin  = pin;
1682                                 goto found_i8259;
1683                         }
1684                 }
1685         }
1686  found_i8259:
1687         /* Look to see what if the MP table has reported the ExtINT */
1688         /* If we could not find the appropriate pin by looking at the ioapic
1689          * the i8259 probably is not connected the ioapic but give the
1690          * mptable a chance anyway.
1691          */
1692         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1693         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1694         /* Trust the MP table if nothing is setup in the hardware */
1695         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1696                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1697                 ioapic_i8259.pin  = i8259_pin;
1698                 ioapic_i8259.apic = i8259_apic;
1699         }
1700         /* Complain if the MP table and the hardware disagree */
1701         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1702                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1703         {
1704                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1705         }
1706
1707         /*
1708          * Do not trust the IO-APIC being empty at bootup
1709          */
1710         clear_IO_APIC();
1711 }
1712
1713 /*
1714  * Not an __init, needed by the reboot code
1715  */
1716 void disable_IO_APIC(void)
1717 {
1718         /*
1719          * Clear the IO-APIC before rebooting:
1720          */
1721         clear_IO_APIC();
1722
1723         /*
1724          * If the i8259 is routed through an IOAPIC
1725          * Put that IOAPIC in virtual wire mode
1726          * so legacy interrupts can be delivered.
1727          */
1728         if (ioapic_i8259.pin != -1) {
1729                 struct IO_APIC_route_entry entry;
1730                 unsigned long flags;
1731
1732                 memset(&entry, 0, sizeof(entry));
1733                 entry.mask            = 0; /* Enabled */
1734                 entry.trigger         = 0; /* Edge */
1735                 entry.irr             = 0;
1736                 entry.polarity        = 0; /* High */
1737                 entry.delivery_status = 0;
1738                 entry.dest_mode       = 0; /* Physical */
1739                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1740                 entry.vector          = 0;
1741                 entry.dest.physical.physical_dest =
1742                                         GET_APIC_ID(apic_read(APIC_ID));
1743
1744                 /*
1745                  * Add it to the IO-APIC irq-routing table:
1746                  */
1747                 spin_lock_irqsave(&ioapic_lock, flags);
1748                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1749                         *(((int *)&entry)+1));
1750                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1751                         *(((int *)&entry)+0));
1752                 spin_unlock_irqrestore(&ioapic_lock, flags);
1753         }
1754         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1755 }
1756
1757 /*
1758  * function to set the IO-APIC physical IDs based on the
1759  * values stored in the MPC table.
1760  *
1761  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1762  */
1763
1764 #ifndef CONFIG_X86_NUMAQ
1765 static void __init setup_ioapic_ids_from_mpc(void)
1766 {
1767         union IO_APIC_reg_00 reg_00;
1768         physid_mask_t phys_id_present_map;
1769         int apic;
1770         int i;
1771         unsigned char old_id;
1772         unsigned long flags;
1773
1774         /*
1775          * Don't check I/O APIC IDs for xAPIC systems.  They have
1776          * no meaning without the serial APIC bus.
1777          */
1778         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1779                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1780                 return;
1781         /*
1782          * This is broken; anything with a real cpu count has to
1783          * circumvent this idiocy regardless.
1784          */
1785         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1786
1787         /*
1788          * Set the IOAPIC ID to the value stored in the MPC table.
1789          */
1790         for (apic = 0; apic < nr_ioapics; apic++) {
1791
1792                 /* Read the register 0 value */
1793                 spin_lock_irqsave(&ioapic_lock, flags);
1794                 reg_00.raw = io_apic_read(apic, 0);
1795                 spin_unlock_irqrestore(&ioapic_lock, flags);
1796
1797                 old_id = mp_ioapics[apic].mpc_apicid;
1798
1799                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1800                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1801                                 apic, mp_ioapics[apic].mpc_apicid);
1802                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1803                                 reg_00.bits.ID);
1804                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1805                 }
1806
1807                 /*
1808                  * Sanity check, is the ID really free? Every APIC in a
1809                  * system must have a unique ID or we get lots of nice
1810                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1811                  */
1812                 if (check_apicid_used(phys_id_present_map,
1813                                         mp_ioapics[apic].mpc_apicid)) {
1814                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1815                                 apic, mp_ioapics[apic].mpc_apicid);
1816                         for (i = 0; i < get_physical_broadcast(); i++)
1817                                 if (!physid_isset(i, phys_id_present_map))
1818                                         break;
1819                         if (i >= get_physical_broadcast())
1820                                 panic("Max APIC ID exceeded!\n");
1821                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1822                                 i);
1823                         physid_set(i, phys_id_present_map);
1824                         mp_ioapics[apic].mpc_apicid = i;
1825                 } else {
1826                         physid_mask_t tmp;
1827                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1828                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1829                                         "phys_id_present_map\n",
1830                                         mp_ioapics[apic].mpc_apicid);
1831                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1832                 }
1833
1834
1835                 /*
1836                  * We need to adjust the IRQ routing table
1837                  * if the ID changed.
1838                  */
1839                 if (old_id != mp_ioapics[apic].mpc_apicid)
1840                         for (i = 0; i < mp_irq_entries; i++)
1841                                 if (mp_irqs[i].mpc_dstapic == old_id)
1842                                         mp_irqs[i].mpc_dstapic
1843                                                 = mp_ioapics[apic].mpc_apicid;
1844
1845                 /*
1846                  * Read the right value from the MPC table and
1847                  * write it into the ID register.
1848                  */
1849                 apic_printk(APIC_VERBOSE, KERN_INFO
1850                         "...changing IO-APIC physical APIC ID to %d ...",
1851                         mp_ioapics[apic].mpc_apicid);
1852
1853                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1854                 spin_lock_irqsave(&ioapic_lock, flags);
1855                 io_apic_write(apic, 0, reg_00.raw);
1856                 spin_unlock_irqrestore(&ioapic_lock, flags);
1857
1858                 /*
1859                  * Sanity check
1860                  */
1861                 spin_lock_irqsave(&ioapic_lock, flags);
1862                 reg_00.raw = io_apic_read(apic, 0);
1863                 spin_unlock_irqrestore(&ioapic_lock, flags);
1864                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1865                         printk("could not set ID!\n");
1866                 else
1867                         apic_printk(APIC_VERBOSE, " ok.\n");
1868         }
1869 }
1870 #else
1871 static void __init setup_ioapic_ids_from_mpc(void) { }
1872 #endif
1873
1874 /*
1875  * There is a nasty bug in some older SMP boards, their mptable lies
1876  * about the timer IRQ. We do the following to work around the situation:
1877  *
1878  *      - timer IRQ defaults to IO-APIC IRQ
1879  *      - if this function detects that timer IRQs are defunct, then we fall
1880  *        back to ISA timer IRQs
1881  */
1882 static int __init timer_irq_works(void)
1883 {
1884         unsigned long t1 = jiffies;
1885
1886         local_irq_enable();
1887         /* Let ten ticks pass... */
1888         mdelay((10 * 1000) / HZ);
1889
1890         /*
1891          * Expect a few ticks at least, to be sure some possible
1892          * glue logic does not lock up after one or two first
1893          * ticks in a non-ExtINT mode.  Also the local APIC
1894          * might have cached one ExtINT interrupt.  Finally, at
1895          * least one tick may be lost due to delays.
1896          */
1897         if (jiffies - t1 > 4)
1898                 return 1;
1899
1900         return 0;
1901 }
1902
1903 /*
1904  * In the SMP+IOAPIC case it might happen that there are an unspecified
1905  * number of pending IRQ events unhandled. These cases are very rare,
1906  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1907  * better to do it this way as thus we do not have to be aware of
1908  * 'pending' interrupts in the IRQ path, except at this point.
1909  */
1910 /*
1911  * Edge triggered needs to resend any interrupt
1912  * that was delayed but this is now handled in the device
1913  * independent code.
1914  */
1915
1916 /*
1917  * Starting up a edge-triggered IO-APIC interrupt is
1918  * nasty - we need to make sure that we get the edge.
1919  * If it is already asserted for some reason, we need
1920  * return 1 to indicate that is was pending.
1921  *
1922  * This is not complete - we should be able to fake
1923  * an edge even if it isn't on the 8259A...
1924  */
1925 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1926 {
1927         int was_pending = 0;
1928         unsigned long flags;
1929
1930         spin_lock_irqsave(&ioapic_lock, flags);
1931         if (irq < 16) {
1932                 disable_8259A_irq(irq);
1933                 if (i8259A_irq_pending(irq))
1934                         was_pending = 1;
1935         }
1936         __unmask_IO_APIC_irq(irq);
1937         spin_unlock_irqrestore(&ioapic_lock, flags);
1938
1939         return was_pending;
1940 }
1941
1942 /*
1943  * Once we have recorded IRQ_PENDING already, we can mask the
1944  * interrupt for real. This prevents IRQ storms from unhandled
1945  * devices.
1946  */
1947 static void ack_edge_ioapic_irq(unsigned int irq)
1948 {
1949         move_irq(irq);
1950         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1951                                         == (IRQ_PENDING | IRQ_DISABLED))
1952                 mask_IO_APIC_irq(irq);
1953         ack_APIC_irq();
1954 }
1955
1956 /*
1957  * Level triggered interrupts can just be masked,
1958  * and shutting down and starting up the interrupt
1959  * is the same as enabling and disabling them -- except
1960  * with a startup need to return a "was pending" value.
1961  *
1962  * Level triggered interrupts are special because we
1963  * do not touch any IO-APIC register while handling
1964  * them. We ack the APIC in the end-IRQ handler, not
1965  * in the start-IRQ-handler. Protection against reentrance
1966  * from the same interrupt is still provided, both by the
1967  * generic IRQ layer and by the fact that an unacked local
1968  * APIC does not accept IRQs.
1969  */
1970 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1971 {
1972         unmask_IO_APIC_irq(irq);
1973
1974         return 0; /* don't check for pending */
1975 }
1976
1977 static void end_level_ioapic_irq (unsigned int irq)
1978 {
1979         unsigned long v;
1980         int i;
1981
1982         move_irq(irq);
1983 /*
1984  * It appears there is an erratum which affects at least version 0x11
1985  * of I/O APIC (that's the 82093AA and cores integrated into various
1986  * chipsets).  Under certain conditions a level-triggered interrupt is
1987  * erroneously delivered as edge-triggered one but the respective IRR
1988  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1989  * message but it will never arrive and further interrupts are blocked
1990  * from the source.  The exact reason is so far unknown, but the
1991  * phenomenon was observed when two consecutive interrupt requests
1992  * from a given source get delivered to the same CPU and the source is
1993  * temporarily disabled in between.
1994  *
1995  * A workaround is to simulate an EOI message manually.  We achieve it
1996  * by setting the trigger mode to edge and then to level when the edge
1997  * trigger mode gets detected in the TMR of a local APIC for a
1998  * level-triggered interrupt.  We mask the source for the time of the
1999  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2000  * The idea is from Manfred Spraul.  --macro
2001  */
2002         i = IO_APIC_VECTOR(irq);
2003
2004         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2005
2006         ack_APIC_irq();
2007
2008         if (!(v & (1 << (i & 0x1f)))) {
2009                 atomic_inc(&irq_mis_count);
2010                 spin_lock(&ioapic_lock);
2011                 __mask_and_edge_IO_APIC_irq(irq);
2012                 __unmask_and_level_IO_APIC_irq(irq);
2013                 spin_unlock(&ioapic_lock);
2014         }
2015 }
2016
2017 #ifdef CONFIG_PCI_MSI
2018 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2019 {
2020         int irq = vector_to_irq(vector);
2021
2022         return startup_edge_ioapic_irq(irq);
2023 }
2024
2025 static void ack_edge_ioapic_vector(unsigned int vector)
2026 {
2027         int irq = vector_to_irq(vector);
2028
2029         move_native_irq(vector);
2030         ack_edge_ioapic_irq(irq);
2031 }
2032
2033 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2034 {
2035         int irq = vector_to_irq(vector);
2036
2037         return startup_level_ioapic_irq (irq);
2038 }
2039
2040 static void end_level_ioapic_vector (unsigned int vector)
2041 {
2042         int irq = vector_to_irq(vector);
2043
2044         move_native_irq(vector);
2045         end_level_ioapic_irq(irq);
2046 }
2047
2048 static void mask_IO_APIC_vector (unsigned int vector)
2049 {
2050         int irq = vector_to_irq(vector);
2051
2052         mask_IO_APIC_irq(irq);
2053 }
2054
2055 static void unmask_IO_APIC_vector (unsigned int vector)
2056 {
2057         int irq = vector_to_irq(vector);
2058
2059         unmask_IO_APIC_irq(irq);
2060 }
2061
2062 #ifdef CONFIG_SMP
2063 static void set_ioapic_affinity_vector (unsigned int vector,
2064                                         cpumask_t cpu_mask)
2065 {
2066         int irq = vector_to_irq(vector);
2067
2068         set_native_irq_info(vector, cpu_mask);
2069         set_ioapic_affinity_irq(irq, cpu_mask);
2070 }
2071 #endif
2072 #endif
2073
2074 static int ioapic_retrigger(unsigned int irq)
2075 {
2076         send_IPI_self(IO_APIC_VECTOR(irq));
2077
2078         return 1;
2079 }
2080
2081 /*
2082  * Level and edge triggered IO-APIC interrupts need different handling,
2083  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2084  * handled with the level-triggered descriptor, but that one has slightly
2085  * more overhead. Level-triggered interrupts cannot be handled with the
2086  * edge-triggered handler, without risking IRQ storms and other ugly
2087  * races.
2088  */
2089 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2090         .typename       = "IO-APIC-edge",
2091         .startup        = startup_edge_ioapic,
2092         .shutdown       = shutdown_edge_ioapic,
2093         .enable         = enable_edge_ioapic,
2094         .disable        = disable_edge_ioapic,
2095         .ack            = ack_edge_ioapic,
2096         .end            = end_edge_ioapic,
2097 #ifdef CONFIG_SMP
2098         .set_affinity   = set_ioapic_affinity,
2099 #endif
2100         .retrigger      = ioapic_retrigger,
2101 };
2102
2103 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2104         .typename       = "IO-APIC-level",
2105         .startup        = startup_level_ioapic,
2106         .shutdown       = shutdown_level_ioapic,
2107         .enable         = enable_level_ioapic,
2108         .disable        = disable_level_ioapic,
2109         .ack            = mask_and_ack_level_ioapic,
2110         .end            = end_level_ioapic,
2111 #ifdef CONFIG_SMP
2112         .set_affinity   = set_ioapic_affinity,
2113 #endif
2114         .retrigger      = ioapic_retrigger,
2115 };
2116
2117 static inline void init_IO_APIC_traps(void)
2118 {
2119         int irq;
2120
2121         /*
2122          * NOTE! The local APIC isn't very good at handling
2123          * multiple interrupts at the same interrupt level.
2124          * As the interrupt level is determined by taking the
2125          * vector number and shifting that right by 4, we
2126          * want to spread these out a bit so that they don't
2127          * all fall in the same interrupt level.
2128          *
2129          * Also, we've got to be careful not to trash gate
2130          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2131          */
2132         for (irq = 0; irq < NR_IRQS ; irq++) {
2133                 int tmp = irq;
2134                 if (use_pci_vector()) {
2135                         if (!platform_legacy_irq(tmp))
2136                                 if ((tmp = vector_to_irq(tmp)) == -1)
2137                                         continue;
2138                 }
2139                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2140                         /*
2141                          * Hmm.. We don't have an entry for this,
2142                          * so default to an old-fashioned 8259
2143                          * interrupt if we can..
2144                          */
2145                         if (irq < 16)
2146                                 make_8259A_irq(irq);
2147                         else
2148                                 /* Strange. Oh, well.. */
2149                                 irq_desc[irq].chip = &no_irq_type;
2150                 }
2151         }
2152 }
2153
2154 static void enable_lapic_irq (unsigned int irq)
2155 {
2156         unsigned long v;
2157
2158         v = apic_read(APIC_LVT0);
2159         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2160 }
2161
2162 static void disable_lapic_irq (unsigned int irq)
2163 {
2164         unsigned long v;
2165
2166         v = apic_read(APIC_LVT0);
2167         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2168 }
2169
2170 static void ack_lapic_irq (unsigned int irq)
2171 {
2172         ack_APIC_irq();
2173 }
2174
2175 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2176
2177 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2178         .typename       = "local-APIC-edge",
2179         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2180         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2181         .enable         = enable_lapic_irq,
2182         .disable        = disable_lapic_irq,
2183         .ack            = ack_lapic_irq,
2184         .end            = end_lapic_irq
2185 };
2186
2187 static void setup_nmi (void)
2188 {
2189         /*
2190          * Dirty trick to enable the NMI watchdog ...
2191          * We put the 8259A master into AEOI mode and
2192          * unmask on all local APICs LVT0 as NMI.
2193          *
2194          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2195          * is from Maciej W. Rozycki - so we do not have to EOI from
2196          * the NMI handler or the timer interrupt.
2197          */
2198         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2199
2200         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2201
2202         apic_printk(APIC_VERBOSE, " done.\n");
2203 }
2204
2205 /*
2206  * This looks a bit hackish but it's about the only one way of sending
2207  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2208  * not support the ExtINT mode, unfortunately.  We need to send these
2209  * cycles as some i82489DX-based boards have glue logic that keeps the
2210  * 8259A interrupt line asserted until INTA.  --macro
2211  */
2212 static inline void unlock_ExtINT_logic(void)
2213 {
2214         int apic, pin, i;
2215         struct IO_APIC_route_entry entry0, entry1;
2216         unsigned char save_control, save_freq_select;
2217         unsigned long flags;
2218
2219         pin  = find_isa_irq_pin(8, mp_INT);
2220         apic = find_isa_irq_apic(8, mp_INT);
2221         if (pin == -1)
2222                 return;
2223
2224         spin_lock_irqsave(&ioapic_lock, flags);
2225         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2226         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2227         spin_unlock_irqrestore(&ioapic_lock, flags);
2228         clear_IO_APIC_pin(apic, pin);
2229
2230         memset(&entry1, 0, sizeof(entry1));
2231
2232         entry1.dest_mode = 0;                   /* physical delivery */
2233         entry1.mask = 0;                        /* unmask IRQ now */
2234         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2235         entry1.delivery_mode = dest_ExtINT;
2236         entry1.polarity = entry0.polarity;
2237         entry1.trigger = 0;
2238         entry1.vector = 0;
2239
2240         spin_lock_irqsave(&ioapic_lock, flags);
2241         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2242         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2243         spin_unlock_irqrestore(&ioapic_lock, flags);
2244
2245         save_control = CMOS_READ(RTC_CONTROL);
2246         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2247         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2248                    RTC_FREQ_SELECT);
2249         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2250
2251         i = 100;
2252         while (i-- > 0) {
2253                 mdelay(10);
2254                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2255                         i -= 10;
2256         }
2257
2258         CMOS_WRITE(save_control, RTC_CONTROL);
2259         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2260         clear_IO_APIC_pin(apic, pin);
2261
2262         spin_lock_irqsave(&ioapic_lock, flags);
2263         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2264         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2265         spin_unlock_irqrestore(&ioapic_lock, flags);
2266 }
2267
2268 int timer_uses_ioapic_pin_0;
2269
2270 /*
2271  * This code may look a bit paranoid, but it's supposed to cooperate with
2272  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2273  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2274  * fanatically on his truly buggy board.
2275  */
2276 static inline void check_timer(void)
2277 {
2278         int apic1, pin1, apic2, pin2;
2279         int vector;
2280
2281         /*
2282          * get/set the timer IRQ vector:
2283          */
2284         disable_8259A_irq(0);
2285         vector = assign_irq_vector(0);
2286         set_intr_gate(vector, interrupt[0]);
2287
2288         /*
2289          * Subtle, code in do_timer_interrupt() expects an AEOI
2290          * mode for the 8259A whenever interrupts are routed
2291          * through I/O APICs.  Also IRQ0 has to be enabled in
2292          * the 8259A which implies the virtual wire has to be
2293          * disabled in the local APIC.
2294          */
2295         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2296         init_8259A(1);
2297         timer_ack = 1;
2298         if (timer_over_8254 > 0)
2299                 enable_8259A_irq(0);
2300
2301         pin1  = find_isa_irq_pin(0, mp_INT);
2302         apic1 = find_isa_irq_apic(0, mp_INT);
2303         pin2  = ioapic_i8259.pin;
2304         apic2 = ioapic_i8259.apic;
2305
2306         if (pin1 == 0)
2307                 timer_uses_ioapic_pin_0 = 1;
2308
2309         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2310                 vector, apic1, pin1, apic2, pin2);
2311
2312         if (pin1 != -1) {
2313                 /*
2314                  * Ok, does IRQ0 through the IOAPIC work?
2315                  */
2316                 unmask_IO_APIC_irq(0);
2317                 if (timer_irq_works()) {
2318                         if (nmi_watchdog == NMI_IO_APIC) {
2319                                 disable_8259A_irq(0);
2320                                 setup_nmi();
2321                                 enable_8259A_irq(0);
2322                         }
2323                         if (disable_timer_pin_1 > 0)
2324                                 clear_IO_APIC_pin(0, pin1);
2325                         return;
2326                 }
2327                 clear_IO_APIC_pin(apic1, pin1);
2328                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2329                                 "IO-APIC\n");
2330         }
2331
2332         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2333         if (pin2 != -1) {
2334                 printk("\n..... (found pin %d) ...", pin2);
2335                 /*
2336                  * legacy devices should be connected to IO APIC #0
2337                  */
2338                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2339                 if (timer_irq_works()) {
2340                         printk("works.\n");
2341                         if (pin1 != -1)
2342                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2343                         else
2344                                 add_pin_to_irq(0, apic2, pin2);
2345                         if (nmi_watchdog == NMI_IO_APIC) {
2346                                 setup_nmi();
2347                         }
2348                         return;
2349                 }
2350                 /*
2351                  * Cleanup, just in case ...
2352                  */
2353                 clear_IO_APIC_pin(apic2, pin2);
2354         }
2355         printk(" failed.\n");
2356
2357         if (nmi_watchdog == NMI_IO_APIC) {
2358                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2359                 nmi_watchdog = 0;
2360         }
2361
2362         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2363
2364         disable_8259A_irq(0);
2365         irq_desc[0].chip = &lapic_irq_type;
2366         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2367         enable_8259A_irq(0);
2368
2369         if (timer_irq_works()) {
2370                 printk(" works.\n");
2371                 return;
2372         }
2373         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2374         printk(" failed.\n");
2375
2376         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2377
2378         timer_ack = 0;
2379         init_8259A(0);
2380         make_8259A_irq(0);
2381         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2382
2383         unlock_ExtINT_logic();
2384
2385         if (timer_irq_works()) {
2386                 printk(" works.\n");
2387                 return;
2388         }
2389         printk(" failed :(.\n");
2390         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2391                 "report.  Then try booting with the 'noapic' option");
2392 }
2393
2394 /*
2395  *
2396  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2397  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2398  *   Linux doesn't really care, as it's not actually used
2399  *   for any interrupt handling anyway.
2400  */
2401 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2402
2403 void __init setup_IO_APIC(void)
2404 {
2405         enable_IO_APIC();
2406
2407         if (acpi_ioapic)
2408                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2409         else
2410                 io_apic_irqs = ~PIC_IRQS;
2411
2412         printk("ENABLING IO-APIC IRQs\n");
2413
2414         /*
2415          * Set up IO-APIC IRQ routing.
2416          */
2417         if (!acpi_ioapic)
2418                 setup_ioapic_ids_from_mpc();
2419         sync_Arb_IDs();
2420         setup_IO_APIC_irqs();
2421         init_IO_APIC_traps();
2422         check_timer();
2423         if (!acpi_ioapic)
2424                 print_IO_APIC();
2425 }
2426
2427 static int __init setup_disable_8254_timer(char *s)
2428 {
2429         timer_over_8254 = -1;
2430         return 1;
2431 }
2432 static int __init setup_enable_8254_timer(char *s)
2433 {
2434         timer_over_8254 = 2;
2435         return 1;
2436 }
2437
2438 __setup("disable_8254_timer", setup_disable_8254_timer);
2439 __setup("enable_8254_timer", setup_enable_8254_timer);
2440
2441 /*
2442  *      Called after all the initialization is done. If we didnt find any
2443  *      APIC bugs then we can allow the modify fast path
2444  */
2445
2446 static int __init io_apic_bug_finalize(void)
2447 {
2448         if(sis_apic_bug == -1)
2449                 sis_apic_bug = 0;
2450         return 0;
2451 }
2452
2453 late_initcall(io_apic_bug_finalize);
2454
2455 struct sysfs_ioapic_data {
2456         struct sys_device dev;
2457         struct IO_APIC_route_entry entry[0];
2458 };
2459 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2460
2461 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2462 {
2463         struct IO_APIC_route_entry *entry;
2464         struct sysfs_ioapic_data *data;
2465         unsigned long flags;
2466         int i;
2467
2468         data = container_of(dev, struct sysfs_ioapic_data, dev);
2469         entry = data->entry;
2470         spin_lock_irqsave(&ioapic_lock, flags);
2471         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2472                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2473                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2474         }
2475         spin_unlock_irqrestore(&ioapic_lock, flags);
2476
2477         return 0;
2478 }
2479
2480 static int ioapic_resume(struct sys_device *dev)
2481 {
2482         struct IO_APIC_route_entry *entry;
2483         struct sysfs_ioapic_data *data;
2484         unsigned long flags;
2485         union IO_APIC_reg_00 reg_00;
2486         int i;
2487
2488         data = container_of(dev, struct sysfs_ioapic_data, dev);
2489         entry = data->entry;
2490
2491         spin_lock_irqsave(&ioapic_lock, flags);
2492         reg_00.raw = io_apic_read(dev->id, 0);
2493         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2494                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2495                 io_apic_write(dev->id, 0, reg_00.raw);
2496         }
2497         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2498                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2499                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2500         }
2501         spin_unlock_irqrestore(&ioapic_lock, flags);
2502
2503         return 0;
2504 }
2505
2506 static struct sysdev_class ioapic_sysdev_class = {
2507         set_kset_name("ioapic"),
2508         .suspend = ioapic_suspend,
2509         .resume = ioapic_resume,
2510 };
2511
2512 static int __init ioapic_init_sysfs(void)
2513 {
2514         struct sys_device * dev;
2515         int i, size, error = 0;
2516
2517         error = sysdev_class_register(&ioapic_sysdev_class);
2518         if (error)
2519                 return error;
2520
2521         for (i = 0; i < nr_ioapics; i++ ) {
2522                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2523                         * sizeof(struct IO_APIC_route_entry);
2524                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2525                 if (!mp_ioapic_data[i]) {
2526                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2527                         continue;
2528                 }
2529                 memset(mp_ioapic_data[i], 0, size);
2530                 dev = &mp_ioapic_data[i]->dev;
2531                 dev->id = i;
2532                 dev->cls = &ioapic_sysdev_class;
2533                 error = sysdev_register(dev);
2534                 if (error) {
2535                         kfree(mp_ioapic_data[i]);
2536                         mp_ioapic_data[i] = NULL;
2537                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2538                         continue;
2539                 }
2540         }
2541
2542         return 0;
2543 }
2544
2545 device_initcall(ioapic_init_sysfs);
2546
2547 /* --------------------------------------------------------------------------
2548                           ACPI-based IOAPIC Configuration
2549    -------------------------------------------------------------------------- */
2550
2551 #ifdef CONFIG_ACPI
2552
2553 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2554 {
2555         union IO_APIC_reg_00 reg_00;
2556         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2557         physid_mask_t tmp;
2558         unsigned long flags;
2559         int i = 0;
2560
2561         /*
2562          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2563          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2564          * supports up to 16 on one shared APIC bus.
2565          *
2566          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2567          *      advantage of new APIC bus architecture.
2568          */
2569
2570         if (physids_empty(apic_id_map))
2571                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2572
2573         spin_lock_irqsave(&ioapic_lock, flags);
2574         reg_00.raw = io_apic_read(ioapic, 0);
2575         spin_unlock_irqrestore(&ioapic_lock, flags);
2576
2577         if (apic_id >= get_physical_broadcast()) {
2578                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2579                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2580                 apic_id = reg_00.bits.ID;
2581         }
2582
2583         /*
2584          * Every APIC in a system must have a unique ID or we get lots of nice
2585          * 'stuck on smp_invalidate_needed IPI wait' messages.
2586          */
2587         if (check_apicid_used(apic_id_map, apic_id)) {
2588
2589                 for (i = 0; i < get_physical_broadcast(); i++) {
2590                         if (!check_apicid_used(apic_id_map, i))
2591                                 break;
2592                 }
2593
2594                 if (i == get_physical_broadcast())
2595                         panic("Max apic_id exceeded!\n");
2596
2597                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2598                         "trying %d\n", ioapic, apic_id, i);
2599
2600                 apic_id = i;
2601         }
2602
2603         tmp = apicid_to_cpu_present(apic_id);
2604         physids_or(apic_id_map, apic_id_map, tmp);
2605
2606         if (reg_00.bits.ID != apic_id) {
2607                 reg_00.bits.ID = apic_id;
2608
2609                 spin_lock_irqsave(&ioapic_lock, flags);
2610                 io_apic_write(ioapic, 0, reg_00.raw);
2611                 reg_00.raw = io_apic_read(ioapic, 0);
2612                 spin_unlock_irqrestore(&ioapic_lock, flags);
2613
2614                 /* Sanity check */
2615                 if (reg_00.bits.ID != apic_id) {
2616                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2617                         return -1;
2618                 }
2619         }
2620
2621         apic_printk(APIC_VERBOSE, KERN_INFO
2622                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2623
2624         return apic_id;
2625 }
2626
2627
2628 int __init io_apic_get_version (int ioapic)
2629 {
2630         union IO_APIC_reg_01    reg_01;
2631         unsigned long flags;
2632
2633         spin_lock_irqsave(&ioapic_lock, flags);
2634         reg_01.raw = io_apic_read(ioapic, 1);
2635         spin_unlock_irqrestore(&ioapic_lock, flags);
2636
2637         return reg_01.bits.version;
2638 }
2639
2640
2641 int __init io_apic_get_redir_entries (int ioapic)
2642 {
2643         union IO_APIC_reg_01    reg_01;
2644         unsigned long flags;
2645
2646         spin_lock_irqsave(&ioapic_lock, flags);
2647         reg_01.raw = io_apic_read(ioapic, 1);
2648         spin_unlock_irqrestore(&ioapic_lock, flags);
2649
2650         return reg_01.bits.entries;
2651 }
2652
2653
2654 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2655 {
2656         struct IO_APIC_route_entry entry;
2657         unsigned long flags;
2658
2659         if (!IO_APIC_IRQ(irq)) {
2660                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2661                         ioapic);
2662                 return -EINVAL;
2663         }
2664
2665         /*
2666          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2667          * Note that we mask (disable) IRQs now -- these get enabled when the
2668          * corresponding device driver registers for this IRQ.
2669          */
2670
2671         memset(&entry,0,sizeof(entry));
2672
2673         entry.delivery_mode = INT_DELIVERY_MODE;
2674         entry.dest_mode = INT_DEST_MODE;
2675         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2676         entry.trigger = edge_level;
2677         entry.polarity = active_high_low;
2678         entry.mask  = 1;
2679
2680         /*
2681          * IRQs < 16 are already in the irq_2_pin[] map
2682          */
2683         if (irq >= 16)
2684                 add_pin_to_irq(irq, ioapic, pin);
2685
2686         entry.vector = assign_irq_vector(irq);
2687
2688         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2689                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2690                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2691                 edge_level, active_high_low);
2692
2693         ioapic_register_intr(irq, entry.vector, edge_level);
2694
2695         if (!ioapic && (irq < 16))
2696                 disable_8259A_irq(irq);
2697
2698         spin_lock_irqsave(&ioapic_lock, flags);
2699         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2700         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2701         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2702         spin_unlock_irqrestore(&ioapic_lock, flags);
2703
2704         return 0;
2705 }
2706
2707 #endif /* CONFIG_ACPI */