1 /* Generic MTRR (Memory Type Range Register) driver.
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/pci.h>
37 #include <linux/smp.h>
38 #include <linux/cpu.h>
39 #include <linux/mutex.h>
43 #include <asm/uaccess.h>
44 #include <asm/processor.h>
48 u32 num_var_ranges = 0;
50 unsigned int *usage_table;
51 static DEFINE_MUTEX(mtrr_mutex);
53 u32 size_or_mask, size_and_mask;
55 static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {};
57 struct mtrr_ops * mtrr_if = NULL;
59 static void set_mtrr(unsigned int reg, unsigned long base,
60 unsigned long size, mtrr_type type);
63 extern int arr3_protected;
65 #define arr3_protected 0
68 void set_mtrr_ops(struct mtrr_ops * ops)
70 if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
71 mtrr_ops[ops->vendor] = ops;
74 /* Returns non-zero if we have the write-combining memory type */
75 static int have_wrcomb(void)
80 if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
81 /* ServerWorks LE chipsets < rev 6 have problems with write-combining
82 Don't allow it and leave room for other chipsets to be tagged */
83 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
84 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
85 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
87 printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
92 /* Intel 450NX errata # 23. Non ascending cacheline evictions to
93 write combining memory may resulting in data corruption */
94 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
95 dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
96 printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
102 return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0);
105 /* This function returns the number of variable MTRRs */
106 static void __init set_num_var_ranges(void)
108 unsigned long config = 0, dummy;
111 rdmsr(MTRRcap_MSR, config, dummy);
112 } else if (is_cpu(AMD))
114 else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
116 num_var_ranges = config & 0xff;
119 static void __init init_table(void)
123 max = num_var_ranges;
124 if ((usage_table = kmalloc(max * sizeof *usage_table, GFP_KERNEL))
126 printk(KERN_ERR "mtrr: could not allocate\n");
129 for (i = 0; i < max; i++)
133 struct set_mtrr_data {
136 unsigned long smp_base;
137 unsigned long smp_size;
138 unsigned int smp_reg;
144 static void ipi_handler(void *info)
145 /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs.
149 struct set_mtrr_data *data = info;
152 local_irq_save(flags);
154 atomic_dec(&data->count);
155 while(!atomic_read(&data->gate))
158 /* The master has cleared me to execute */
159 if (data->smp_reg != ~0U)
160 mtrr_if->set(data->smp_reg, data->smp_base,
161 data->smp_size, data->smp_type);
165 atomic_dec(&data->count);
166 while(atomic_read(&data->gate))
169 atomic_dec(&data->count);
170 local_irq_restore(flags);
176 * set_mtrr - update mtrrs on all processors
177 * @reg: mtrr in question
182 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
184 * 1. Send IPI to do the following:
185 * 2. Disable Interrupts
186 * 3. Wait for all procs to do so
187 * 4. Enter no-fill cache mode
191 * 8. Disable all range registers
192 * 9. Update the MTRRs
193 * 10. Enable all range registers
194 * 11. Flush all TLBs and caches again
195 * 12. Enter normal cache mode and reenable caching
197 * 14. Wait for buddies to catch up
198 * 15. Enable interrupts.
200 * What does that mean for us? Well, first we set data.count to the number
201 * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait
202 * until it hits 0 and proceed. We set the data.gate flag and reset data.count.
203 * Meanwhile, they are waiting for that flag to be set. Once it's set, each
204 * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it
205 * differently, so we call mtrr_if->set() callback and let them take care of it.
206 * When they're done, they again decrement data->count and wait for data.gate to
208 * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag.
209 * Everyone then enables interrupts and we all continue on.
211 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
214 static void set_mtrr(unsigned int reg, unsigned long base,
215 unsigned long size, mtrr_type type)
217 struct set_mtrr_data data;
221 data.smp_base = base;
222 data.smp_size = size;
223 data.smp_type = type;
224 atomic_set(&data.count, num_booting_cpus() - 1);
225 atomic_set(&data.gate,0);
227 /* Start the ball rolling on other CPUs */
228 if (smp_call_function(ipi_handler, &data, 1, 0) != 0)
229 panic("mtrr: timed out waiting for other CPUs\n");
231 local_irq_save(flags);
233 while(atomic_read(&data.count))
236 /* ok, reset count and toggle gate */
237 atomic_set(&data.count, num_booting_cpus() - 1);
238 atomic_set(&data.gate,1);
240 /* do our MTRR business */
243 * We use this same function to initialize the mtrrs on boot.
244 * The state of the boot cpu's mtrrs has been saved, and we want
245 * to replicate across all the APs.
246 * If we're doing that @reg is set to something special...
249 mtrr_if->set(reg,base,size,type);
251 /* wait for the others */
252 while(atomic_read(&data.count))
255 atomic_set(&data.count, num_booting_cpus() - 1);
256 atomic_set(&data.gate,0);
259 * Wait here for everyone to have seen the gate change
260 * So we're the last ones to touch 'data'
262 while(atomic_read(&data.count))
265 local_irq_restore(flags);
269 * mtrr_add_page - Add a memory type region
270 * @base: Physical base address of region in pages (in units of 4 kB!)
271 * @size: Physical size of region in pages (4 kB)
272 * @type: Type of MTRR desired
273 * @increment: If this is true do usage counting on the region
275 * Memory type region registers control the caching on newer Intel and
276 * non Intel processors. This function allows drivers to request an
277 * MTRR is added. The details and hardware specifics of each processor's
278 * implementation are hidden from the caller, but nevertheless the
279 * caller should expect to need to provide a power of two size on an
280 * equivalent power of two boundary.
282 * If the region cannot be added either because all regions are in use
283 * or the CPU cannot support it a negative value is returned. On success
284 * the register number for this entry is returned, but should be treated
287 * On a multiprocessor machine the changes are made to all processors.
288 * This is required on x86 by the Intel processors.
290 * The available types are
292 * %MTRR_TYPE_UNCACHABLE - No caching
294 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
296 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
298 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
300 * BUGS: Needs a quiet flag for the cases where drivers do not mind
301 * failures and do not wish system log messages to be sent.
304 int mtrr_add_page(unsigned long base, unsigned long size,
305 unsigned int type, char increment)
316 if ((error = mtrr_if->validate_add_page(base,size,type)))
319 if (type >= MTRR_NUM_TYPES) {
320 printk(KERN_WARNING "mtrr: type: %u invalid\n", type);
324 /* If the type is WC, check that this processor supports it */
325 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
327 "mtrr: your processor doesn't support write-combining\n");
331 if (base & size_or_mask || size & size_or_mask) {
332 printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n");
338 /* No CPU hotplug when we change MTRR entries */
340 /* Search for existing MTRR */
341 mutex_lock(&mtrr_mutex);
342 for (i = 0; i < num_var_ranges; ++i) {
343 mtrr_if->get(i, &lbase, &lsize, <ype);
344 if (base >= lbase + lsize)
346 if ((base < lbase) && (base + size <= lbase))
348 /* At this point we know there is some kind of overlap/enclosure */
349 if ((base < lbase) || (base + size > lbase + lsize)) {
351 "mtrr: 0x%lx000,0x%lx000 overlaps existing"
352 " 0x%lx000,0x%x000\n", base, size, lbase,
356 /* New region is enclosed by an existing region */
358 if (type == MTRR_TYPE_UNCACHABLE)
360 printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
361 base, size, mtrr_attrib_to_str(ltype),
362 mtrr_attrib_to_str(type));
370 /* Search for an empty MTRR */
371 i = mtrr_if->get_free_region(base, size);
373 set_mtrr(i, base, size, type);
376 printk(KERN_INFO "mtrr: no more MTRRs available\n");
379 mutex_unlock(&mtrr_mutex);
380 unlock_cpu_hotplug();
384 static int mtrr_check(unsigned long base, unsigned long size)
386 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
388 "mtrr: size and base must be multiples of 4 kiB\n");
390 "mtrr: size: 0x%lx base: 0x%lx\n", size, base);
398 * mtrr_add - Add a memory type region
399 * @base: Physical base address of region
400 * @size: Physical size of region
401 * @type: Type of MTRR desired
402 * @increment: If this is true do usage counting on the region
404 * Memory type region registers control the caching on newer Intel and
405 * non Intel processors. This function allows drivers to request an
406 * MTRR is added. The details and hardware specifics of each processor's
407 * implementation are hidden from the caller, but nevertheless the
408 * caller should expect to need to provide a power of two size on an
409 * equivalent power of two boundary.
411 * If the region cannot be added either because all regions are in use
412 * or the CPU cannot support it a negative value is returned. On success
413 * the register number for this entry is returned, but should be treated
416 * On a multiprocessor machine the changes are made to all processors.
417 * This is required on x86 by the Intel processors.
419 * The available types are
421 * %MTRR_TYPE_UNCACHABLE - No caching
423 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
425 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
427 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
429 * BUGS: Needs a quiet flag for the cases where drivers do not mind
430 * failures and do not wish system log messages to be sent.
434 mtrr_add(unsigned long base, unsigned long size, unsigned int type,
437 if (mtrr_check(base, size))
439 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
444 * mtrr_del_page - delete a memory type region
445 * @reg: Register returned by mtrr_add
446 * @base: Physical base address
447 * @size: Size of region
449 * If register is supplied then base and size are ignored. This is
450 * how drivers should call it.
452 * Releases an MTRR region. If the usage count drops to zero the
453 * register is freed and the region returns to default state.
454 * On success the register is returned, on failure a negative error
458 int mtrr_del_page(int reg, unsigned long base, unsigned long size)
469 max = num_var_ranges;
470 /* No CPU hotplug when we change MTRR entries */
472 mutex_lock(&mtrr_mutex);
474 /* Search for existing MTRR */
475 for (i = 0; i < max; ++i) {
476 mtrr_if->get(i, &lbase, &lsize, <ype);
477 if (lbase == base && lsize == size) {
483 printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base,
489 printk(KERN_WARNING "mtrr: register: %d too big\n", reg);
492 if (is_cpu(CYRIX) && !use_intel()) {
493 if ((reg == 3) && arr3_protected) {
494 printk(KERN_WARNING "mtrr: ARR3 cannot be changed\n");
498 mtrr_if->get(reg, &lbase, &lsize, <ype);
500 printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg);
503 if (usage_table[reg] < 1) {
504 printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg);
507 if (--usage_table[reg] < 1)
508 set_mtrr(reg, 0, 0, 0);
511 mutex_unlock(&mtrr_mutex);
512 unlock_cpu_hotplug();
516 * mtrr_del - delete a memory type region
517 * @reg: Register returned by mtrr_add
518 * @base: Physical base address
519 * @size: Size of region
521 * If register is supplied then base and size are ignored. This is
522 * how drivers should call it.
524 * Releases an MTRR region. If the usage count drops to zero the
525 * register is freed and the region returns to default state.
526 * On success the register is returned, on failure a negative error
531 mtrr_del(int reg, unsigned long base, unsigned long size)
533 if (mtrr_check(base, size))
535 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
538 EXPORT_SYMBOL(mtrr_add);
539 EXPORT_SYMBOL(mtrr_del);
542 * These should be called implicitly, but we can't yet until all the initcall
545 extern void amd_init_mtrr(void);
546 extern void cyrix_init_mtrr(void);
547 extern void centaur_init_mtrr(void);
549 static void __init init_ifs(void)
551 #ifndef CONFIG_X86_64
558 /* The suspend/resume methods are only for CPU without MTRR. CPU using generic
559 * MTRR driver doesn't require this
567 static struct mtrr_value * mtrr_state;
569 static int mtrr_save(struct sys_device * sysdev, pm_message_t state)
572 int size = num_var_ranges * sizeof(struct mtrr_value);
574 mtrr_state = kmalloc(size,GFP_ATOMIC);
576 memset(mtrr_state,0,size);
580 for (i = 0; i < num_var_ranges; i++) {
582 &mtrr_state[i].lbase,
583 &mtrr_state[i].lsize,
584 &mtrr_state[i].ltype);
589 static int mtrr_restore(struct sys_device * sysdev)
593 for (i = 0; i < num_var_ranges; i++) {
594 if (mtrr_state[i].lsize)
598 mtrr_state[i].ltype);
606 static struct sysdev_driver mtrr_sysdev_driver = {
607 .suspend = mtrr_save,
608 .resume = mtrr_restore,
613 * mtrr_bp_init - initialize mtrrs on the boot CPU
615 * This needs to be called early; before any of the other CPUs are
616 * initialized (i.e. before smp_init()).
619 void __init mtrr_bp_init(void)
624 mtrr_if = &generic_mtrr_ops;
625 size_or_mask = 0xff000000; /* 36 bits */
626 size_and_mask = 0x00f00000;
628 /* This is an AMD specific MSR, but we assume(hope?) that
629 Intel will implement it to when they extend the address
631 if (cpuid_eax(0x80000000) >= 0x80000008) {
633 phys_addr = cpuid_eax(0x80000008) & 0xff;
634 /* CPUID workaround for Intel 0F33/0F34 CPU */
635 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
636 boot_cpu_data.x86 == 0xF &&
637 boot_cpu_data.x86_model == 0x3 &&
638 (boot_cpu_data.x86_mask == 0x3 ||
639 boot_cpu_data.x86_mask == 0x4))
642 size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
643 size_and_mask = ~size_or_mask & 0xfff00000;
644 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
645 boot_cpu_data.x86 == 6) {
646 /* VIA C* family have Intel style MTRRs, but
648 size_or_mask = 0xfff00000; /* 32 bits */
652 switch (boot_cpu_data.x86_vendor) {
654 if (cpu_has_k6_mtrr) {
655 /* Pre-Athlon (K6) AMD CPU MTRRs */
656 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
657 size_or_mask = 0xfff00000; /* 32 bits */
661 case X86_VENDOR_CENTAUR:
662 if (cpu_has_centaur_mcr) {
663 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
664 size_or_mask = 0xfff00000; /* 32 bits */
668 case X86_VENDOR_CYRIX:
669 if (cpu_has_cyrix_arr) {
670 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
671 size_or_mask = 0xfff00000; /* 32 bits */
681 set_num_var_ranges();
688 void mtrr_ap_init(void)
692 if (!mtrr_if || !use_intel())
695 * Ideally we should hold mtrr_mutex here to avoid mtrr entries changed,
696 * but this routine will be called in cpu boot time, holding the lock
697 * breaks it. This routine is called in two cases: 1.very earily time
698 * of software resume, when there absolutely isn't mtrr entry changes;
699 * 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to
700 * prevent mtrr entry changes
702 local_irq_save(flags);
706 local_irq_restore(flags);
709 static int __init mtrr_init_finialize(void)
716 /* The CPUs haven't MTRR and seemes not support SMP. They have
717 * specific drivers, we use a tricky method to support
718 * suspend/resume for them.
719 * TBD: is there any system with such CPU which supports
720 * suspend/resume? if no, we should remove the code.
722 sysdev_driver_register(&cpu_sysdev_class,
723 &mtrr_sysdev_driver);
727 subsys_initcall(mtrr_init_finialize);