2 * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is the same as v1, but adds voltage scaling.
12 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C)
13 * voltage scaling support has currently been disabled in this driver
14 * until we have code that gets it right.
15 * Version 3 of longhaul got renamed to Powersaver and redesigned
16 * to use the POWERSAVER MSR at 0x110a.
17 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
18 * It's pretty much the same feature wise to longhaul v2, though
19 * there is provision for scaling FSB too, but this doesn't work
20 * too well in practice so we don't even try to use this.
22 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/cpufreq.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
35 #include <asm/timex.h>
38 #include <linux/acpi.h>
39 #include <acpi/processor.h>
43 #define PFX "longhaul: "
45 #define TYPE_LONGHAUL_V1 1
46 #define TYPE_LONGHAUL_V2 2
47 #define TYPE_POWERSAVER 3
53 #define CPU_NEHEMIAH 5
54 #define CPU_NEHEMIAH_C 6
57 #define USE_ACPI_C3 (1 << 1)
58 #define USE_NORTHBRIDGE (1 << 2)
59 #define USE_VT8235 (1 << 3)
62 static unsigned int numscales=16;
63 static unsigned int fsb;
65 static struct mV_pos *vrm_mV_table;
66 static unsigned char *mV_vrm_table;
71 static struct f_msr f_msr_table[32];
73 static unsigned int highest_speed, lowest_speed; /* kHz */
74 static unsigned int minmult, maxmult;
75 static int can_scale_voltage;
76 static struct acpi_processor *pr = NULL;
77 static struct acpi_processor_cx *cx = NULL;
78 static u8 longhaul_flags;
79 static u8 longhaul_pos;
81 /* Module parameters */
82 static int scale_voltage;
84 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
87 /* Clock ratios multiplied by 10 */
88 static int clock_ratio[32];
89 static int eblcr_table[32];
90 static int longhaul_version;
91 static struct cpufreq_frequency_table *longhaul_table;
93 #ifdef CONFIG_CPU_FREQ_DEBUG
94 static char speedbuffer[8];
96 static char *print_speed(int speed)
99 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
104 snprintf(speedbuffer, sizeof(speedbuffer),
105 "%dGHz", speed/1000);
107 snprintf(speedbuffer, sizeof(speedbuffer),
108 "%d.%dGHz", speed/1000, (speed%1000)/100);
115 static unsigned int calc_speed(int mult)
126 static int longhaul_get_cpu_mult(void)
128 unsigned long invalue=0,lo, hi;
130 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
131 invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
132 if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
136 return eblcr_table[invalue];
139 /* For processor with BCR2 MSR */
141 static void do_longhaul1(unsigned int clock_ratio_index)
145 rdmsrl(MSR_VIA_BCR2, bcr2.val);
146 /* Enable software clock multiplier */
147 bcr2.bits.ESOFTBF = 1;
148 bcr2.bits.CLOCKMUL = clock_ratio_index;
150 /* Sync to timer tick */
152 /* Change frequency on next halt or sleep */
153 wrmsrl(MSR_VIA_BCR2, bcr2.val);
154 /* Invoke transition */
155 ACPI_FLUSH_CPU_CACHE();
158 /* Disable software clock multiplier */
160 rdmsrl(MSR_VIA_BCR2, bcr2.val);
161 bcr2.bits.ESOFTBF = 0;
162 wrmsrl(MSR_VIA_BCR2, bcr2.val);
165 /* For processor with Longhaul MSR */
167 static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
169 union msr_longhaul longhaul;
173 dest_pos = f_msr_table[clock_ratio_index].pos;
175 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
176 /* Setup new frequency */
177 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
178 longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
179 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
180 /* Setup new voltage */
181 if (can_scale_voltage)
182 longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm;
183 /* Sync to timer tick */
185 /* Raise voltage if necessary */
186 if (can_scale_voltage && longhaul_pos < dest_pos) {
187 longhaul.bits.EnableSoftVID = 1;
188 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
191 ACPI_FLUSH_CPU_CACHE();
194 ACPI_FLUSH_CPU_CACHE();
197 /* Dummy op - must do something useless after P_LVL3
199 t = inl(acpi_fadt.xpm_tmr_blk.address);
201 longhaul.bits.EnableSoftVID = 0;
202 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
203 longhaul_pos = dest_pos;
206 /* Change frequency on next halt or sleep */
207 longhaul.bits.EnableSoftBusRatio = 1;
208 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
210 ACPI_FLUSH_CPU_CACHE();
213 ACPI_FLUSH_CPU_CACHE();
216 /* Dummy op - must do something useless after P_LVL3 read */
217 t = inl(acpi_fadt.xpm_tmr_blk.address);
219 /* Disable bus ratio bit */
220 longhaul.bits.EnableSoftBusRatio = 0;
221 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
223 /* Reduce voltage if necessary */
224 if (can_scale_voltage && longhaul_pos > dest_pos) {
225 longhaul.bits.EnableSoftVID = 1;
226 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
229 ACPI_FLUSH_CPU_CACHE();
232 ACPI_FLUSH_CPU_CACHE();
235 /* Dummy op - must do something useless after P_LVL3
237 t = inl(acpi_fadt.xpm_tmr_blk.address);
239 longhaul.bits.EnableSoftVID = 0;
240 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
241 longhaul_pos = dest_pos;
246 * longhaul_set_cpu_frequency()
247 * @clock_ratio_index : bitpattern of the new multiplier.
249 * Sets a new clock ratio.
252 static void longhaul_setstate(unsigned int clock_ratio_index)
255 struct cpufreq_freqs freqs;
256 static unsigned int old_ratio=-1;
258 unsigned int pic1_mask, pic2_mask;
260 if (old_ratio == clock_ratio_index)
262 old_ratio = clock_ratio_index;
264 mult = clock_ratio[clock_ratio_index];
268 speed = calc_speed(mult);
269 if ((speed > highest_speed) || (speed < lowest_speed))
272 freqs.old = calc_speed(longhaul_get_cpu_mult());
274 freqs.cpu = 0; /* longhaul.c is UP only driver */
276 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
278 dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
279 fsb, mult/10, mult%10, print_speed(speed/1000));
282 local_irq_save(flags);
284 pic2_mask = inb(0xA1);
285 pic1_mask = inb(0x21); /* works on C3. save mask. */
286 outb(0xFF,0xA1); /* Overkill */
287 outb(0xFE,0x21); /* TMR0 only */
289 if (longhaul_flags & USE_NORTHBRIDGE) {
290 /* Disable AGP and PCI arbiters */
292 } else if ((pr != NULL) && pr->flags.bm_control) {
293 /* Disable bus master arbitration */
294 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1,
295 ACPI_MTX_DO_NOT_LOCK);
297 switch (longhaul_version) {
300 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
301 * Software controlled multipliers only.
303 * *NB* Until we get voltage scaling working v1 & v2 are the same code.
304 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5b] and Ezra [C5C]
306 case TYPE_LONGHAUL_V1:
307 case TYPE_LONGHAUL_V2:
308 do_longhaul1(clock_ratio_index);
312 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
313 * We can scale voltage with this too, but that's currently
314 * disabled until we come up with a decent 'match freq to voltage'
316 * When we add voltage scaling, we will also need to do the
317 * voltage/freq setting in order depending on the direction
318 * of scaling (like we do in powernow-k7.c)
319 * Nehemiah can do FSB scaling too, but this has never been proven
320 * to work in practice.
322 case TYPE_POWERSAVER:
323 if (longhaul_flags & USE_ACPI_C3) {
324 /* Don't allow wakeup */
325 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0,
326 ACPI_MTX_DO_NOT_LOCK);
327 do_powersaver(cx->address, clock_ratio_index);
329 do_powersaver(0, clock_ratio_index);
334 if (longhaul_flags & USE_NORTHBRIDGE) {
335 /* Enable arbiters */
337 } else if ((pr != NULL) && pr->flags.bm_control) {
338 /* Enable bus master arbitration */
339 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0,
340 ACPI_MTX_DO_NOT_LOCK);
342 outb(pic2_mask,0xA1); /* restore mask */
343 outb(pic1_mask,0x21);
345 local_irq_restore(flags);
348 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
352 * Centaur decided to make life a little more tricky.
353 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
354 * Samuel2 and above have to try and guess what the FSB is.
355 * We do this by assuming we booted at maximum multiplier, and interpolate
356 * between that value multiplied by possible FSBs and cpu_mhz which
357 * was calculated at boot time. Really ugly, but no other way to do this.
362 static int guess_fsb(int mult)
364 int speed = cpu_khz / 1000;
366 int speeds[] = { 666, 1000, 1333, 2000 };
369 for (i = 0; i < 4; i++) {
370 f_max = ((speeds[i] * mult) + 50) / 100;
371 f_max += (ROUNDING / 2);
372 f_min = f_max - ROUNDING;
373 if ((speed <= f_max) && (speed >= f_min))
374 return speeds[i] / 10;
380 static int __init longhaul_get_ranges(void)
382 unsigned int j, k = 0;
385 /* Get current frequency */
386 mult = longhaul_get_cpu_mult();
388 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
391 fsb = guess_fsb(mult);
393 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
396 /* Get max multiplier - as we always did.
397 * Longhaul MSR is usefull only when voltage scaling is enabled.
398 * C3 is booting at max anyway. */
400 /* Get min multiplier */
413 dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
414 minmult/10, minmult%10, maxmult/10, maxmult%10);
416 highest_speed = calc_speed(maxmult);
417 lowest_speed = calc_speed(minmult);
418 dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
419 print_speed(lowest_speed/1000),
420 print_speed(highest_speed/1000));
422 if (lowest_speed == highest_speed) {
423 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
426 if (lowest_speed > highest_speed) {
427 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
428 lowest_speed, highest_speed);
432 longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
436 for (j=0; j < numscales; j++) {
438 ratio = clock_ratio[j];
441 if (ratio > maxmult || ratio < minmult)
443 longhaul_table[k].frequency = calc_speed(ratio);
444 longhaul_table[k].index = j;
448 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
450 kfree (longhaul_table);
458 static void __init longhaul_setup_voltagescaling(void)
460 union msr_longhaul longhaul;
461 struct mV_pos minvid, maxvid;
462 unsigned int j, speed, pos, kHz_step, numvscales;
465 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
466 if (!(longhaul.bits.RevisionID & 1)) {
467 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
471 if (!longhaul.bits.VRMRev) {
472 printk (KERN_INFO PFX "VRM 8.5\n");
473 vrm_mV_table = &vrm85_mV[0];
474 mV_vrm_table = &mV_vrm85[0];
476 printk (KERN_INFO PFX "Mobile VRM\n");
477 vrm_mV_table = &mobilevrm_mV[0];
478 mV_vrm_table = &mV_mobilevrm[0];
481 minvid = vrm_mV_table[longhaul.bits.MinimumVID];
482 maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
484 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
485 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
486 "Voltage scaling disabled.\n",
487 minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
491 if (minvid.mV == maxvid.mV) {
492 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
493 "both %d.%03d. Voltage scaling disabled\n",
494 maxvid.mV/1000, maxvid.mV%1000);
498 /* How many voltage steps */
499 numvscales = maxvid.pos - minvid.pos + 1;
503 "%d possible voltage scales\n",
504 maxvid.mV/1000, maxvid.mV%1000,
505 minvid.mV/1000, minvid.mV%1000,
508 /* Calculate max frequency at min voltage */
509 j = longhaul.bits.MinMHzBR;
510 if (longhaul.bits.MinMHzBR4)
512 min_vid_speed = eblcr_table[j];
513 if (min_vid_speed == -1)
515 switch (longhaul.bits.MinMHzFSB) {
517 min_vid_speed *= 13333;
520 min_vid_speed *= 10000;
523 min_vid_speed *= 6666;
529 if (min_vid_speed >= highest_speed)
531 /* Calculate kHz for one voltage step */
532 kHz_step = (highest_speed - min_vid_speed) / numvscales;
535 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
536 speed = longhaul_table[j].frequency;
537 if (speed > min_vid_speed)
538 pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
541 f_msr_table[longhaul_table[j].index].vrm = mV_vrm_table[pos];
542 f_msr_table[longhaul_table[j].index].pos = pos;
546 longhaul_pos = maxvid.pos;
547 can_scale_voltage = 1;
548 printk(KERN_INFO PFX "Voltage scaling enabled. "
549 "Use of \"conservative\" governor is highly recommended.\n");
553 static int longhaul_verify(struct cpufreq_policy *policy)
555 return cpufreq_frequency_table_verify(policy, longhaul_table);
559 static int longhaul_target(struct cpufreq_policy *policy,
560 unsigned int target_freq, unsigned int relation)
562 unsigned int table_index = 0;
563 unsigned int new_clock_ratio = 0;
565 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
568 new_clock_ratio = longhaul_table[table_index].index & 0xFF;
570 longhaul_setstate(new_clock_ratio);
576 static unsigned int longhaul_get(unsigned int cpu)
580 return calc_speed(longhaul_get_cpu_mult());
583 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
585 void *context, void **return_value)
587 struct acpi_device *d;
589 if ( acpi_bus_get_device(obj_handle, &d) ) {
592 *return_value = (void *)acpi_driver_data(d);
596 /* VIA don't support PM2 reg, but have something similar */
597 static int enable_arbiter_disable(void)
603 /* Find PLE133 host bridge */
605 dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0, NULL);
606 /* Find CLE266 host bridge */
609 dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_862X_0, NULL);
610 /* Find CN400 V-Link host bridge */
612 dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
616 /* Enable access to port 0x22 */
617 pci_read_config_byte(dev, reg, &pci_cmd);
618 if (!(pci_cmd & 1<<7)) {
620 pci_write_config_byte(dev, reg, pci_cmd);
621 pci_read_config_byte(dev, reg, &pci_cmd);
622 if (!(pci_cmd & 1<<7)) {
624 "Can't enable access to port 0x22.\n");
633 static int longhaul_setup_vt8235(void)
638 /* Find VT8235 southbridge */
639 dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
641 /* Set transition time to max */
642 pci_read_config_byte(dev, 0xec, &pci_cmd);
643 pci_cmd &= ~(1 << 2);
644 pci_write_config_byte(dev, 0xec, pci_cmd);
645 pci_read_config_byte(dev, 0xe4, &pci_cmd);
646 pci_cmd &= ~(1 << 7);
647 pci_write_config_byte(dev, 0xe4, pci_cmd);
648 pci_read_config_byte(dev, 0xe5, &pci_cmd);
650 pci_write_config_byte(dev, 0xe5, pci_cmd);
656 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
658 struct cpuinfo_x86 *c = cpu_data;
663 /* Check what we have on this motherboard */
664 switch (c->x86_model) {
666 cpu_model = CPU_SAMUEL;
667 cpuname = "C3 'Samuel' [C5A]";
668 longhaul_version = TYPE_LONGHAUL_V1;
669 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
670 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
674 longhaul_version = TYPE_LONGHAUL_V1;
675 switch (c->x86_mask) {
677 cpu_model = CPU_SAMUEL2;
678 cpuname = "C3 'Samuel 2' [C5B]";
679 /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */
680 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
681 memcpy (eblcr_table, samuel2_eblcr, sizeof(samuel2_eblcr));
684 if (c->x86_mask < 8) {
685 cpu_model = CPU_SAMUEL2;
686 cpuname = "C3 'Samuel 2' [C5B]";
688 cpu_model = CPU_EZRA;
689 cpuname = "C3 'Ezra' [C5C]";
691 memcpy (clock_ratio, ezra_clock_ratio, sizeof(ezra_clock_ratio));
692 memcpy (eblcr_table, ezra_eblcr, sizeof(ezra_eblcr));
698 cpu_model = CPU_EZRA_T;
699 cpuname = "C3 'Ezra-T' [C5M]";
700 longhaul_version = TYPE_POWERSAVER;
702 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
703 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
707 longhaul_version = TYPE_POWERSAVER;
710 nehemiah_clock_ratio,
711 sizeof(nehemiah_clock_ratio));
712 memcpy(eblcr_table, nehemiah_eblcr, sizeof(nehemiah_eblcr));
713 switch (c->x86_mask) {
715 cpu_model = CPU_NEHEMIAH;
716 cpuname = "C3 'Nehemiah A' [C5XLOE]";
719 cpu_model = CPU_NEHEMIAH;
720 cpuname = "C3 'Nehemiah B' [C5XLOH]";
723 cpu_model = CPU_NEHEMIAH_C;
724 cpuname = "C3 'Nehemiah C' [C5P]";
734 printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
735 switch (longhaul_version) {
736 case TYPE_LONGHAUL_V1:
737 case TYPE_LONGHAUL_V2:
738 printk ("Longhaul v%d supported.\n", longhaul_version);
740 case TYPE_POWERSAVER:
741 printk ("Powersaver supported.\n");
746 vt8235_present = longhaul_setup_vt8235();
748 /* Find ACPI data for processor */
749 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
750 ACPI_UINT32_MAX, &longhaul_walk_callback,
753 /* Check ACPI support for C3 state */
754 if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
755 cx = &pr->power.states[ACPI_STATE_C3];
756 if (cx->address > 0 && cx->latency <= 1000) {
757 longhaul_flags |= USE_ACPI_C3;
758 goto print_support_type;
761 /* Check if northbridge is friendly */
762 if (enable_arbiter_disable()) {
763 longhaul_flags |= USE_NORTHBRIDGE;
764 goto print_support_type;
766 /* Use VT8235 southbridge if present */
767 if (longhaul_version == TYPE_POWERSAVER && vt8235_present) {
768 longhaul_flags |= USE_VT8235;
769 goto print_support_type;
771 /* Check ACPI support for bus master arbiter disable */
772 if ((pr == NULL) || !(pr->flags.bm_control)) {
774 "No ACPI support. Unsupported northbridge.\n");
779 if (longhaul_flags & USE_NORTHBRIDGE)
780 printk (KERN_INFO PFX "Using northbridge support.\n");
781 else if (longhaul_flags & USE_VT8235)
782 printk (KERN_INFO PFX "Using VT8235 support.\n");
784 printk (KERN_INFO PFX "Using ACPI support.\n");
786 ret = longhaul_get_ranges();
790 if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
791 longhaul_setup_voltagescaling();
793 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
794 policy->cpuinfo.transition_latency = 200000; /* nsec */
795 policy->cur = calc_speed(longhaul_get_cpu_mult());
797 ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
801 cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
806 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
808 cpufreq_frequency_table_put_attr(policy->cpu);
812 static struct freq_attr* longhaul_attr[] = {
813 &cpufreq_freq_attr_scaling_available_freqs,
817 static struct cpufreq_driver longhaul_driver = {
818 .verify = longhaul_verify,
819 .target = longhaul_target,
821 .init = longhaul_cpu_init,
822 .exit = __devexit_p(longhaul_cpu_exit),
824 .owner = THIS_MODULE,
825 .attr = longhaul_attr,
829 static int __init longhaul_init(void)
831 struct cpuinfo_x86 *c = cpu_data;
833 if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
837 if (num_online_cpus() > 1) {
838 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
842 #ifdef CONFIG_X86_IO_APIC
844 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
848 switch (c->x86_model) {
850 return cpufreq_register_driver(&longhaul_driver);
852 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
861 static void __exit longhaul_exit(void)
865 for (i=0; i < numscales; i++) {
866 if (clock_ratio[i] == maxmult) {
867 longhaul_setstate(i);
872 cpufreq_unregister_driver(&longhaul_driver);
873 kfree(longhaul_table);
876 module_param (scale_voltage, int, 0644);
877 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
879 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
880 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
881 MODULE_LICENSE ("GPL");
883 late_initcall(longhaul_init);
884 module_exit(longhaul_exit);