1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
24 DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
25 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
27 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
28 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
30 static int cachesize_override __cpuinitdata = -1;
31 static int disable_x86_fxsr __cpuinitdata;
32 static int disable_x86_serial_nr __cpuinitdata = 1;
33 static int disable_x86_sep __cpuinitdata;
35 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
37 extern int disable_pse;
39 static void __cpuinit default_init(struct cpuinfo_x86 * c)
41 /* Not much we can do here... */
42 /* Check if at least it has cpuid */
43 if (c->cpuid_level == -1) {
44 /* No cpuid. It must be an ancient CPU */
46 strcpy(c->x86_model_id, "486");
48 strcpy(c->x86_model_id, "386");
52 static struct cpu_dev __cpuinitdata default_cpu = {
53 .c_init = default_init,
54 .c_vendor = "Unknown",
56 static struct cpu_dev * this_cpu = &default_cpu;
58 static int __init cachesize_setup(char *str)
60 get_option (&str, &cachesize_override);
63 __setup("cachesize=", cachesize_setup);
65 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
70 if (cpuid_eax(0x80000000) < 0x80000004)
73 v = (unsigned int *) c->x86_model_id;
74 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
75 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
76 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
77 c->x86_model_id[48] = 0;
79 /* Intel chips right-justify this string for some dumb reason;
80 undo that brain damage */
81 p = q = &c->x86_model_id[0];
87 while ( q <= &c->x86_model_id[48] )
88 *q++ = '\0'; /* Zero-pad the rest */
95 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
97 unsigned int n, dummy, ecx, edx, l2size;
99 n = cpuid_eax(0x80000000);
101 if (n >= 0x80000005) {
102 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
103 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
104 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
105 c->x86_cache_size=(ecx>>24)+(edx>>24);
108 if (n < 0x80000006) /* Some chips just has a large L1. */
111 ecx = cpuid_ecx(0x80000006);
114 /* do processor-specific cache resizing */
115 if (this_cpu->c_size_cache)
116 l2size = this_cpu->c_size_cache(c,l2size);
118 /* Allow user to override all this if necessary. */
119 if (cachesize_override != -1)
120 l2size = cachesize_override;
123 return; /* Again, no L2 cache is possible */
125 c->x86_cache_size = l2size;
127 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
131 /* Naming convention should be: <Name> [(<Codename>)] */
132 /* This table only is used unless init_<vendor>() below doesn't set it; */
133 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
135 /* Look up CPU names by table lookup. */
136 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
138 struct cpu_model_info *info;
140 if ( c->x86_model >= 16 )
141 return NULL; /* Range check */
146 info = this_cpu->c_models;
148 while (info && info->family) {
149 if (info->family == c->x86)
150 return info->model_names[c->x86_model];
153 return NULL; /* Not found */
157 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
159 char *v = c->x86_vendor_id;
163 for (i = 0; i < X86_VENDOR_NUM; i++) {
165 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
166 (cpu_devs[i]->c_ident[1] &&
167 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
170 this_cpu = cpu_devs[i];
177 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
178 printk(KERN_ERR "CPU: Your system may be unstable.\n");
180 c->x86_vendor = X86_VENDOR_UNKNOWN;
181 this_cpu = &default_cpu;
185 static int __init x86_fxsr_setup(char * s)
187 /* Tell all the other CPU's to not use it... */
188 disable_x86_fxsr = 1;
191 * ... and clear the bits early in the boot_cpu_data
192 * so that the bootup process doesn't try to do this
195 clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability);
196 clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability);
199 __setup("nofxsr", x86_fxsr_setup);
202 static int __init x86_sep_setup(char * s)
207 __setup("nosep", x86_sep_setup);
210 /* Standard macro to see if a specific flag is changeable */
211 static inline int flag_is_changeable_p(u32 flag)
225 : "=&r" (f1), "=&r" (f2)
228 return ((f1^f2) & flag) != 0;
232 /* Probe for the CPUID instruction */
233 static int __cpuinit have_cpuid_p(void)
235 return flag_is_changeable_p(X86_EFLAGS_ID);
238 /* Do minimum CPU detection early.
239 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
240 The others are not touched to avoid unwanted side effects.
242 WARNING: this function is only called on the BP. Don't add code here
243 that is supposed to run on all CPUs. */
244 static void __init early_cpu_detect(void)
246 struct cpuinfo_x86 *c = &boot_cpu_data;
248 c->x86_cache_alignment = 32;
253 /* Get vendor name */
254 cpuid(0x00000000, &c->cpuid_level,
255 (int *)&c->x86_vendor_id[0],
256 (int *)&c->x86_vendor_id[8],
257 (int *)&c->x86_vendor_id[4]);
259 get_cpu_vendor(c, 1);
262 if (c->cpuid_level >= 0x00000001) {
263 u32 junk, tfms, cap0, misc;
264 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
265 c->x86 = (tfms >> 8) & 15;
266 c->x86_model = (tfms >> 4) & 15;
268 c->x86 += (tfms >> 20) & 0xff;
270 c->x86_model += ((tfms >> 16) & 0xF) << 4;
271 c->x86_mask = tfms & 15;
273 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
277 static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
282 if (have_cpuid_p()) {
283 /* Get vendor name */
284 cpuid(0x00000000, &c->cpuid_level,
285 (int *)&c->x86_vendor_id[0],
286 (int *)&c->x86_vendor_id[8],
287 (int *)&c->x86_vendor_id[4]);
289 get_cpu_vendor(c, 0);
290 /* Initialize the standard set of capabilities */
291 /* Note that the vendor-specific code below might override */
293 /* Intel-defined flags: level 0x00000001 */
294 if ( c->cpuid_level >= 0x00000001 ) {
295 u32 capability, excap;
296 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
297 c->x86_capability[0] = capability;
298 c->x86_capability[4] = excap;
299 c->x86 = (tfms >> 8) & 15;
300 c->x86_model = (tfms >> 4) & 15;
302 c->x86 += (tfms >> 20) & 0xff;
304 c->x86_model += ((tfms >> 16) & 0xF) << 4;
305 c->x86_mask = tfms & 15;
307 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
309 c->apicid = (ebx >> 24) & 0xFF;
312 /* Have CPUID level 0 only - unheard of */
316 /* AMD-defined flags: level 0x80000001 */
317 xlvl = cpuid_eax(0x80000000);
318 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
319 if ( xlvl >= 0x80000001 ) {
320 c->x86_capability[1] = cpuid_edx(0x80000001);
321 c->x86_capability[6] = cpuid_ecx(0x80000001);
323 if ( xlvl >= 0x80000004 )
324 get_model_name(c); /* Default name */
328 early_intel_workaround(c);
331 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
335 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
337 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
338 /* Disable processor serial number */
340 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
342 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
343 printk(KERN_NOTICE "CPU serial number disabled.\n");
344 clear_bit(X86_FEATURE_PN, c->x86_capability);
346 /* Disabling the serial number may affect the cpuid level */
347 c->cpuid_level = cpuid_eax(0);
351 static int __init x86_serial_nr_setup(char *s)
353 disable_x86_serial_nr = 0;
356 __setup("serialnumber", x86_serial_nr_setup);
361 * This does the hard work of actually picking apart the CPU stuff...
363 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
367 c->loops_per_jiffy = loops_per_jiffy;
368 c->x86_cache_size = -1;
369 c->x86_vendor = X86_VENDOR_UNKNOWN;
370 c->cpuid_level = -1; /* CPUID not detected */
371 c->x86_model = c->x86_mask = 0; /* So far unknown... */
372 c->x86_vendor_id[0] = '\0'; /* Unset */
373 c->x86_model_id[0] = '\0'; /* Unset */
374 c->x86_max_cores = 1;
375 memset(&c->x86_capability, 0, sizeof c->x86_capability);
377 if (!have_cpuid_p()) {
378 /* First of all, decide if this is a 486 or higher */
379 /* It's a 486 if we can modify the AC flag */
380 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
388 printk(KERN_DEBUG "CPU: After generic identify, caps:");
389 for (i = 0; i < NCAPINTS; i++)
390 printk(" %08lx", c->x86_capability[i]);
393 if (this_cpu->c_identify) {
394 this_cpu->c_identify(c);
396 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
397 for (i = 0; i < NCAPINTS; i++)
398 printk(" %08lx", c->x86_capability[i]);
403 * Vendor-specific initialization. In this section we
404 * canonicalize the feature flags, meaning if there are
405 * features a certain CPU supports which CPUID doesn't
406 * tell us, CPUID claiming incorrect flags, or other bugs,
407 * we handle them here.
409 * At the end of this section, c->x86_capability better
410 * indicate the features this CPU genuinely supports!
412 if (this_cpu->c_init)
415 /* Disable the PN if appropriate */
416 squash_the_stupid_serial_number(c);
419 * The vendor-specific functions might have changed features. Now
420 * we do "generic changes."
425 clear_bit(X86_FEATURE_TSC, c->x86_capability);
428 if (disable_x86_fxsr) {
429 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
430 clear_bit(X86_FEATURE_XMM, c->x86_capability);
435 clear_bit(X86_FEATURE_SEP, c->x86_capability);
438 clear_bit(X86_FEATURE_PSE, c->x86_capability);
440 /* If the model name is still unset, do table lookup. */
441 if ( !c->x86_model_id[0] ) {
443 p = table_lookup_model(c);
445 strcpy(c->x86_model_id, p);
448 sprintf(c->x86_model_id, "%02x/%02x",
449 c->x86, c->x86_model);
452 /* Now the feature flags better reflect actual CPU features! */
454 printk(KERN_DEBUG "CPU: After all inits, caps:");
455 for (i = 0; i < NCAPINTS; i++)
456 printk(" %08lx", c->x86_capability[i]);
460 * On SMP, boot_cpu_data holds the common feature set between
461 * all CPUs; so make sure that we indicate which features are
462 * common between the CPUs. The first time this routine gets
463 * executed, c == &boot_cpu_data.
465 if ( c != &boot_cpu_data ) {
466 /* AND the already accumulated flags with these */
467 for ( i = 0 ; i < NCAPINTS ; i++ )
468 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
471 /* Init Machine Check Exception if available. */
474 if (c == &boot_cpu_data)
478 if (c == &boot_cpu_data)
485 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
487 u32 eax, ebx, ecx, edx;
488 int index_msb, core_bits;
490 cpuid(1, &eax, &ebx, &ecx, &edx);
492 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
495 smp_num_siblings = (ebx & 0xff0000) >> 16;
497 if (smp_num_siblings == 1) {
498 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
499 } else if (smp_num_siblings > 1 ) {
501 if (smp_num_siblings > NR_CPUS) {
502 printk(KERN_WARNING "CPU: Unsupported number of the "
503 "siblings %d", smp_num_siblings);
504 smp_num_siblings = 1;
508 index_msb = get_count_order(smp_num_siblings);
509 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
511 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
514 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
516 index_msb = get_count_order(smp_num_siblings) ;
518 core_bits = get_count_order(c->x86_max_cores);
520 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
521 ((1 << core_bits) - 1);
523 if (c->x86_max_cores > 1)
524 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
530 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
534 if (c->x86_vendor < X86_VENDOR_NUM)
535 vendor = this_cpu->c_vendor;
536 else if (c->cpuid_level >= 0)
537 vendor = c->x86_vendor_id;
539 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
540 printk("%s ", vendor);
542 if (!c->x86_model_id[0])
543 printk("%d86", c->x86);
545 printk("%s", c->x86_model_id);
547 if (c->x86_mask || c->cpuid_level >= 0)
548 printk(" stepping %02x\n", c->x86_mask);
553 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
556 * We're emulating future behavior.
557 * In the future, the cpu-specific init functions will be called implicitly
558 * via the magic of initcalls.
559 * They will insert themselves into the cpu_devs structure.
560 * Then, when cpu_init() is called, we can just iterate over that array.
563 extern int intel_cpu_init(void);
564 extern int cyrix_init_cpu(void);
565 extern int nsc_init_cpu(void);
566 extern int amd_init_cpu(void);
567 extern int centaur_init_cpu(void);
568 extern int transmeta_init_cpu(void);
569 extern int rise_init_cpu(void);
570 extern int nexgen_init_cpu(void);
571 extern int umc_init_cpu(void);
573 void __init early_cpu_init(void)
580 transmeta_init_cpu();
586 #ifdef CONFIG_DEBUG_PAGEALLOC
587 /* pse is not compatible with on-the-fly unmapping,
588 * disable it even if the cpus claim to support it.
590 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
595 * cpu_init() initializes state that is per-CPU. Some data is already
596 * initialized (naturally) in the bootstrap process, such as the GDT
597 * and IDT. We reload them nevertheless, this function acts as a
598 * 'CPU state barrier', nothing should get across.
600 void __cpuinit cpu_init(void)
602 int cpu = smp_processor_id();
603 struct tss_struct * t = &per_cpu(init_tss, cpu);
604 struct thread_struct *thread = ¤t->thread;
605 struct desc_struct *gdt;
606 __u32 stk16_off = (__u32)&per_cpu(cpu_16bit_stack, cpu);
607 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
609 if (cpu_test_and_set(cpu, cpu_initialized)) {
610 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
611 for (;;) local_irq_enable();
613 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
615 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
616 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
617 if (tsc_disable && cpu_has_tsc) {
618 printk(KERN_NOTICE "Disabling TSC...\n");
619 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
620 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
621 set_in_cr4(X86_CR4_TSD);
624 /* The CPU hotplug case */
625 if (cpu_gdt_descr->address) {
626 gdt = (struct desc_struct *)cpu_gdt_descr->address;
627 memset(gdt, 0, PAGE_SIZE);
631 * This is a horrible hack to allocate the GDT. The problem
632 * is that cpu_init() is called really early for the boot CPU
633 * (and hence needs bootmem) but much later for the secondary
634 * CPUs, when bootmem will have gone away
636 if (NODE_DATA(0)->bdata->node_bootmem_map) {
637 gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
638 /* alloc_bootmem_pages panics on failure, so no check */
639 memset(gdt, 0, PAGE_SIZE);
641 gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
642 if (unlikely(!gdt)) {
643 printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
650 * Initialize the per-CPU GDT with the boot GDT,
651 * and set up the GDT descriptor:
653 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
655 /* Set up GDT entry for 16bit stack */
656 *(__u64 *)(&gdt[GDT_ENTRY_ESPFIX_SS]) |=
657 ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) |
658 ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) |
659 (CPU_16BIT_STACK_SIZE - 1);
661 cpu_gdt_descr->size = GDT_SIZE - 1;
662 cpu_gdt_descr->address = (unsigned long)gdt;
664 load_gdt(cpu_gdt_descr);
665 load_idt(&idt_descr);
668 * Set up and load the per-CPU TSS and LDT
670 atomic_inc(&init_mm.mm_count);
671 current->active_mm = &init_mm;
673 enter_lazy_tlb(&init_mm, current);
675 load_esp0(t, thread);
678 load_LDT(&init_mm.context);
680 #ifdef CONFIG_DOUBLEFAULT
681 /* Set up doublefault TSS pointer in the GDT */
682 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
685 /* Clear %fs and %gs. */
686 asm volatile ("movl %0, %%fs; movl %0, %%gs" : : "r" (0));
688 /* Clear all 6 debug registers: */
697 * Force FPU initialization:
699 current_thread_info()->status = 0;
701 mxcsr_feature_mask_init();
704 #ifdef CONFIG_HOTPLUG_CPU
705 void __cpuinit cpu_uninit(void)
707 int cpu = raw_smp_processor_id();
708 cpu_clear(cpu, cpu_initialized);
711 per_cpu(cpu_tlbstate, cpu).state = 0;
712 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;