1 #include <linux/init.h>
2 #include <linux/bitops.h>
5 #include <asm/processor.h>
10 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
11 * misexecution of code under Linux. Owners of such processors should
12 * contact AMD for precise details and a CPU swap.
14 * See http://www.multimania.com/poulot/k6bug.html
15 * http://www.amd.com/K6/k6docs/revgd.html
17 * The following test is erm.. interesting. AMD neglected to up
18 * the chip setting when fixing the bug but they also tweaked some
19 * performance at the same time..
22 extern void vide(void);
23 __asm__(".align 4\nvide: ret");
25 static void __init init_amd(struct cpuinfo_x86 *c)
28 int mbytes = num_physpages >> (20-PAGE_SHIFT);
32 * FIXME: We should handle the K5 here. Set up the write
33 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
37 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
38 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
39 clear_bit(0*32+31, c->x86_capability);
41 r = get_model_name(c);
47 * General Systems BIOSen alias the cpu frequency registers
48 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
49 * drivers subsequently pokes it, and changes the CPU speed.
50 * Workaround : Remove the unneeded alias.
52 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
53 #define CBAR_ENB (0x80000000)
54 #define CBAR_KEY (0X000000CB)
55 if (c->x86_model==9 || c->x86_model == 10) {
56 if (inl (CBAR) & CBAR_ENB)
57 outl (0 | CBAR_KEY, CBAR);
61 if( c->x86_model < 6 )
63 /* Based on AMD doc 20734R - June 2000 */
64 if ( c->x86_model == 0 ) {
65 clear_bit(X86_FEATURE_APIC, c->x86_capability);
66 set_bit(X86_FEATURE_PGE, c->x86_capability);
71 if ( c->x86_model == 6 && c->x86_mask == 1 ) {
72 const int K6_BUG_LOOP = 1000000;
77 printk(KERN_INFO "AMD K6 stepping B detected - ");
80 * It looks like AMD fixed the 2.6.2 bug and improved indirect
81 * calls at the same time.
92 /* Knock these two lines out if it debugs out ok */
93 printk(KERN_INFO "AMD K6 stepping B detected - ");
95 if (d > 20*K6_BUG_LOOP)
96 printk("system stability may be impaired when more than 32 MB are used.\n");
98 printk("probably OK (after B9730xxxx).\n");
99 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
102 /* K6 with old style WHCR */
103 if (c->x86_model < 8 ||
104 (c->x86_model== 8 && c->x86_mask < 8)) {
105 /* We can only write allocate on the low 508Mb */
109 rdmsr(MSR_K6_WHCR, l, h);
110 if ((l&0x0000FFFF)==0) {
112 l=(1<<0)|((mbytes/4)<<1);
113 local_irq_save(flags);
115 wrmsr(MSR_K6_WHCR, l, h);
116 local_irq_restore(flags);
117 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
123 if ((c->x86_model == 8 && c->x86_mask >7) ||
124 c->x86_model == 9 || c->x86_model == 13) {
125 /* The more serious chips .. */
130 rdmsr(MSR_K6_WHCR, l, h);
131 if ((l&0xFFFF0000)==0) {
133 l=((mbytes>>2)<<22)|(1<<16);
134 local_irq_save(flags);
136 wrmsr(MSR_K6_WHCR, l, h);
137 local_irq_restore(flags);
138 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
142 /* Set MTRR capability flag if appropriate */
143 if (c->x86_model == 13 || c->x86_model == 9 ||
144 (c->x86_model == 8 && c->x86_mask >= 8))
145 set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
150 case 6: /* An Athlon/Duron */
152 /* Bit 15 of Athlon specific MSR 15, needs to be 0
153 * to enable SSE on Palomino/Morgan/Barton CPU's.
154 * If the BIOS didn't enable it already, enable it here.
156 if (c->x86_model >= 6 && c->x86_model <= 10) {
157 if (!cpu_has(c, X86_FEATURE_XMM)) {
158 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
159 rdmsr(MSR_K7_HWCR, l, h);
161 wrmsr(MSR_K7_HWCR, l, h);
162 set_bit(X86_FEATURE_XMM, c->x86_capability);
166 /* It's been determined by AMD that Athlons since model 8 stepping 1
167 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
168 * As per AMD technical note 27212 0.2
170 if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
171 rdmsr(MSR_K7_CLK_CTL, l, h);
172 if ((l & 0xfff00000) != 0x20000000) {
173 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
174 ((l & 0x000fffff)|0x20000000));
175 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
183 set_bit(X86_FEATURE_K8, c->x86_capability);
186 set_bit(X86_FEATURE_K7, c->x86_capability);
190 display_cacheinfo(c);
194 /* AMD dual core looks like HT but isn't really. Hide it from the
195 scheduler. This works around problems with the domain scheduler.
196 Also probably gives slightly better scheduling and disables
197 SMT nice which is harmful on dual core.
198 TBD tune the domain scheduler for dual core. */
199 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
200 smp_num_siblings = 1;
203 if (cpuid_eax(0x80000000) >= 0x80000008) {
204 c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
205 if (c->x86_num_cores & (c->x86_num_cores - 1))
206 c->x86_num_cores = 1;
210 static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
212 /* AMD errata T13 (order #21922) */
214 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
216 if (c->x86_model == 4 &&
217 (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
223 static struct cpu_dev amd_cpu_dev __initdata = {
225 .c_ident = { "AuthenticAMD" },
227 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
239 .c_identify = generic_identify,
240 .c_size_cache = amd_size_cache,
243 int __init amd_init_cpu(void)
245 cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
249 //early_arch_initcall(amd_init_cpu);