2 * arch/cris/arch-v32/drivers/nandflash.c
6 * Derived from drivers/mtd/nand/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/slab.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <asm/arch/memmap.h>
22 #include <hwregs/reg_map.h>
23 #include <hwregs/reg_rdwr.h>
24 #include <hwregs/gio_defs.h>
25 #include <hwregs/bif_core_defs.h>
33 /* Bitmask for control pins */
34 #define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
36 /* Bitmask for mtd nand control bits */
37 #define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)
40 static struct mtd_info *crisv32_mtd;
42 * hardware specific access to control-lines
44 static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
48 reg_gio_rw_pa_dout dout;
49 struct nand_chip *this = mtd->priv;
51 local_irq_save(flags);
53 /* control bits change */
54 if (ctrl & NAND_CTRL_CHANGE) {
55 dout = REG_RD(gio, regi_gio, rw_pa_dout);
56 dout.data &= ~PIN_BITMASK;
58 #if (CE_BIT == 4 && NAND_NCE == 1 && \
59 CLE_BIT == 5 && NAND_CLE == 2 && \
60 ALE_BIT == 6 && NAND_ALE == 4)
61 /* Pins in same order as control bits, but shifted.
62 * Optimize for this case; works for 2.6.18 */
63 dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT;
66 if (!(ctrl & NAND_NCE))
67 dout.data |= (1 << CE_BIT);
69 dout.data |= (1 << CLE_BIT);
71 dout.data |= (1 << ALE_BIT);
73 REG_WR(gio, regi_gio, rw_pa_dout, dout);
77 if (cmd != NAND_CMD_NONE)
78 writeb(cmd, this->IO_ADDR_W);
80 local_irq_restore(flags);
84 * read device ready pin
86 int crisv32_device_ready(struct mtd_info *mtd)
88 reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
89 return ((din.data & (1 << BY_BIT)) >> BY_BIT);
93 * Main initialization routine
95 struct mtd_info *__init crisv32_nand_flash_probe(void)
97 void __iomem *read_cs;
98 void __iomem *write_cs;
100 reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core,
102 reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
103 struct nand_chip *this;
106 /* Allocate memory for MTD device structure and private data */
107 crisv32_mtd = kmalloc(sizeof(struct mtd_info) +
108 sizeof(struct nand_chip), GFP_KERNEL);
110 printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
111 "device structure.\n");
116 read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
117 write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
119 if (!read_cs || !write_cs) {
120 printk(KERN_ERR "CRISv32 NAND ioremap failed\n");
125 /* Get pointer to private data */
126 this = (struct nand_chip *) (&crisv32_mtd[1]);
128 pa_oe.oe |= 1 << CE_BIT;
129 pa_oe.oe |= 1 << ALE_BIT;
130 pa_oe.oe |= 1 << CLE_BIT;
131 pa_oe.oe &= ~(1 << BY_BIT);
132 REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
134 bif_cfg.gated_csp0 = regk_bif_core_rd;
135 bif_cfg.gated_csp1 = regk_bif_core_wr;
136 REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
138 /* Initialize structures */
139 memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
140 memset((char *) this, 0, sizeof(struct nand_chip));
142 /* Link the private data with the MTD structure */
143 crisv32_mtd->priv = this;
145 /* Set address of NAND IO lines */
146 this->IO_ADDR_R = read_cs;
147 this->IO_ADDR_W = write_cs;
148 this->cmd_ctrl = crisv32_hwcontrol;
149 this->dev_ready = crisv32_device_ready;
150 /* 20 us command delay time */
151 this->chip_delay = 20;
152 this->ecc.mode = NAND_ECC_SOFT;
154 /* Enable the following for a flash based bad block table */
155 /* this->options = NAND_USE_FLASH_BBT; */
157 /* Scan to find existance of the device */
158 if (nand_scan(crisv32_mtd, 1)) {
166 iounmap((void *)read_cs);
167 iounmap((void *)write_cs);