arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #ifdef CONFIG_IPIPE
  19 #include <linux/ipipe.h>
  20 #endif
  21 #ifdef CONFIG_KGDB
  22 #include <linux/kgdb.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29 #include <asm/bfin5xx_spi.h>
  30 #include <asm/bfin_sport.h>
  31 #include <asm/bfin_can.h>
  32
  33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  34
  35 #ifdef BF537_FAMILY
  36 # define BF537_GENERIC_ERROR_INT_DEMUX
  37 # define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
  38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
  39 # define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
  40 # define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
  41 # define UART_ERR_MASK  (0x6)   /* UART_IIR */
  42 # define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
  43 #else
  44 # undef BF537_GENERIC_ERROR_INT_DEMUX
  45 #endif
  46
  47 /*
  48  * NOTES:
  49  * - we have separated the physical Hardware interrupt from the
  50  * levels that the LINUX kernel sees (see the description in irq.h)
  51  * -
  52  */
  53
  54 #ifndef CONFIG_SMP
  55 /* Initialize this to an actual value to force it into the .data
  56  * section so that we know it is properly initialized at entry into
  57  * the kernel but before bss is initialized to zero (which is where
  58  * it would live otherwise).  The 0x1f magic represents the IRQs we
  59  * cannot actually mask out in hardware.
  60  */
  61 unsigned long bfin_irq_flags = 0x1f;
  62 EXPORT_SYMBOL(bfin_irq_flags);
  63 #endif
  64
  65 /* The number of spurious interrupts */
  66 atomic_t num_spurious;
  67
  68 #ifdef CONFIG_PM
  69 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  70 unsigned vr_wakeup;
  71 #endif
  72
  73 struct ivgx {
  74         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  75         unsigned int irqno;
  76         /* corresponding bit in the SIC_ISR register */
  77         unsigned int isrflag;
  78 } ivg_table[NR_PERI_INTS];
  79
  80 struct ivg_slice {
  81         /* position of first irq in ivg_table for given ivg */
  82         struct ivgx *ifirst;
  83         struct ivgx *istop;
  84 } ivg7_13[IVG13 - IVG7 + 1];
  85
  86
  87 /*
  88  * Search SIC_IAR and fill tables with the irqvalues
  89  * and their positions in the SIC_ISR register.
  90  */
  91 static void __init search_IAR(void)
  92 {
  93         unsigned ivg, irq_pos = 0;
  94         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  95                 int irqN;
  96
  97                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  98
  99                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
 100                         int irqn;
 101                         u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
 102 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
 103         defined(CONFIG_BF538) || defined(CONFIG_BF539)
 104                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
 105 #else
 106                                 (irqN >> 3)
 107 #endif
 108                                 );
 109
 110                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
 111                                 int iar_shift = (irqn & 7) * 4;
 112                                 if (ivg == (0xf & (iar >> iar_shift))) {
 113                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
 114                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 115                                         ivg7_13[ivg].istop++;
 116                                         irq_pos++;
 117                                 }
 118                         }
 119                 }
 120         }
 121 }
 122
 123 /*
 124  * This is for core internal IRQs
 125  */
 126
 127 static void bfin_ack_noop(struct irq_data *d)
 128 {
 129         /* Dummy function.  */
 130 }
 131
 132 static void bfin_core_mask_irq(struct irq_data *d)
 133 {
 134         bfin_irq_flags &= ~(1 << d->irq);
 135         if (!hard_irqs_disabled())
 136                 hard_local_irq_enable();
 137 }
 138
 139 static void bfin_core_unmask_irq(struct irq_data *d)
 140 {
 141         bfin_irq_flags |= 1 << d->irq;
 142         /*
 143          * If interrupts are enabled, IMASK must contain the same value
 144          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 145          * are currently disabled we need not do anything; one of the
 146          * callers will take care of setting IMASK to the proper value
 147          * when reenabling interrupts.
 148          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 149          * what we need.
 150          */
 151         if (!hard_irqs_disabled())
 152                 hard_local_irq_enable();
 153         return;
 154 }
 155
 156 static void bfin_internal_mask_irq(unsigned int irq)
 157 {
 158         unsigned long flags;
 159
 160 #ifdef CONFIG_BF53x
 161         flags = hard_local_irq_save();
 162         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 163                              ~(1 << SIC_SYSIRQ(irq)));
 164 #else
 165         unsigned mask_bank, mask_bit;
 166         flags = hard_local_irq_save();
 167         mask_bank = SIC_SYSIRQ(irq) / 32;
 168         mask_bit = SIC_SYSIRQ(irq) % 32;
 169         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 170                              ~(1 << mask_bit));
 171 #ifdef CONFIG_SMP
 172         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 173                              ~(1 << mask_bit));
 174 #endif
 175 #endif
 176         hard_local_irq_restore(flags);
 177 }
 178
 179 static void bfin_internal_mask_irq_chip(struct irq_data *d)
 180 {
 181         bfin_internal_mask_irq(d->irq);
 182 }
 183
 184 #ifdef CONFIG_SMP
 185 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
 186                 const struct cpumask *affinity)
 187 #else
 188 static void bfin_internal_unmask_irq(unsigned int irq)
 189 #endif
 190 {
 191         unsigned long flags;
 192
 193 #ifdef CONFIG_BF53x
 194         flags = hard_local_irq_save();
 195         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 196                              (1 << SIC_SYSIRQ(irq)));
 197 #else
 198         unsigned mask_bank, mask_bit;
 199         flags = hard_local_irq_save();
 200         mask_bank = SIC_SYSIRQ(irq) / 32;
 201         mask_bit = SIC_SYSIRQ(irq) % 32;
 202 #ifdef CONFIG_SMP
 203         if (cpumask_test_cpu(0, affinity))
 204 #endif
 205                 bfin_write_SIC_IMASK(mask_bank,
 206                         bfin_read_SIC_IMASK(mask_bank) |
 207                         (1 << mask_bit));
 208 #ifdef CONFIG_SMP
 209         if (cpumask_test_cpu(1, affinity))
 210                 bfin_write_SICB_IMASK(mask_bank,
 211                         bfin_read_SICB_IMASK(mask_bank) |
 212                         (1 << mask_bit));
 213 #endif
 214 #endif
 215         hard_local_irq_restore(flags);
 216 }
 217
 218 #ifdef CONFIG_SMP
 219 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 220 {
 221         bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
 222 }
 223
 224 static int bfin_internal_set_affinity(struct irq_data *d,
 225                                       const struct cpumask *mask, bool force)
 226 {
 227         bfin_internal_mask_irq(d->irq);
 228         bfin_internal_unmask_irq_affinity(d->irq, mask);
 229
 230         return 0;
 231 }
 232 #else
 233 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 234 {
 235         bfin_internal_unmask_irq(d->irq);
 236 }
 237 #endif
 238
 239 #ifdef CONFIG_PM
 240 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 241 {
 242         u32 bank, bit, wakeup = 0;
 243         unsigned long flags;
 244         bank = SIC_SYSIRQ(irq) / 32;
 245         bit = SIC_SYSIRQ(irq) % 32;
 246
 247         switch (irq) {
 248 #ifdef IRQ_RTC
 249         case IRQ_RTC:
 250         wakeup |= WAKE;
 251         break;
 252 #endif
 253 #ifdef IRQ_CAN0_RX
 254         case IRQ_CAN0_RX:
 255         wakeup |= CANWE;
 256         break;
 257 #endif
 258 #ifdef IRQ_CAN1_RX
 259         case IRQ_CAN1_RX:
 260         wakeup |= CANWE;
 261         break;
 262 #endif
 263 #ifdef IRQ_USB_INT0
 264         case IRQ_USB_INT0:
 265         wakeup |= USBWE;
 266         break;
 267 #endif
 268 #ifdef CONFIG_BF54x
 269         case IRQ_CNT:
 270         wakeup |= ROTWE;
 271         break;
 272 #endif
 273         default:
 274         break;
 275         }
 276
 277         flags = hard_local_irq_save();
 278
 279         if (state) {
 280                 bfin_sic_iwr[bank] |= (1 << bit);
 281                 vr_wakeup  |= wakeup;
 282
 283         } else {
 284                 bfin_sic_iwr[bank] &= ~(1 << bit);
 285                 vr_wakeup  &= ~wakeup;
 286         }
 287
 288         hard_local_irq_restore(flags);
 289
 290         return 0;
 291 }
 292
 293 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 294 {
 295         return bfin_internal_set_wake(d->irq, state);
 296 }
 297 #endif
 298
 299 static struct irq_chip bfin_core_irqchip = {
 300         .name = "CORE",
 301         .irq_ack = bfin_ack_noop,
 302         .irq_mask = bfin_core_mask_irq,
 303         .irq_unmask = bfin_core_unmask_irq,
 304 };
 305
 306 static struct irq_chip bfin_internal_irqchip = {
 307         .name = "INTN",
 308         .irq_ack = bfin_ack_noop,
 309         .irq_mask = bfin_internal_mask_irq_chip,
 310         .irq_unmask = bfin_internal_unmask_irq_chip,
 311         .irq_mask_ack = bfin_internal_mask_irq_chip,
 312         .irq_disable = bfin_internal_mask_irq_chip,
 313         .irq_enable = bfin_internal_unmask_irq_chip,
 314 #ifdef CONFIG_SMP
 315         .irq_set_affinity = bfin_internal_set_affinity,
 316 #endif
 317 #ifdef CONFIG_PM
 318         .irq_set_wake = bfin_internal_set_wake_chip,
 319 #endif
 320 };
 321
 322 static void bfin_handle_irq(unsigned irq)
 323 {
 324 #ifdef CONFIG_IPIPE
 325         struct pt_regs regs;    /* Contents not used. */
 326         ipipe_trace_irq_entry(irq);
 327         __ipipe_handle_irq(irq, &regs);
 328         ipipe_trace_irq_exit(irq);
 329 #else /* !CONFIG_IPIPE */
 330         generic_handle_irq(irq);
 331 #endif  /* !CONFIG_IPIPE */
 332 }
 333
 334 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 335 static int error_int_mask;
 336
 337 static void bfin_generic_error_mask_irq(unsigned int irq)
 338 {
 339         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
 340         if (!error_int_mask)
 341                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 342 }
 343
 344 static void bfin_generic_error_unmask_irq(unsigned int irq)
 345 {
 346         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 347         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
 348 }
 349
 350 static struct irq_chip bfin_generic_error_irqchip = {
 351         .name = "ERROR",
 352         .irq_ack = bfin_ack_noop,
 353         .mask_ack = bfin_generic_error_mask_irq,
 354         .mask = bfin_generic_error_mask_irq,
 355         .unmask = bfin_generic_error_unmask_irq,
 356 };
 357
 358 static void bfin_demux_error_irq(unsigned int int_err_irq,
 359                                  struct irq_desc *inta_desc)
 360 {
 361         int irq = 0;
 362
 363 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 364         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 365                 irq = IRQ_MAC_ERROR;
 366         else
 367 #endif
 368         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 369                 irq = IRQ_SPORT0_ERROR;
 370         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 371                 irq = IRQ_SPORT1_ERROR;
 372         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 373                 irq = IRQ_PPI_ERROR;
 374         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 375                 irq = IRQ_CAN_ERROR;
 376         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 377                 irq = IRQ_SPI_ERROR;
 378         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 379                 irq = IRQ_UART0_ERROR;
 380         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 381                 irq = IRQ_UART1_ERROR;
 382
 383         if (irq) {
 384                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
 385                         bfin_handle_irq(irq);
 386                 else {
 387
 388                         switch (irq) {
 389                         case IRQ_PPI_ERROR:
 390                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 391                                 break;
 392 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 393                         case IRQ_MAC_ERROR:
 394                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 395                                 break;
 396 #endif
 397                         case IRQ_SPORT0_ERROR:
 398                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 399                                 break;
 400
 401                         case IRQ_SPORT1_ERROR:
 402                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 403                                 break;
 404
 405                         case IRQ_CAN_ERROR:
 406                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 407                                 break;
 408
 409                         case IRQ_SPI_ERROR:
 410                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 411                                 break;
 412
 413                         default:
 414                                 break;
 415                         }
 416
 417                         pr_debug("IRQ %d:"
 418                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 419                                  irq);
 420                 }
 421         } else
 422                 printk(KERN_ERR
 423                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 424                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 425                        __func__, __FILE__, __LINE__);
 426
 427 }
 428 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 429
 430 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 431 static int mac_stat_int_mask;
 432
 433 static void bfin_mac_status_ack_irq(unsigned int irq)
 434 {
 435         switch (irq) {
 436         case IRQ_MAC_MMCINT:
 437                 bfin_write_EMAC_MMC_TIRQS(
 438                         bfin_read_EMAC_MMC_TIRQE() &
 439                         bfin_read_EMAC_MMC_TIRQS());
 440                 bfin_write_EMAC_MMC_RIRQS(
 441                         bfin_read_EMAC_MMC_RIRQE() &
 442                         bfin_read_EMAC_MMC_RIRQS());
 443                 break;
 444         case IRQ_MAC_RXFSINT:
 445                 bfin_write_EMAC_RX_STKY(
 446                         bfin_read_EMAC_RX_IRQE() &
 447                         bfin_read_EMAC_RX_STKY());
 448                 break;
 449         case IRQ_MAC_TXFSINT:
 450                 bfin_write_EMAC_TX_STKY(
 451                         bfin_read_EMAC_TX_IRQE() &
 452                         bfin_read_EMAC_TX_STKY());
 453                 break;
 454         case IRQ_MAC_WAKEDET:
 455                  bfin_write_EMAC_WKUP_CTL(
 456                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 457                 break;
 458         default:
 459                 /* These bits are W1C */
 460                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 461                 break;
 462         }
 463 }
 464
 465 static void bfin_mac_status_mask_irq(unsigned int irq)
 466 {
 467         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 468 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 469         switch (irq) {
 470         case IRQ_MAC_PHYINT:
 471                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 472                 break;
 473         default:
 474                 break;
 475         }
 476 #else
 477         if (!mac_stat_int_mask)
 478                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 479 #endif
 480         bfin_mac_status_ack_irq(irq);
 481 }
 482
 483 static void bfin_mac_status_unmask_irq(unsigned int irq)
 484 {
 485 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 486         switch (irq) {
 487         case IRQ_MAC_PHYINT:
 488                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 489                 break;
 490         default:
 491                 break;
 492         }
 493 #else
 494         if (!mac_stat_int_mask)
 495                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 496 #endif
 497         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 498 }
 499
 500 #ifdef CONFIG_PM
 501 int bfin_mac_status_set_wake(unsigned int irq, unsigned int state)
 502 {
 503 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 504         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 505 #else
 506         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 507 #endif
 508 }
 509 #endif
 510
 511 static struct irq_chip bfin_mac_status_irqchip = {
 512         .name = "MACST",
 513         .irq_ack = bfin_ack_noop,
 514         .mask_ack = bfin_mac_status_mask_irq,
 515         .mask = bfin_mac_status_mask_irq,
 516         .unmask = bfin_mac_status_unmask_irq,
 517 #ifdef CONFIG_PM
 518         .set_wake = bfin_mac_status_set_wake,
 519 #endif
 520 };
 521
 522 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 523                                  struct irq_desc *inta_desc)
 524 {
 525         int i, irq = 0;
 526         u32 status = bfin_read_EMAC_SYSTAT();
 527
 528         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 529                 if (status & (1L << i)) {
 530                         irq = IRQ_MAC_PHYINT + i;
 531                         break;
 532                 }
 533
 534         if (irq) {
 535                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 536                         bfin_handle_irq(irq);
 537                 } else {
 538                         bfin_mac_status_ack_irq(irq);
 539                         pr_debug("IRQ %d:"
 540                                  " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 541                                  irq);
 542                 }
 543         } else
 544                 printk(KERN_ERR
 545                        "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 546                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
 547                        "(EMAC_SYSTAT=0x%X)\n",
 548                        __func__, __FILE__, __LINE__, status);
 549 }
 550 #endif
 551
 552 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 553 {
 554 #ifdef CONFIG_IPIPE
 555         _set_irq_handler(irq, handle_level_irq);
 556 #else
 557         __set_irq_handler_unlocked(irq, handle);
 558 #endif
 559 }
 560
 561 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 562 extern void bfin_gpio_irq_prepare(unsigned gpio);
 563
 564 #if !defined(CONFIG_BF54x)
 565
 566 static void bfin_gpio_ack_irq(unsigned int irq)
 567 {
 568         /* AFAIK ack_irq in case mask_ack is provided
 569          * get's only called for edge sense irqs
 570          */
 571         set_gpio_data(irq_to_gpio(irq), 0);
 572 }
 573
 574 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 575 {
 576         struct irq_desc *desc = irq_to_desc(irq);
 577         u32 gpionr = irq_to_gpio(irq);
 578
 579         if (desc->handle_irq == handle_edge_irq)
 580                 set_gpio_data(gpionr, 0);
 581
 582         set_gpio_maska(gpionr, 0);
 583 }
 584
 585 static void bfin_gpio_mask_irq(unsigned int irq)
 586 {
 587         set_gpio_maska(irq_to_gpio(irq), 0);
 588 }
 589
 590 static void bfin_gpio_unmask_irq(unsigned int irq)
 591 {
 592         set_gpio_maska(irq_to_gpio(irq), 1);
 593 }
 594
 595 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 596 {
 597         u32 gpionr = irq_to_gpio(irq);
 598
 599         if (__test_and_set_bit(gpionr, gpio_enabled))
 600                 bfin_gpio_irq_prepare(gpionr);
 601
 602         bfin_gpio_unmask_irq(irq);
 603
 604         return 0;
 605 }
 606
 607 static void bfin_gpio_irq_shutdown(unsigned int irq)
 608 {
 609         u32 gpionr = irq_to_gpio(irq);
 610
 611         bfin_gpio_mask_irq(irq);
 612         __clear_bit(gpionr, gpio_enabled);
 613         bfin_gpio_irq_free(gpionr);
 614 }
 615
 616 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 617 {
 618         int ret;
 619         char buf[16];
 620         u32 gpionr = irq_to_gpio(irq);
 621
 622         if (type == IRQ_TYPE_PROBE) {
 623                 /* only probe unenabled GPIO interrupt lines */
 624                 if (test_bit(gpionr, gpio_enabled))
 625                         return 0;
 626                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 627         }
 628
 629         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 630                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 631
 632                 snprintf(buf, 16, "gpio-irq%d", irq);
 633                 ret = bfin_gpio_irq_request(gpionr, buf);
 634                 if (ret)
 635                         return ret;
 636
 637                 if (__test_and_set_bit(gpionr, gpio_enabled))
 638                         bfin_gpio_irq_prepare(gpionr);
 639
 640         } else {
 641                 __clear_bit(gpionr, gpio_enabled);
 642                 return 0;
 643         }
 644
 645         set_gpio_inen(gpionr, 0);
 646         set_gpio_dir(gpionr, 0);
 647
 648         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 649             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 650                 set_gpio_both(gpionr, 1);
 651         else
 652                 set_gpio_both(gpionr, 0);
 653
 654         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 655                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 656         else
 657                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 658
 659         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 660                 set_gpio_edge(gpionr, 1);
 661                 set_gpio_inen(gpionr, 1);
 662                 set_gpio_data(gpionr, 0);
 663
 664         } else {
 665                 set_gpio_edge(gpionr, 0);
 666                 set_gpio_inen(gpionr, 1);
 667         }
 668
 669         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 670                 bfin_set_irq_handler(irq, handle_edge_irq);
 671         else
 672                 bfin_set_irq_handler(irq, handle_level_irq);
 673
 674         return 0;
 675 }
 676
 677 #ifdef CONFIG_PM
 678 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 679 {
 680         return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state);
 681 }
 682 #endif
 683
 684 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 685                                 struct irq_desc *desc)
 686 {
 687         unsigned int i, gpio, mask, irq, search = 0;
 688
 689         switch (inta_irq) {
 690 #if defined(CONFIG_BF53x)
 691         case IRQ_PROG_INTA:
 692                 irq = IRQ_PF0;
 693                 search = 1;
 694                 break;
 695 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 696         case IRQ_MAC_RX:
 697                 irq = IRQ_PH0;
 698                 break;
 699 # endif
 700 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 701         case IRQ_PORTF_INTA:
 702                 irq = IRQ_PF0;
 703                 break;
 704 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 705         case IRQ_PORTF_INTA:
 706                 irq = IRQ_PF0;
 707                 break;
 708         case IRQ_PORTG_INTA:
 709                 irq = IRQ_PG0;
 710                 break;
 711         case IRQ_PORTH_INTA:
 712                 irq = IRQ_PH0;
 713                 break;
 714 #elif defined(CONFIG_BF561)
 715         case IRQ_PROG0_INTA:
 716                 irq = IRQ_PF0;
 717                 break;
 718         case IRQ_PROG1_INTA:
 719                 irq = IRQ_PF16;
 720                 break;
 721         case IRQ_PROG2_INTA:
 722                 irq = IRQ_PF32;
 723                 break;
 724 #endif
 725         default:
 726                 BUG();
 727                 return;
 728         }
 729
 730         if (search) {
 731                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 732                         irq += i;
 733
 734                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 735
 736                         while (mask) {
 737                                 if (mask & 1)
 738                                         bfin_handle_irq(irq);
 739                                 irq++;
 740                                 mask >>= 1;
 741                         }
 742                 }
 743         } else {
 744                         gpio = irq_to_gpio(irq);
 745                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 746
 747                         do {
 748                                 if (mask & 1)
 749                                         bfin_handle_irq(irq);
 750                                 irq++;
 751                                 mask >>= 1;
 752                         } while (mask);
 753         }
 754
 755 }
 756
 757 #else                           /* CONFIG_BF54x */
 758
 759 #define NR_PINT_SYS_IRQS        4
 760 #define NR_PINT_BITS            32
 761 #define NR_PINTS                160
 762 #define IRQ_NOT_AVAIL           0xFF
 763
 764 #define PINT_2_BANK(x)          ((x) >> 5)
 765 #define PINT_2_BIT(x)           ((x) & 0x1F)
 766 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 767
 768 static unsigned char irq2pint_lut[NR_PINTS];
 769 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 770
 771 struct pin_int_t {
 772         unsigned int mask_set;
 773         unsigned int mask_clear;
 774         unsigned int request;
 775         unsigned int assign;
 776         unsigned int edge_set;
 777         unsigned int edge_clear;
 778         unsigned int invert_set;
 779         unsigned int invert_clear;
 780         unsigned int pinstate;
 781         unsigned int latch;
 782 };
 783
 784 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 785         (struct pin_int_t *)PINT0_MASK_SET,
 786         (struct pin_int_t *)PINT1_MASK_SET,
 787         (struct pin_int_t *)PINT2_MASK_SET,
 788         (struct pin_int_t *)PINT3_MASK_SET,
 789 };
 790
 791 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 792 {
 793         unsigned int irq_base;
 794
 795         if (bank < 2) {         /*PA-PB */
 796                 irq_base = IRQ_PA0 + bmap * 16;
 797         } else {                /*PC-PJ */
 798                 irq_base = IRQ_PC0 + bmap * 16;
 799         }
 800
 801         return irq_base;
 802 }
 803
 804         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 805 void init_pint_lut(void)
 806 {
 807         u16 bank, bit, irq_base, bit_pos;
 808         u32 pint_assign;
 809         u8 bmap;
 810
 811         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 812
 813         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 814
 815                 pint_assign = pint[bank]->assign;
 816
 817                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 818
 819                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 820
 821                         irq_base = get_irq_base(bank, bmap);
 822
 823                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 824                         bit_pos = bit + bank * NR_PINT_BITS;
 825
 826                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 827                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 828                 }
 829         }
 830 }
 831
 832 static void bfin_gpio_ack_irq(unsigned int irq)
 833 {
 834         struct irq_desc *desc = irq_to_desc(irq);
 835         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 836         u32 pintbit = PINT_BIT(pint_val);
 837         u32 bank = PINT_2_BANK(pint_val);
 838
 839         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 840                 if (pint[bank]->invert_set & pintbit)
 841                         pint[bank]->invert_clear = pintbit;
 842                 else
 843                         pint[bank]->invert_set = pintbit;
 844         }
 845         pint[bank]->request = pintbit;
 846
 847 }
 848
 849 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 850 {
 851         struct irq_desc *desc = irq_to_desc(irq);
 852         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 853         u32 pintbit = PINT_BIT(pint_val);
 854         u32 bank = PINT_2_BANK(pint_val);
 855
 856         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 857                 if (pint[bank]->invert_set & pintbit)
 858                         pint[bank]->invert_clear = pintbit;
 859                 else
 860                         pint[bank]->invert_set = pintbit;
 861         }
 862
 863         pint[bank]->request = pintbit;
 864         pint[bank]->mask_clear = pintbit;
 865 }
 866
 867 static void bfin_gpio_mask_irq(unsigned int irq)
 868 {
 869         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 870
 871         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 872 }
 873
 874 static void bfin_gpio_unmask_irq(unsigned int irq)
 875 {
 876         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 877         u32 pintbit = PINT_BIT(pint_val);
 878         u32 bank = PINT_2_BANK(pint_val);
 879
 880         pint[bank]->mask_set = pintbit;
 881 }
 882
 883 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 884 {
 885         u32 gpionr = irq_to_gpio(irq);
 886         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 887
 888         if (pint_val == IRQ_NOT_AVAIL) {
 889                 printk(KERN_ERR
 890                 "GPIO IRQ %d :Not in PINT Assign table "
 891                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 892                 return -ENODEV;
 893         }
 894
 895         if (__test_and_set_bit(gpionr, gpio_enabled))
 896                 bfin_gpio_irq_prepare(gpionr);
 897
 898         bfin_gpio_unmask_irq(irq);
 899
 900         return 0;
 901 }
 902
 903 static void bfin_gpio_irq_shutdown(unsigned int irq)
 904 {
 905         u32 gpionr = irq_to_gpio(irq);
 906
 907         bfin_gpio_mask_irq(irq);
 908         __clear_bit(gpionr, gpio_enabled);
 909         bfin_gpio_irq_free(gpionr);
 910 }
 911
 912 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 913 {
 914         int ret;
 915         char buf[16];
 916         u32 gpionr = irq_to_gpio(irq);
 917         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 918         u32 pintbit = PINT_BIT(pint_val);
 919         u32 bank = PINT_2_BANK(pint_val);
 920
 921         if (pint_val == IRQ_NOT_AVAIL)
 922                 return -ENODEV;
 923
 924         if (type == IRQ_TYPE_PROBE) {
 925                 /* only probe unenabled GPIO interrupt lines */
 926                 if (test_bit(gpionr, gpio_enabled))
 927                         return 0;
 928                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 929         }
 930
 931         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 932                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 933
 934                 snprintf(buf, 16, "gpio-irq%d", irq);
 935                 ret = bfin_gpio_irq_request(gpionr, buf);
 936                 if (ret)
 937                         return ret;
 938
 939                 if (__test_and_set_bit(gpionr, gpio_enabled))
 940                         bfin_gpio_irq_prepare(gpionr);
 941
 942         } else {
 943                 __clear_bit(gpionr, gpio_enabled);
 944                 return 0;
 945         }
 946
 947         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 948                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 949         else
 950                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 951
 952         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 953             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 954                 if (gpio_get_value(gpionr))
 955                         pint[bank]->invert_set = pintbit;
 956                 else
 957                         pint[bank]->invert_clear = pintbit;
 958         }
 959
 960         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 961                 pint[bank]->edge_set = pintbit;
 962                 bfin_set_irq_handler(irq, handle_edge_irq);
 963         } else {
 964                 pint[bank]->edge_clear = pintbit;
 965                 bfin_set_irq_handler(irq, handle_level_irq);
 966         }
 967
 968         return 0;
 969 }
 970
 971 #ifdef CONFIG_PM
 972 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 973 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 974
 975 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 976 {
 977         u32 pint_irq;
 978         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 979         u32 bank = PINT_2_BANK(pint_val);
 980         u32 pintbit = PINT_BIT(pint_val);
 981
 982         switch (bank) {
 983         case 0:
 984                 pint_irq = IRQ_PINT0;
 985                 break;
 986         case 2:
 987                 pint_irq = IRQ_PINT2;
 988                 break;
 989         case 3:
 990                 pint_irq = IRQ_PINT3;
 991                 break;
 992         case 1:
 993                 pint_irq = IRQ_PINT1;
 994                 break;
 995         default:
 996                 return -EINVAL;
 997         }
 998
 999         bfin_internal_set_wake(pint_irq, state);
1000
1001         if (state)
1002                 pint_wakeup_masks[bank] |= pintbit;
1003         else
1004                 pint_wakeup_masks[bank] &= ~pintbit;
1005
1006         return 0;
1007 }
1008
1009 u32 bfin_pm_setup(void)
1010 {
1011         u32 val, i;
1012
1013         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1014                 val = pint[i]->mask_clear;
1015                 pint_saved_masks[i] = val;
1016                 if (val ^ pint_wakeup_masks[i]) {
1017                         pint[i]->mask_clear = val;
1018                         pint[i]->mask_set = pint_wakeup_masks[i];
1019                 }
1020         }
1021
1022         return 0;
1023 }
1024
1025 void bfin_pm_restore(void)
1026 {
1027         u32 i, val;
1028
1029         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1030                 val = pint_saved_masks[i];
1031                 if (val ^ pint_wakeup_masks[i]) {
1032                         pint[i]->mask_clear = pint[i]->mask_clear;
1033                         pint[i]->mask_set = val;
1034                 }
1035         }
1036 }
1037 #endif
1038
1039 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1040                                 struct irq_desc *desc)
1041 {
1042         u32 bank, pint_val;
1043         u32 request, irq;
1044
1045         switch (inta_irq) {
1046         case IRQ_PINT0:
1047                 bank = 0;
1048                 break;
1049         case IRQ_PINT2:
1050                 bank = 2;
1051                 break;
1052         case IRQ_PINT3:
1053                 bank = 3;
1054                 break;
1055         case IRQ_PINT1:
1056                 bank = 1;
1057                 break;
1058         default:
1059                 return;
1060         }
1061
1062         pint_val = bank * NR_PINT_BITS;
1063
1064         request = pint[bank]->request;
1065
1066         while (request) {
1067                 if (request & 1) {
1068                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1069                         bfin_handle_irq(irq);
1070                 }
1071                 pint_val++;
1072                 request >>= 1;
1073         }
1074
1075 }
1076 #endif
1077
1078 static struct irq_chip bfin_gpio_irqchip = {
1079         .name = "GPIO",
1080         .ack = bfin_gpio_ack_irq,
1081         .mask = bfin_gpio_mask_irq,
1082         .mask_ack = bfin_gpio_mask_ack_irq,
1083         .unmask = bfin_gpio_unmask_irq,
1084         .disable = bfin_gpio_mask_irq,
1085         .enable = bfin_gpio_unmask_irq,
1086         .set_type = bfin_gpio_irq_type,
1087         .startup = bfin_gpio_irq_startup,
1088         .shutdown = bfin_gpio_irq_shutdown,
1089 #ifdef CONFIG_PM
1090         .set_wake = bfin_gpio_set_wake,
1091 #endif
1092 };
1093
1094 void __cpuinit init_exception_vectors(void)
1095 {
1096         /* cannot program in software:
1097          * evt0 - emulation (jtag)
1098          * evt1 - reset
1099          */
1100         bfin_write_EVT2(evt_nmi);
1101         bfin_write_EVT3(trap);
1102         bfin_write_EVT5(evt_ivhw);
1103         bfin_write_EVT6(evt_timer);
1104         bfin_write_EVT7(evt_evt7);
1105         bfin_write_EVT8(evt_evt8);
1106         bfin_write_EVT9(evt_evt9);
1107         bfin_write_EVT10(evt_evt10);
1108         bfin_write_EVT11(evt_evt11);
1109         bfin_write_EVT12(evt_evt12);
1110         bfin_write_EVT13(evt_evt13);
1111         bfin_write_EVT14(evt_evt14);
1112         bfin_write_EVT15(evt_system_call);
1113         CSYNC();
1114 }
1115
1116 /*
1117  * This function should be called during kernel startup to initialize
1118  * the BFin IRQ handling routines.
1119  */
1120
1121 int __init init_arch_irq(void)
1122 {
1123         int irq;
1124         unsigned long ilat = 0;
1125         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1126 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1127         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1128         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1129         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1130 # ifdef CONFIG_BF54x
1131         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1132 # endif
1133 # ifdef CONFIG_SMP
1134         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1135         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1136 # endif
1137 #else
1138         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1139 #endif
1140
1141         local_irq_disable();
1142
1143 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1144         /* Clear EMAC Interrupt Status bits so we can demux it later */
1145         bfin_write_EMAC_SYSTAT(-1);
1146 #endif
1147
1148 #ifdef CONFIG_BF54x
1149 # ifdef CONFIG_PINTx_REASSIGN
1150         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1151         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1152         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1153         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1154 # endif
1155         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1156         init_pint_lut();
1157 #endif
1158
1159         for (irq = 0; irq <= SYS_IRQS; irq++) {
1160                 if (irq <= IRQ_CORETMR)
1161                         set_irq_chip(irq, &bfin_core_irqchip);
1162                 else
1163                         set_irq_chip(irq, &bfin_internal_irqchip);
1164
1165                 switch (irq) {
1166 #if defined(CONFIG_BF53x)
1167                 case IRQ_PROG_INTA:
1168 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1169                 case IRQ_MAC_RX:
1170 # endif
1171 #elif defined(CONFIG_BF54x)
1172                 case IRQ_PINT0:
1173                 case IRQ_PINT1:
1174                 case IRQ_PINT2:
1175                 case IRQ_PINT3:
1176 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1177                 case IRQ_PORTF_INTA:
1178                 case IRQ_PORTG_INTA:
1179                 case IRQ_PORTH_INTA:
1180 #elif defined(CONFIG_BF561)
1181                 case IRQ_PROG0_INTA:
1182                 case IRQ_PROG1_INTA:
1183                 case IRQ_PROG2_INTA:
1184 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1185                 case IRQ_PORTF_INTA:
1186 #endif
1187                         set_irq_chained_handler(irq,
1188                                                 bfin_demux_gpio_irq);
1189                         break;
1190 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1191                 case IRQ_GENERIC_ERROR:
1192                         set_irq_chained_handler(irq, bfin_demux_error_irq);
1193                         break;
1194 #endif
1195 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1196                 case IRQ_MAC_ERROR:
1197                         set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1198                         break;
1199 #endif
1200 #ifdef CONFIG_SMP
1201                 case IRQ_SUPPLE_0:
1202                 case IRQ_SUPPLE_1:
1203                         set_irq_handler(irq, handle_percpu_irq);
1204                         break;
1205 #endif
1206
1207 #ifdef CONFIG_TICKSOURCE_CORETMR
1208                 case IRQ_CORETMR:
1209 # ifdef CONFIG_SMP
1210                         set_irq_handler(irq, handle_percpu_irq);
1211                         break;
1212 # else
1213                         set_irq_handler(irq, handle_simple_irq);
1214                         break;
1215 # endif
1216 #endif
1217
1218 #ifdef CONFIG_TICKSOURCE_GPTMR0
1219                 case IRQ_TIMER0:
1220                         set_irq_handler(irq, handle_simple_irq);
1221                         break;
1222 #endif
1223
1224 #ifdef CONFIG_IPIPE
1225                 default:
1226                         set_irq_handler(irq, handle_level_irq);
1227                         break;
1228 #else /* !CONFIG_IPIPE */
1229                 default:
1230                         set_irq_handler(irq, handle_simple_irq);
1231                         break;
1232 #endif /* !CONFIG_IPIPE */
1233                 }
1234         }
1235
1236 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1237         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1238                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1239                                          handle_level_irq);
1240 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1241         set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1242 #endif
1243 #endif
1244
1245 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1246         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1247                 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1248                                          handle_level_irq);
1249 #endif
1250         /* if configured as edge, then will be changed to do_edge_IRQ */
1251         for (irq = GPIO_IRQ_BASE;
1252                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1253                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1254                                          handle_level_irq);
1255
1256         bfin_write_IMASK(0);
1257         CSYNC();
1258         ilat = bfin_read_ILAT();
1259         CSYNC();
1260         bfin_write_ILAT(ilat);
1261         CSYNC();
1262
1263         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1264         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1265          * local_irq_enable()
1266          */
1267         program_IAR();
1268         /* Therefore it's better to setup IARs before interrupts enabled */
1269         search_IAR();
1270
1271         /* Enable interrupts IVG7-15 */
1272         bfin_irq_flags |= IMASK_IVG15 |
1273             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1274             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1275
1276         /* This implicitly covers ANOMALY_05000171
1277          * Boot-ROM code modifies SICA_IWRx wakeup registers
1278          */
1279 #ifdef SIC_IWR0
1280         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1281 # ifdef SIC_IWR1
1282         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1283          * will screw up the bootrom as it relies on MDMA0/1 waking it
1284          * up from IDLE instructions.  See this report for more info:
1285          * http://blackfin.uclinux.org/gf/tracker/4323
1286          */
1287         if (ANOMALY_05000435)
1288                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1289         else
1290                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1291 # endif
1292 # ifdef SIC_IWR2
1293         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1294 # endif
1295 #else
1296         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1297 #endif
1298
1299         return 0;
1300 }
1301
1302 #ifdef CONFIG_DO_IRQ_L1
1303 __attribute__((l1_text))
1304 #endif
1305 void do_irq(int vec, struct pt_regs *fp)
1306 {
1307         if (vec == EVT_IVTMR_P) {
1308                 vec = IRQ_CORETMR;
1309         } else {
1310                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1311                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1312 #if defined(SIC_ISR0)
1313                 unsigned long sic_status[3];
1314
1315                 if (smp_processor_id()) {
1316 # ifdef SICB_ISR0
1317                         /* This will be optimized out in UP mode. */
1318                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1319                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1320 # endif
1321                 } else {
1322                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1323                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1324                 }
1325 # ifdef SIC_ISR2
1326                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1327 # endif
1328                 for (;; ivg++) {
1329                         if (ivg >= ivg_stop) {
1330                                 atomic_inc(&num_spurious);
1331                                 return;
1332                         }
1333                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1334                                 break;
1335                 }
1336 #else
1337                 unsigned long sic_status;
1338
1339                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1340
1341                 for (;; ivg++) {
1342                         if (ivg >= ivg_stop) {
1343                                 atomic_inc(&num_spurious);
1344                                 return;
1345                         } else if (sic_status & ivg->isrflag)
1346                                 break;
1347                 }
1348 #endif
1349                 vec = ivg->irqno;
1350         }
1351         asm_do_IRQ(vec, fp);
1352 }
1353
1354 #ifdef CONFIG_IPIPE
1355
1356 int __ipipe_get_irq_priority(unsigned irq)
1357 {
1358         int ient, prio;
1359
1360         if (irq <= IRQ_CORETMR)
1361                 return irq;
1362
1363         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1364                 struct ivgx *ivg = ivg_table + ient;
1365                 if (ivg->irqno == irq) {
1366                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1367                                 if (ivg7_13[prio].ifirst <= ivg &&
1368                                     ivg7_13[prio].istop > ivg)
1369                                         return IVG7 + prio;
1370                         }
1371                 }
1372         }
1373
1374         return IVG15;
1375 }
1376
1377 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1378 #ifdef CONFIG_DO_IRQ_L1
1379 __attribute__((l1_text))
1380 #endif
1381 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1382 {
1383         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1384         struct ipipe_domain *this_domain = __ipipe_current_domain;
1385         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1386         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1387         int irq, s;
1388
1389         if (likely(vec == EVT_IVTMR_P))
1390                 irq = IRQ_CORETMR;
1391         else {
1392 #if defined(SIC_ISR0)
1393                 unsigned long sic_status[3];
1394
1395                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1396                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1397 # ifdef SIC_ISR2
1398                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1399 # endif
1400                 for (;; ivg++) {
1401                         if (ivg >= ivg_stop) {
1402                                 atomic_inc(&num_spurious);
1403                                 return 0;
1404                         }
1405                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1406                                 break;
1407                 }
1408 #else
1409                 unsigned long sic_status;
1410
1411                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1412
1413                 for (;; ivg++) {
1414                         if (ivg >= ivg_stop) {
1415                                 atomic_inc(&num_spurious);
1416                                 return 0;
1417                         } else if (sic_status & ivg->isrflag)
1418                                 break;
1419                 }
1420 #endif
1421                 irq = ivg->irqno;
1422         }
1423
1424         if (irq == IRQ_SYSTMR) {
1425 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1426                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1427 #endif
1428                 /* This is basically what we need from the register frame. */
1429                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1430                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1431                 if (this_domain != ipipe_root_domain)
1432                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1433                 else
1434                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1435         }
1436
1437         if (this_domain == ipipe_root_domain) {
1438                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1439                 barrier();
1440         }
1441
1442         ipipe_trace_irq_entry(irq);
1443         __ipipe_handle_irq(irq, regs);
1444         ipipe_trace_irq_exit(irq);
1445
1446         if (this_domain == ipipe_root_domain) {
1447                 set_thread_flag(TIF_IRQ_SYNC);
1448                 if (!s) {
1449                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1450                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1451                 }
1452         }
1453
1454         return 0;
1455 }
1456
1457 #endif /* CONFIG_IPIPE */