arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #ifdef CONFIG_IPIPE
  19 #include <linux/ipipe.h>
  20 #endif
  21 #ifdef CONFIG_KGDB
  22 #include <linux/kgdb.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29 #include <asm/bfin5xx_spi.h>
  30 #include <asm/bfin_sport.h>
  31 #include <asm/bfin_can.h>
  32
  33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  34
  35 #ifdef BF537_FAMILY
  36 # define BF537_GENERIC_ERROR_INT_DEMUX
  37 # define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
  38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
  39 # define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
  40 # define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
  41 # define UART_ERR_MASK  (0x6)   /* UART_IIR */
  42 # define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
  43 #else
  44 # undef BF537_GENERIC_ERROR_INT_DEMUX
  45 #endif
  46
  47 /*
  48  * NOTES:
  49  * - we have separated the physical Hardware interrupt from the
  50  * levels that the LINUX kernel sees (see the description in irq.h)
  51  * -
  52  */
  53
  54 #ifndef CONFIG_SMP
  55 /* Initialize this to an actual value to force it into the .data
  56  * section so that we know it is properly initialized at entry into
  57  * the kernel but before bss is initialized to zero (which is where
  58  * it would live otherwise).  The 0x1f magic represents the IRQs we
  59  * cannot actually mask out in hardware.
  60  */
  61 unsigned long bfin_irq_flags = 0x1f;
  62 EXPORT_SYMBOL(bfin_irq_flags);
  63 #endif
  64
  65 /* The number of spurious interrupts */
  66 atomic_t num_spurious;
  67
  68 #ifdef CONFIG_PM
  69 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  70 unsigned vr_wakeup;
  71 #endif
  72
  73 struct ivgx {
  74         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  75         unsigned int irqno;
  76         /* corresponding bit in the SIC_ISR register */
  77         unsigned int isrflag;
  78 } ivg_table[NR_PERI_INTS];
  79
  80 struct ivg_slice {
  81         /* position of first irq in ivg_table for given ivg */
  82         struct ivgx *ifirst;
  83         struct ivgx *istop;
  84 } ivg7_13[IVG13 - IVG7 + 1];
  85
  86
  87 /*
  88  * Search SIC_IAR and fill tables with the irqvalues
  89  * and their positions in the SIC_ISR register.
  90  */
  91 static void __init search_IAR(void)
  92 {
  93         unsigned ivg, irq_pos = 0;
  94         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  95                 int irqN;
  96
  97                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  98
  99                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
 100                         int irqn;
 101                         u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
 102 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
 103         defined(CONFIG_BF538) || defined(CONFIG_BF539)
 104                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
 105 #else
 106                                 (irqN >> 3)
 107 #endif
 108                                 );
 109
 110                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
 111                                 int iar_shift = (irqn & 7) * 4;
 112                                 if (ivg == (0xf & (iar >> iar_shift))) {
 113                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
 114                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 115                                         ivg7_13[ivg].istop++;
 116                                         irq_pos++;
 117                                 }
 118                         }
 119                 }
 120         }
 121 }
 122
 123 /*
 124  * This is for core internal IRQs
 125  */
 126
 127 static void bfin_ack_noop(struct irq_data *d)
 128 {
 129         /* Dummy function.  */
 130 }
 131
 132 static void bfin_core_mask_irq(struct irq_data *d)
 133 {
 134         bfin_irq_flags &= ~(1 << d->irq);
 135         if (!hard_irqs_disabled())
 136                 hard_local_irq_enable();
 137 }
 138
 139 static void bfin_core_unmask_irq(struct irq_data *d)
 140 {
 141         bfin_irq_flags |= 1 << d->irq;
 142         /*
 143          * If interrupts are enabled, IMASK must contain the same value
 144          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 145          * are currently disabled we need not do anything; one of the
 146          * callers will take care of setting IMASK to the proper value
 147          * when reenabling interrupts.
 148          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 149          * what we need.
 150          */
 151         if (!hard_irqs_disabled())
 152                 hard_local_irq_enable();
 153         return;
 154 }
 155
 156 static void bfin_internal_mask_irq(unsigned int irq)
 157 {
 158         unsigned long flags;
 159
 160 #ifdef CONFIG_BF53x
 161         flags = hard_local_irq_save();
 162         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 163                              ~(1 << SIC_SYSIRQ(irq)));
 164 #else
 165         unsigned mask_bank, mask_bit;
 166         flags = hard_local_irq_save();
 167         mask_bank = SIC_SYSIRQ(irq) / 32;
 168         mask_bit = SIC_SYSIRQ(irq) % 32;
 169         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 170                              ~(1 << mask_bit));
 171 #ifdef CONFIG_SMP
 172         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 173                              ~(1 << mask_bit));
 174 #endif
 175 #endif
 176         hard_local_irq_restore(flags);
 177 }
 178
 179 static void bfin_internal_mask_irq_chip(struct irq_data *d)
 180 {
 181         bfin_internal_mask_irq(d->irq);
 182 }
 183
 184 #ifdef CONFIG_SMP
 185 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
 186                 const struct cpumask *affinity)
 187 #else
 188 static void bfin_internal_unmask_irq(unsigned int irq)
 189 #endif
 190 {
 191         unsigned long flags;
 192
 193 #ifdef CONFIG_BF53x
 194         flags = hard_local_irq_save();
 195         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 196                              (1 << SIC_SYSIRQ(irq)));
 197 #else
 198         unsigned mask_bank, mask_bit;
 199         flags = hard_local_irq_save();
 200         mask_bank = SIC_SYSIRQ(irq) / 32;
 201         mask_bit = SIC_SYSIRQ(irq) % 32;
 202 #ifdef CONFIG_SMP
 203         if (cpumask_test_cpu(0, affinity))
 204 #endif
 205                 bfin_write_SIC_IMASK(mask_bank,
 206                         bfin_read_SIC_IMASK(mask_bank) |
 207                         (1 << mask_bit));
 208 #ifdef CONFIG_SMP
 209         if (cpumask_test_cpu(1, affinity))
 210                 bfin_write_SICB_IMASK(mask_bank,
 211                         bfin_read_SICB_IMASK(mask_bank) |
 212                         (1 << mask_bit));
 213 #endif
 214 #endif
 215         hard_local_irq_restore(flags);
 216 }
 217
 218 #ifdef CONFIG_SMP
 219 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 220 {
 221         bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
 222 }
 223
 224 static int bfin_internal_set_affinity(struct irq_data *d,
 225                                       const struct cpumask *mask, bool force)
 226 {
 227         bfin_internal_mask_irq(d->irq);
 228         bfin_internal_unmask_irq_affinity(d->irq, mask);
 229
 230         return 0;
 231 }
 232 #else
 233 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 234 {
 235         bfin_internal_unmask_irq(d->irq);
 236 }
 237 #endif
 238
 239 #ifdef CONFIG_PM
 240 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 241 {
 242         u32 bank, bit, wakeup = 0;
 243         unsigned long flags;
 244         bank = SIC_SYSIRQ(irq) / 32;
 245         bit = SIC_SYSIRQ(irq) % 32;
 246
 247         switch (irq) {
 248 #ifdef IRQ_RTC
 249         case IRQ_RTC:
 250         wakeup |= WAKE;
 251         break;
 252 #endif
 253 #ifdef IRQ_CAN0_RX
 254         case IRQ_CAN0_RX:
 255         wakeup |= CANWE;
 256         break;
 257 #endif
 258 #ifdef IRQ_CAN1_RX
 259         case IRQ_CAN1_RX:
 260         wakeup |= CANWE;
 261         break;
 262 #endif
 263 #ifdef IRQ_USB_INT0
 264         case IRQ_USB_INT0:
 265         wakeup |= USBWE;
 266         break;
 267 #endif
 268 #ifdef CONFIG_BF54x
 269         case IRQ_CNT:
 270         wakeup |= ROTWE;
 271         break;
 272 #endif
 273         default:
 274         break;
 275         }
 276
 277         flags = hard_local_irq_save();
 278
 279         if (state) {
 280                 bfin_sic_iwr[bank] |= (1 << bit);
 281                 vr_wakeup  |= wakeup;
 282
 283         } else {
 284                 bfin_sic_iwr[bank] &= ~(1 << bit);
 285                 vr_wakeup  &= ~wakeup;
 286         }
 287
 288         hard_local_irq_restore(flags);
 289
 290         return 0;
 291 }
 292
 293 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 294 {
 295         return bfin_internal_set_wake(d->irq, state);
 296 }
 297 #endif
 298
 299 static struct irq_chip bfin_core_irqchip = {
 300         .name = "CORE",
 301         .irq_ack = bfin_ack_noop,
 302         .irq_mask = bfin_core_mask_irq,
 303         .irq_unmask = bfin_core_unmask_irq,
 304 };
 305
 306 static struct irq_chip bfin_internal_irqchip = {
 307         .name = "INTN",
 308         .irq_ack = bfin_ack_noop,
 309         .irq_mask = bfin_internal_mask_irq_chip,
 310         .irq_unmask = bfin_internal_unmask_irq_chip,
 311         .irq_mask_ack = bfin_internal_mask_irq_chip,
 312         .irq_disable = bfin_internal_mask_irq_chip,
 313         .irq_enable = bfin_internal_unmask_irq_chip,
 314 #ifdef CONFIG_SMP
 315         .irq_set_affinity = bfin_internal_set_affinity,
 316 #endif
 317 #ifdef CONFIG_PM
 318         .irq_set_wake = bfin_internal_set_wake_chip,
 319 #endif
 320 };
 321
 322 static void bfin_handle_irq(unsigned irq)
 323 {
 324 #ifdef CONFIG_IPIPE
 325         struct pt_regs regs;    /* Contents not used. */
 326         ipipe_trace_irq_entry(irq);
 327         __ipipe_handle_irq(irq, &regs);
 328         ipipe_trace_irq_exit(irq);
 329 #else /* !CONFIG_IPIPE */
 330         generic_handle_irq(irq);
 331 #endif  /* !CONFIG_IPIPE */
 332 }
 333
 334 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 335 static int error_int_mask;
 336
 337 static void bfin_generic_error_mask_irq(struct irq_data *d)
 338 {
 339         error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
 340         if (!error_int_mask)
 341                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 342 }
 343
 344 static void bfin_generic_error_unmask_irq(struct irq_data *d)
 345 {
 346         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 347         error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
 348 }
 349
 350 static struct irq_chip bfin_generic_error_irqchip = {
 351         .name = "ERROR",
 352         .irq_ack = bfin_ack_noop,
 353         .irq_mask_ack = bfin_generic_error_mask_irq,
 354         .irq_mask = bfin_generic_error_mask_irq,
 355         .irq_unmask = bfin_generic_error_unmask_irq,
 356 };
 357
 358 static void bfin_demux_error_irq(unsigned int int_err_irq,
 359                                  struct irq_desc *inta_desc)
 360 {
 361         int irq = 0;
 362
 363 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 364         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 365                 irq = IRQ_MAC_ERROR;
 366         else
 367 #endif
 368         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 369                 irq = IRQ_SPORT0_ERROR;
 370         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 371                 irq = IRQ_SPORT1_ERROR;
 372         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 373                 irq = IRQ_PPI_ERROR;
 374         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 375                 irq = IRQ_CAN_ERROR;
 376         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 377                 irq = IRQ_SPI_ERROR;
 378         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 379                 irq = IRQ_UART0_ERROR;
 380         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 381                 irq = IRQ_UART1_ERROR;
 382
 383         if (irq) {
 384                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
 385                         bfin_handle_irq(irq);
 386                 else {
 387
 388                         switch (irq) {
 389                         case IRQ_PPI_ERROR:
 390                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 391                                 break;
 392 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 393                         case IRQ_MAC_ERROR:
 394                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 395                                 break;
 396 #endif
 397                         case IRQ_SPORT0_ERROR:
 398                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 399                                 break;
 400
 401                         case IRQ_SPORT1_ERROR:
 402                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 403                                 break;
 404
 405                         case IRQ_CAN_ERROR:
 406                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 407                                 break;
 408
 409                         case IRQ_SPI_ERROR:
 410                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 411                                 break;
 412
 413                         default:
 414                                 break;
 415                         }
 416
 417                         pr_debug("IRQ %d:"
 418                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 419                                  irq);
 420                 }
 421         } else
 422                 printk(KERN_ERR
 423                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 424                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 425                        __func__, __FILE__, __LINE__);
 426
 427 }
 428 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 429
 430 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 431 static int mac_stat_int_mask;
 432
 433 static void bfin_mac_status_ack_irq(unsigned int irq)
 434 {
 435         switch (irq) {
 436         case IRQ_MAC_MMCINT:
 437                 bfin_write_EMAC_MMC_TIRQS(
 438                         bfin_read_EMAC_MMC_TIRQE() &
 439                         bfin_read_EMAC_MMC_TIRQS());
 440                 bfin_write_EMAC_MMC_RIRQS(
 441                         bfin_read_EMAC_MMC_RIRQE() &
 442                         bfin_read_EMAC_MMC_RIRQS());
 443                 break;
 444         case IRQ_MAC_RXFSINT:
 445                 bfin_write_EMAC_RX_STKY(
 446                         bfin_read_EMAC_RX_IRQE() &
 447                         bfin_read_EMAC_RX_STKY());
 448                 break;
 449         case IRQ_MAC_TXFSINT:
 450                 bfin_write_EMAC_TX_STKY(
 451                         bfin_read_EMAC_TX_IRQE() &
 452                         bfin_read_EMAC_TX_STKY());
 453                 break;
 454         case IRQ_MAC_WAKEDET:
 455                  bfin_write_EMAC_WKUP_CTL(
 456                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 457                 break;
 458         default:
 459                 /* These bits are W1C */
 460                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 461                 break;
 462         }
 463 }
 464
 465 static void bfin_mac_status_mask_irq(struct irq_data *d)
 466 {
 467         unsigned int irq = d->irq;
 468
 469         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 470 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 471         switch (irq) {
 472         case IRQ_MAC_PHYINT:
 473                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 474                 break;
 475         default:
 476                 break;
 477         }
 478 #else
 479         if (!mac_stat_int_mask)
 480                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 481 #endif
 482         bfin_mac_status_ack_irq(irq);
 483 }
 484
 485 static void bfin_mac_status_unmask_irq(struct irq_data *d)
 486 {
 487         unsigned int irq = d->irq;
 488
 489 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 490         switch (irq) {
 491         case IRQ_MAC_PHYINT:
 492                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 493                 break;
 494         default:
 495                 break;
 496         }
 497 #else
 498         if (!mac_stat_int_mask)
 499                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 500 #endif
 501         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 502 }
 503
 504 #ifdef CONFIG_PM
 505 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 506 {
 507 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 508         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 509 #else
 510         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 511 #endif
 512 }
 513 #endif
 514
 515 static struct irq_chip bfin_mac_status_irqchip = {
 516         .name = "MACST",
 517         .irq_ack = bfin_ack_noop,
 518         .irq_mask_ack = bfin_mac_status_mask_irq,
 519         .irq_mask = bfin_mac_status_mask_irq,
 520         .irq_unmask = bfin_mac_status_unmask_irq,
 521 #ifdef CONFIG_PM
 522         .irq_set_wake = bfin_mac_status_set_wake,
 523 #endif
 524 };
 525
 526 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 527                                  struct irq_desc *inta_desc)
 528 {
 529         int i, irq = 0;
 530         u32 status = bfin_read_EMAC_SYSTAT();
 531
 532         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 533                 if (status & (1L << i)) {
 534                         irq = IRQ_MAC_PHYINT + i;
 535                         break;
 536                 }
 537
 538         if (irq) {
 539                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 540                         bfin_handle_irq(irq);
 541                 } else {
 542                         bfin_mac_status_ack_irq(irq);
 543                         pr_debug("IRQ %d:"
 544                                  " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 545                                  irq);
 546                 }
 547         } else
 548                 printk(KERN_ERR
 549                        "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 550                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
 551                        "(EMAC_SYSTAT=0x%X)\n",
 552                        __func__, __FILE__, __LINE__, status);
 553 }
 554 #endif
 555
 556 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 557 {
 558 #ifdef CONFIG_IPIPE
 559         _set_irq_handler(irq, handle_level_irq);
 560 #else
 561         __set_irq_handler_unlocked(irq, handle);
 562 #endif
 563 }
 564
 565 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 566 extern void bfin_gpio_irq_prepare(unsigned gpio);
 567
 568 #if !defined(CONFIG_BF54x)
 569
 570 static void bfin_gpio_ack_irq(struct irq_data *d)
 571 {
 572         /* AFAIK ack_irq in case mask_ack is provided
 573          * get's only called for edge sense irqs
 574          */
 575         set_gpio_data(irq_to_gpio(d->irq), 0);
 576 }
 577
 578 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 579 {
 580         unsigned int irq = d->irq;
 581         struct irq_desc *desc = irq_to_desc(irq);
 582         u32 gpionr = irq_to_gpio(irq);
 583
 584         if (desc->handle_irq == handle_edge_irq)
 585                 set_gpio_data(gpionr, 0);
 586
 587         set_gpio_maska(gpionr, 0);
 588 }
 589
 590 static void bfin_gpio_mask_irq(struct irq_data *d)
 591 {
 592         set_gpio_maska(irq_to_gpio(d->irq), 0);
 593 }
 594
 595 static void bfin_gpio_unmask_irq(struct irq_data *d)
 596 {
 597         set_gpio_maska(irq_to_gpio(d->irq), 1);
 598 }
 599
 600 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 601 {
 602         u32 gpionr = irq_to_gpio(d->irq);
 603
 604         if (__test_and_set_bit(gpionr, gpio_enabled))
 605                 bfin_gpio_irq_prepare(gpionr);
 606
 607         bfin_gpio_unmask_irq(d);
 608
 609         return 0;
 610 }
 611
 612 static void bfin_gpio_irq_shutdown(struct irq_data *d)
 613 {
 614         u32 gpionr = irq_to_gpio(d->irq);
 615
 616         bfin_gpio_mask_irq(d);
 617         __clear_bit(gpionr, gpio_enabled);
 618         bfin_gpio_irq_free(gpionr);
 619 }
 620
 621 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 622 {
 623         unsigned int irq = d->irq;
 624         int ret;
 625         char buf[16];
 626         u32 gpionr = irq_to_gpio(irq);
 627
 628         if (type == IRQ_TYPE_PROBE) {
 629                 /* only probe unenabled GPIO interrupt lines */
 630                 if (test_bit(gpionr, gpio_enabled))
 631                         return 0;
 632                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 633         }
 634
 635         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 636                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 637
 638                 snprintf(buf, 16, "gpio-irq%d", irq);
 639                 ret = bfin_gpio_irq_request(gpionr, buf);
 640                 if (ret)
 641                         return ret;
 642
 643                 if (__test_and_set_bit(gpionr, gpio_enabled))
 644                         bfin_gpio_irq_prepare(gpionr);
 645
 646         } else {
 647                 __clear_bit(gpionr, gpio_enabled);
 648                 return 0;
 649         }
 650
 651         set_gpio_inen(gpionr, 0);
 652         set_gpio_dir(gpionr, 0);
 653
 654         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 655             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 656                 set_gpio_both(gpionr, 1);
 657         else
 658                 set_gpio_both(gpionr, 0);
 659
 660         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 661                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 662         else
 663                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 664
 665         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 666                 set_gpio_edge(gpionr, 1);
 667                 set_gpio_inen(gpionr, 1);
 668                 set_gpio_data(gpionr, 0);
 669
 670         } else {
 671                 set_gpio_edge(gpionr, 0);
 672                 set_gpio_inen(gpionr, 1);
 673         }
 674
 675         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 676                 bfin_set_irq_handler(irq, handle_edge_irq);
 677         else
 678                 bfin_set_irq_handler(irq, handle_level_irq);
 679
 680         return 0;
 681 }
 682
 683 #ifdef CONFIG_PM
 684 int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 685 {
 686         return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
 687 }
 688 #endif
 689
 690 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 691                                 struct irq_desc *desc)
 692 {
 693         unsigned int i, gpio, mask, irq, search = 0;
 694
 695         switch (inta_irq) {
 696 #if defined(CONFIG_BF53x)
 697         case IRQ_PROG_INTA:
 698                 irq = IRQ_PF0;
 699                 search = 1;
 700                 break;
 701 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 702         case IRQ_MAC_RX:
 703                 irq = IRQ_PH0;
 704                 break;
 705 # endif
 706 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 707         case IRQ_PORTF_INTA:
 708                 irq = IRQ_PF0;
 709                 break;
 710 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 711         case IRQ_PORTF_INTA:
 712                 irq = IRQ_PF0;
 713                 break;
 714         case IRQ_PORTG_INTA:
 715                 irq = IRQ_PG0;
 716                 break;
 717         case IRQ_PORTH_INTA:
 718                 irq = IRQ_PH0;
 719                 break;
 720 #elif defined(CONFIG_BF561)
 721         case IRQ_PROG0_INTA:
 722                 irq = IRQ_PF0;
 723                 break;
 724         case IRQ_PROG1_INTA:
 725                 irq = IRQ_PF16;
 726                 break;
 727         case IRQ_PROG2_INTA:
 728                 irq = IRQ_PF32;
 729                 break;
 730 #endif
 731         default:
 732                 BUG();
 733                 return;
 734         }
 735
 736         if (search) {
 737                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 738                         irq += i;
 739
 740                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 741
 742                         while (mask) {
 743                                 if (mask & 1)
 744                                         bfin_handle_irq(irq);
 745                                 irq++;
 746                                 mask >>= 1;
 747                         }
 748                 }
 749         } else {
 750                         gpio = irq_to_gpio(irq);
 751                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 752
 753                         do {
 754                                 if (mask & 1)
 755                                         bfin_handle_irq(irq);
 756                                 irq++;
 757                                 mask >>= 1;
 758                         } while (mask);
 759         }
 760
 761 }
 762
 763 #else                           /* CONFIG_BF54x */
 764
 765 #define NR_PINT_SYS_IRQS        4
 766 #define NR_PINT_BITS            32
 767 #define NR_PINTS                160
 768 #define IRQ_NOT_AVAIL           0xFF
 769
 770 #define PINT_2_BANK(x)          ((x) >> 5)
 771 #define PINT_2_BIT(x)           ((x) & 0x1F)
 772 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 773
 774 static unsigned char irq2pint_lut[NR_PINTS];
 775 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 776
 777 struct pin_int_t {
 778         unsigned int mask_set;
 779         unsigned int mask_clear;
 780         unsigned int request;
 781         unsigned int assign;
 782         unsigned int edge_set;
 783         unsigned int edge_clear;
 784         unsigned int invert_set;
 785         unsigned int invert_clear;
 786         unsigned int pinstate;
 787         unsigned int latch;
 788 };
 789
 790 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 791         (struct pin_int_t *)PINT0_MASK_SET,
 792         (struct pin_int_t *)PINT1_MASK_SET,
 793         (struct pin_int_t *)PINT2_MASK_SET,
 794         (struct pin_int_t *)PINT3_MASK_SET,
 795 };
 796
 797 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 798 {
 799         unsigned int irq_base;
 800
 801         if (bank < 2) {         /*PA-PB */
 802                 irq_base = IRQ_PA0 + bmap * 16;
 803         } else {                /*PC-PJ */
 804                 irq_base = IRQ_PC0 + bmap * 16;
 805         }
 806
 807         return irq_base;
 808 }
 809
 810         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 811 void init_pint_lut(void)
 812 {
 813         u16 bank, bit, irq_base, bit_pos;
 814         u32 pint_assign;
 815         u8 bmap;
 816
 817         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 818
 819         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 820
 821                 pint_assign = pint[bank]->assign;
 822
 823                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 824
 825                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 826
 827                         irq_base = get_irq_base(bank, bmap);
 828
 829                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 830                         bit_pos = bit + bank * NR_PINT_BITS;
 831
 832                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 833                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 834                 }
 835         }
 836 }
 837
 838 static void bfin_gpio_ack_irq(struct irq_data *d)
 839 {
 840         struct irq_desc *desc = irq_to_desc(d->irq);
 841         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 842         u32 pintbit = PINT_BIT(pint_val);
 843         u32 bank = PINT_2_BANK(pint_val);
 844
 845         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 846                 if (pint[bank]->invert_set & pintbit)
 847                         pint[bank]->invert_clear = pintbit;
 848                 else
 849                         pint[bank]->invert_set = pintbit;
 850         }
 851         pint[bank]->request = pintbit;
 852
 853 }
 854
 855 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 856 {
 857         struct irq_desc *desc = irq_to_desc(d->irq);
 858         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 859         u32 pintbit = PINT_BIT(pint_val);
 860         u32 bank = PINT_2_BANK(pint_val);
 861
 862         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 863                 if (pint[bank]->invert_set & pintbit)
 864                         pint[bank]->invert_clear = pintbit;
 865                 else
 866                         pint[bank]->invert_set = pintbit;
 867         }
 868
 869         pint[bank]->request = pintbit;
 870         pint[bank]->mask_clear = pintbit;
 871 }
 872
 873 static void bfin_gpio_mask_irq(struct irq_data *d)
 874 {
 875         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 876
 877         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 878 }
 879
 880 static void bfin_gpio_unmask_irq(struct irq_data *d)
 881 {
 882         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 883         u32 pintbit = PINT_BIT(pint_val);
 884         u32 bank = PINT_2_BANK(pint_val);
 885
 886         pint[bank]->mask_set = pintbit;
 887 }
 888
 889 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 890 {
 891         unsigned int irq = d->irq;
 892         u32 gpionr = irq_to_gpio(irq);
 893         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 894
 895         if (pint_val == IRQ_NOT_AVAIL) {
 896                 printk(KERN_ERR
 897                 "GPIO IRQ %d :Not in PINT Assign table "
 898                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 899                 return -ENODEV;
 900         }
 901
 902         if (__test_and_set_bit(gpionr, gpio_enabled))
 903                 bfin_gpio_irq_prepare(gpionr);
 904
 905         bfin_gpio_unmask_irq(d);
 906
 907         return 0;
 908 }
 909
 910 static void bfin_gpio_irq_shutdown(struct irq_data *d)
 911 {
 912         u32 gpionr = irq_to_gpio(d->irq);
 913
 914         bfin_gpio_mask_irq(d);
 915         __clear_bit(gpionr, gpio_enabled);
 916         bfin_gpio_irq_free(gpionr);
 917 }
 918
 919 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 920 {
 921         unsigned int irq = d->irq;
 922         int ret;
 923         char buf[16];
 924         u32 gpionr = irq_to_gpio(irq);
 925         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 926         u32 pintbit = PINT_BIT(pint_val);
 927         u32 bank = PINT_2_BANK(pint_val);
 928
 929         if (pint_val == IRQ_NOT_AVAIL)
 930                 return -ENODEV;
 931
 932         if (type == IRQ_TYPE_PROBE) {
 933                 /* only probe unenabled GPIO interrupt lines */
 934                 if (test_bit(gpionr, gpio_enabled))
 935                         return 0;
 936                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 937         }
 938
 939         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 940                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 941
 942                 snprintf(buf, 16, "gpio-irq%d", irq);
 943                 ret = bfin_gpio_irq_request(gpionr, buf);
 944                 if (ret)
 945                         return ret;
 946
 947                 if (__test_and_set_bit(gpionr, gpio_enabled))
 948                         bfin_gpio_irq_prepare(gpionr);
 949
 950         } else {
 951                 __clear_bit(gpionr, gpio_enabled);
 952                 return 0;
 953         }
 954
 955         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 956                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 957         else
 958                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 959
 960         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 961             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 962                 if (gpio_get_value(gpionr))
 963                         pint[bank]->invert_set = pintbit;
 964                 else
 965                         pint[bank]->invert_clear = pintbit;
 966         }
 967
 968         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 969                 pint[bank]->edge_set = pintbit;
 970                 bfin_set_irq_handler(irq, handle_edge_irq);
 971         } else {
 972                 pint[bank]->edge_clear = pintbit;
 973                 bfin_set_irq_handler(irq, handle_level_irq);
 974         }
 975
 976         return 0;
 977 }
 978
 979 #ifdef CONFIG_PM
 980 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 981 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 982
 983 int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 984 {
 985         u32 pint_irq;
 986         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
 987         u32 bank = PINT_2_BANK(pint_val);
 988         u32 pintbit = PINT_BIT(pint_val);
 989
 990         switch (bank) {
 991         case 0:
 992                 pint_irq = IRQ_PINT0;
 993                 break;
 994         case 2:
 995                 pint_irq = IRQ_PINT2;
 996                 break;
 997         case 3:
 998                 pint_irq = IRQ_PINT3;
 999                 break;
1000         case 1:
1001                 pint_irq = IRQ_PINT1;
1002                 break;
1003         default:
1004                 return -EINVAL;
1005         }
1006
1007         bfin_internal_set_wake(pint_irq, state);
1008
1009         if (state)
1010                 pint_wakeup_masks[bank] |= pintbit;
1011         else
1012                 pint_wakeup_masks[bank] &= ~pintbit;
1013
1014         return 0;
1015 }
1016
1017 u32 bfin_pm_setup(void)
1018 {
1019         u32 val, i;
1020
1021         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1022                 val = pint[i]->mask_clear;
1023                 pint_saved_masks[i] = val;
1024                 if (val ^ pint_wakeup_masks[i]) {
1025                         pint[i]->mask_clear = val;
1026                         pint[i]->mask_set = pint_wakeup_masks[i];
1027                 }
1028         }
1029
1030         return 0;
1031 }
1032
1033 void bfin_pm_restore(void)
1034 {
1035         u32 i, val;
1036
1037         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1038                 val = pint_saved_masks[i];
1039                 if (val ^ pint_wakeup_masks[i]) {
1040                         pint[i]->mask_clear = pint[i]->mask_clear;
1041                         pint[i]->mask_set = val;
1042                 }
1043         }
1044 }
1045 #endif
1046
1047 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1048                                 struct irq_desc *desc)
1049 {
1050         u32 bank, pint_val;
1051         u32 request, irq;
1052
1053         switch (inta_irq) {
1054         case IRQ_PINT0:
1055                 bank = 0;
1056                 break;
1057         case IRQ_PINT2:
1058                 bank = 2;
1059                 break;
1060         case IRQ_PINT3:
1061                 bank = 3;
1062                 break;
1063         case IRQ_PINT1:
1064                 bank = 1;
1065                 break;
1066         default:
1067                 return;
1068         }
1069
1070         pint_val = bank * NR_PINT_BITS;
1071
1072         request = pint[bank]->request;
1073
1074         while (request) {
1075                 if (request & 1) {
1076                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1077                         bfin_handle_irq(irq);
1078                 }
1079                 pint_val++;
1080                 request >>= 1;
1081         }
1082
1083 }
1084 #endif
1085
1086 static struct irq_chip bfin_gpio_irqchip = {
1087         .name = "GPIO",
1088         .irq_ack = bfin_gpio_ack_irq,
1089         .irq_mask = bfin_gpio_mask_irq,
1090         .irq_mask_ack = bfin_gpio_mask_ack_irq,
1091         .irq_unmask = bfin_gpio_unmask_irq,
1092         .irq_disable = bfin_gpio_mask_irq,
1093         .irq_enable = bfin_gpio_unmask_irq,
1094         .irq_set_type = bfin_gpio_irq_type,
1095         .irq_startup = bfin_gpio_irq_startup,
1096         .irq_shutdown = bfin_gpio_irq_shutdown,
1097 #ifdef CONFIG_PM
1098         .irq_set_wake = bfin_gpio_set_wake,
1099 #endif
1100 };
1101
1102 void __cpuinit init_exception_vectors(void)
1103 {
1104         /* cannot program in software:
1105          * evt0 - emulation (jtag)
1106          * evt1 - reset
1107          */
1108         bfin_write_EVT2(evt_nmi);
1109         bfin_write_EVT3(trap);
1110         bfin_write_EVT5(evt_ivhw);
1111         bfin_write_EVT6(evt_timer);
1112         bfin_write_EVT7(evt_evt7);
1113         bfin_write_EVT8(evt_evt8);
1114         bfin_write_EVT9(evt_evt9);
1115         bfin_write_EVT10(evt_evt10);
1116         bfin_write_EVT11(evt_evt11);
1117         bfin_write_EVT12(evt_evt12);
1118         bfin_write_EVT13(evt_evt13);
1119         bfin_write_EVT14(evt_evt14);
1120         bfin_write_EVT15(evt_system_call);
1121         CSYNC();
1122 }
1123
1124 /*
1125  * This function should be called during kernel startup to initialize
1126  * the BFin IRQ handling routines.
1127  */
1128
1129 int __init init_arch_irq(void)
1130 {
1131         int irq;
1132         unsigned long ilat = 0;
1133         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1134 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1135         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1136         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1137         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1138 # ifdef CONFIG_BF54x
1139         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1140 # endif
1141 # ifdef CONFIG_SMP
1142         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1143         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1144 # endif
1145 #else
1146         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1147 #endif
1148
1149         local_irq_disable();
1150
1151 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1152         /* Clear EMAC Interrupt Status bits so we can demux it later */
1153         bfin_write_EMAC_SYSTAT(-1);
1154 #endif
1155
1156 #ifdef CONFIG_BF54x
1157 # ifdef CONFIG_PINTx_REASSIGN
1158         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1159         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1160         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1161         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1162 # endif
1163         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1164         init_pint_lut();
1165 #endif
1166
1167         for (irq = 0; irq <= SYS_IRQS; irq++) {
1168                 if (irq <= IRQ_CORETMR)
1169                         set_irq_chip(irq, &bfin_core_irqchip);
1170                 else
1171                         set_irq_chip(irq, &bfin_internal_irqchip);
1172
1173                 switch (irq) {
1174 #if defined(CONFIG_BF53x)
1175                 case IRQ_PROG_INTA:
1176 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1177                 case IRQ_MAC_RX:
1178 # endif
1179 #elif defined(CONFIG_BF54x)
1180                 case IRQ_PINT0:
1181                 case IRQ_PINT1:
1182                 case IRQ_PINT2:
1183                 case IRQ_PINT3:
1184 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1185                 case IRQ_PORTF_INTA:
1186                 case IRQ_PORTG_INTA:
1187                 case IRQ_PORTH_INTA:
1188 #elif defined(CONFIG_BF561)
1189                 case IRQ_PROG0_INTA:
1190                 case IRQ_PROG1_INTA:
1191                 case IRQ_PROG2_INTA:
1192 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1193                 case IRQ_PORTF_INTA:
1194 #endif
1195                         set_irq_chained_handler(irq,
1196                                                 bfin_demux_gpio_irq);
1197                         break;
1198 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1199                 case IRQ_GENERIC_ERROR:
1200                         set_irq_chained_handler(irq, bfin_demux_error_irq);
1201                         break;
1202 #endif
1203 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1204                 case IRQ_MAC_ERROR:
1205                         set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1206                         break;
1207 #endif
1208 #ifdef CONFIG_SMP
1209                 case IRQ_SUPPLE_0:
1210                 case IRQ_SUPPLE_1:
1211                         set_irq_handler(irq, handle_percpu_irq);
1212                         break;
1213 #endif
1214
1215 #ifdef CONFIG_TICKSOURCE_CORETMR
1216                 case IRQ_CORETMR:
1217 # ifdef CONFIG_SMP
1218                         set_irq_handler(irq, handle_percpu_irq);
1219                         break;
1220 # else
1221                         set_irq_handler(irq, handle_simple_irq);
1222                         break;
1223 # endif
1224 #endif
1225
1226 #ifdef CONFIG_TICKSOURCE_GPTMR0
1227                 case IRQ_TIMER0:
1228                         set_irq_handler(irq, handle_simple_irq);
1229                         break;
1230 #endif
1231
1232 #ifdef CONFIG_IPIPE
1233                 default:
1234                         set_irq_handler(irq, handle_level_irq);
1235                         break;
1236 #else /* !CONFIG_IPIPE */
1237                 default:
1238                         set_irq_handler(irq, handle_simple_irq);
1239                         break;
1240 #endif /* !CONFIG_IPIPE */
1241                 }
1242         }
1243
1244 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1245         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1246                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1247                                          handle_level_irq);
1248 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1249         set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1250 #endif
1251 #endif
1252
1253 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1254         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1255                 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1256                                          handle_level_irq);
1257 #endif
1258         /* if configured as edge, then will be changed to do_edge_IRQ */
1259         for (irq = GPIO_IRQ_BASE;
1260                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1261                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1262                                          handle_level_irq);
1263
1264         bfin_write_IMASK(0);
1265         CSYNC();
1266         ilat = bfin_read_ILAT();
1267         CSYNC();
1268         bfin_write_ILAT(ilat);
1269         CSYNC();
1270
1271         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1272         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1273          * local_irq_enable()
1274          */
1275         program_IAR();
1276         /* Therefore it's better to setup IARs before interrupts enabled */
1277         search_IAR();
1278
1279         /* Enable interrupts IVG7-15 */
1280         bfin_irq_flags |= IMASK_IVG15 |
1281             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1282             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1283
1284         /* This implicitly covers ANOMALY_05000171
1285          * Boot-ROM code modifies SICA_IWRx wakeup registers
1286          */
1287 #ifdef SIC_IWR0
1288         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1289 # ifdef SIC_IWR1
1290         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1291          * will screw up the bootrom as it relies on MDMA0/1 waking it
1292          * up from IDLE instructions.  See this report for more info:
1293          * http://blackfin.uclinux.org/gf/tracker/4323
1294          */
1295         if (ANOMALY_05000435)
1296                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1297         else
1298                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1299 # endif
1300 # ifdef SIC_IWR2
1301         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1302 # endif
1303 #else
1304         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1305 #endif
1306
1307         return 0;
1308 }
1309
1310 #ifdef CONFIG_DO_IRQ_L1
1311 __attribute__((l1_text))
1312 #endif
1313 void do_irq(int vec, struct pt_regs *fp)
1314 {
1315         if (vec == EVT_IVTMR_P) {
1316                 vec = IRQ_CORETMR;
1317         } else {
1318                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1319                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1320 #if defined(SIC_ISR0)
1321                 unsigned long sic_status[3];
1322
1323                 if (smp_processor_id()) {
1324 # ifdef SICB_ISR0
1325                         /* This will be optimized out in UP mode. */
1326                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1327                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1328 # endif
1329                 } else {
1330                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1331                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1332                 }
1333 # ifdef SIC_ISR2
1334                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1335 # endif
1336                 for (;; ivg++) {
1337                         if (ivg >= ivg_stop) {
1338                                 atomic_inc(&num_spurious);
1339                                 return;
1340                         }
1341                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1342                                 break;
1343                 }
1344 #else
1345                 unsigned long sic_status;
1346
1347                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1348
1349                 for (;; ivg++) {
1350                         if (ivg >= ivg_stop) {
1351                                 atomic_inc(&num_spurious);
1352                                 return;
1353                         } else if (sic_status & ivg->isrflag)
1354                                 break;
1355                 }
1356 #endif
1357                 vec = ivg->irqno;
1358         }
1359         asm_do_IRQ(vec, fp);
1360 }
1361
1362 #ifdef CONFIG_IPIPE
1363
1364 int __ipipe_get_irq_priority(unsigned irq)
1365 {
1366         int ient, prio;
1367
1368         if (irq <= IRQ_CORETMR)
1369                 return irq;
1370
1371         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1372                 struct ivgx *ivg = ivg_table + ient;
1373                 if (ivg->irqno == irq) {
1374                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1375                                 if (ivg7_13[prio].ifirst <= ivg &&
1376                                     ivg7_13[prio].istop > ivg)
1377                                         return IVG7 + prio;
1378                         }
1379                 }
1380         }
1381
1382         return IVG15;
1383 }
1384
1385 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1386 #ifdef CONFIG_DO_IRQ_L1
1387 __attribute__((l1_text))
1388 #endif
1389 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1390 {
1391         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1392         struct ipipe_domain *this_domain = __ipipe_current_domain;
1393         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1394         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1395         int irq, s;
1396
1397         if (likely(vec == EVT_IVTMR_P))
1398                 irq = IRQ_CORETMR;
1399         else {
1400 #if defined(SIC_ISR0)
1401                 unsigned long sic_status[3];
1402
1403                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1404                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1405 # ifdef SIC_ISR2
1406                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1407 # endif
1408                 for (;; ivg++) {
1409                         if (ivg >= ivg_stop) {
1410                                 atomic_inc(&num_spurious);
1411                                 return 0;
1412                         }
1413                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1414                                 break;
1415                 }
1416 #else
1417                 unsigned long sic_status;
1418
1419                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1420
1421                 for (;; ivg++) {
1422                         if (ivg >= ivg_stop) {
1423                                 atomic_inc(&num_spurious);
1424                                 return 0;
1425                         } else if (sic_status & ivg->isrflag)
1426                                 break;
1427                 }
1428 #endif
1429                 irq = ivg->irqno;
1430         }
1431
1432         if (irq == IRQ_SYSTMR) {
1433 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1434                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1435 #endif
1436                 /* This is basically what we need from the register frame. */
1437                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1438                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1439                 if (this_domain != ipipe_root_domain)
1440                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1441                 else
1442                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1443         }
1444
1445         if (this_domain == ipipe_root_domain) {
1446                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1447                 barrier();
1448         }
1449
1450         ipipe_trace_irq_entry(irq);
1451         __ipipe_handle_irq(irq, regs);
1452         ipipe_trace_irq_exit(irq);
1453
1454         if (this_domain == ipipe_root_domain) {
1455                 set_thread_flag(TIF_IRQ_SYNC);
1456                 if (!s) {
1457                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1458                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1459                 }
1460         }
1461
1462         return 0;
1463 }
1464
1465 #endif /* CONFIG_IPIPE */