arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #ifdef CONFIG_IPIPE
  19 #include <linux/ipipe.h>
  20 #endif
  21 #ifdef CONFIG_KGDB
  22 #include <linux/kgdb.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29 #include <asm/bfin5xx_spi.h>
  30 #include <asm/bfin_sport.h>
  31 #include <asm/bfin_can.h>
  32
  33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  34
  35 #ifdef BF537_FAMILY
  36 # define BF537_GENERIC_ERROR_INT_DEMUX
  37 # define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
  38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
  39 # define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
  40 # define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
  41 # define UART_ERR_MASK  (0x6)   /* UART_IIR */
  42 # define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
  43 #else
  44 # undef BF537_GENERIC_ERROR_INT_DEMUX
  45 #endif
  46
  47 /*
  48  * NOTES:
  49  * - we have separated the physical Hardware interrupt from the
  50  * levels that the LINUX kernel sees (see the description in irq.h)
  51  * -
  52  */
  53
  54 #ifndef CONFIG_SMP
  55 /* Initialize this to an actual value to force it into the .data
  56  * section so that we know it is properly initialized at entry into
  57  * the kernel but before bss is initialized to zero (which is where
  58  * it would live otherwise).  The 0x1f magic represents the IRQs we
  59  * cannot actually mask out in hardware.
  60  */
  61 unsigned long bfin_irq_flags = 0x1f;
  62 EXPORT_SYMBOL(bfin_irq_flags);
  63 #endif
  64
  65 /* The number of spurious interrupts */
  66 atomic_t num_spurious;
  67
  68 #ifdef CONFIG_PM
  69 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  70 unsigned vr_wakeup;
  71 #endif
  72
  73 struct ivgx {
  74         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  75         unsigned int irqno;
  76         /* corresponding bit in the SIC_ISR register */
  77         unsigned int isrflag;
  78 } ivg_table[NR_PERI_INTS];
  79
  80 struct ivg_slice {
  81         /* position of first irq in ivg_table for given ivg */
  82         struct ivgx *ifirst;
  83         struct ivgx *istop;
  84 } ivg7_13[IVG13 - IVG7 + 1];
  85
  86
  87 /*
  88  * Search SIC_IAR and fill tables with the irqvalues
  89  * and their positions in the SIC_ISR register.
  90  */
  91 static void __init search_IAR(void)
  92 {
  93         unsigned ivg, irq_pos = 0;
  94         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  95                 int irqN;
  96
  97                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  98
  99                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
 100                         int irqn;
 101                         u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
 102 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
 103         defined(CONFIG_BF538) || defined(CONFIG_BF539)
 104                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
 105 #else
 106                                 (irqN >> 3)
 107 #endif
 108                                 );
 109
 110                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
 111                                 int iar_shift = (irqn & 7) * 4;
 112                                 if (ivg == (0xf & (iar >> iar_shift))) {
 113                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
 114                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 115                                         ivg7_13[ivg].istop++;
 116                                         irq_pos++;
 117                                 }
 118                         }
 119                 }
 120         }
 121 }
 122
 123 /*
 124  * This is for core internal IRQs
 125  */
 126
 127 static void bfin_ack_noop(struct irq_data *d)
 128 {
 129         /* Dummy function.  */
 130 }
 131
 132 static void bfin_core_mask_irq(struct irq_data *d)
 133 {
 134         bfin_irq_flags &= ~(1 << d->irq);
 135         if (!hard_irqs_disabled())
 136                 hard_local_irq_enable();
 137 }
 138
 139 static void bfin_core_unmask_irq(struct irq_data *d)
 140 {
 141         bfin_irq_flags |= 1 << d->irq;
 142         /*
 143          * If interrupts are enabled, IMASK must contain the same value
 144          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 145          * are currently disabled we need not do anything; one of the
 146          * callers will take care of setting IMASK to the proper value
 147          * when reenabling interrupts.
 148          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 149          * what we need.
 150          */
 151         if (!hard_irqs_disabled())
 152                 hard_local_irq_enable();
 153         return;
 154 }
 155
 156 static void bfin_internal_mask_irq(unsigned int irq)
 157 {
 158         unsigned long flags;
 159
 160 #ifdef CONFIG_BF53x
 161         flags = hard_local_irq_save();
 162         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 163                              ~(1 << SIC_SYSIRQ(irq)));
 164 #else
 165         unsigned mask_bank, mask_bit;
 166         flags = hard_local_irq_save();
 167         mask_bank = SIC_SYSIRQ(irq) / 32;
 168         mask_bit = SIC_SYSIRQ(irq) % 32;
 169         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 170                              ~(1 << mask_bit));
 171 #ifdef CONFIG_SMP
 172         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 173                              ~(1 << mask_bit));
 174 #endif
 175 #endif
 176         hard_local_irq_restore(flags);
 177 }
 178
 179 static void bfin_internal_mask_irq_chip(struct irq_data *d)
 180 {
 181         bfin_internal_mask_irq(d->irq);
 182 }
 183
 184 #ifdef CONFIG_SMP
 185 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
 186                 const struct cpumask *affinity)
 187 #else
 188 static void bfin_internal_unmask_irq(unsigned int irq)
 189 #endif
 190 {
 191         unsigned long flags;
 192
 193 #ifdef CONFIG_BF53x
 194         flags = hard_local_irq_save();
 195         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 196                              (1 << SIC_SYSIRQ(irq)));
 197 #else
 198         unsigned mask_bank, mask_bit;
 199         flags = hard_local_irq_save();
 200         mask_bank = SIC_SYSIRQ(irq) / 32;
 201         mask_bit = SIC_SYSIRQ(irq) % 32;
 202 #ifdef CONFIG_SMP
 203         if (cpumask_test_cpu(0, affinity))
 204 #endif
 205                 bfin_write_SIC_IMASK(mask_bank,
 206                         bfin_read_SIC_IMASK(mask_bank) |
 207                         (1 << mask_bit));
 208 #ifdef CONFIG_SMP
 209         if (cpumask_test_cpu(1, affinity))
 210                 bfin_write_SICB_IMASK(mask_bank,
 211                         bfin_read_SICB_IMASK(mask_bank) |
 212                         (1 << mask_bit));
 213 #endif
 214 #endif
 215         hard_local_irq_restore(flags);
 216 }
 217
 218 #ifdef CONFIG_SMP
 219 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 220 {
 221         bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
 222 }
 223
 224 static int bfin_internal_set_affinity(struct irq_data *d,
 225                                       const struct cpumask *mask, bool force)
 226 {
 227         bfin_internal_mask_irq(d->irq);
 228         bfin_internal_unmask_irq_affinity(d->irq, mask);
 229
 230         return 0;
 231 }
 232 #else
 233 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 234 {
 235         bfin_internal_unmask_irq(d->irq);
 236 }
 237 #endif
 238
 239 #ifdef CONFIG_PM
 240 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 241 {
 242         u32 bank, bit, wakeup = 0;
 243         unsigned long flags;
 244         bank = SIC_SYSIRQ(irq) / 32;
 245         bit = SIC_SYSIRQ(irq) % 32;
 246
 247         switch (irq) {
 248 #ifdef IRQ_RTC
 249         case IRQ_RTC:
 250         wakeup |= WAKE;
 251         break;
 252 #endif
 253 #ifdef IRQ_CAN0_RX
 254         case IRQ_CAN0_RX:
 255         wakeup |= CANWE;
 256         break;
 257 #endif
 258 #ifdef IRQ_CAN1_RX
 259         case IRQ_CAN1_RX:
 260         wakeup |= CANWE;
 261         break;
 262 #endif
 263 #ifdef IRQ_USB_INT0
 264         case IRQ_USB_INT0:
 265         wakeup |= USBWE;
 266         break;
 267 #endif
 268 #ifdef CONFIG_BF54x
 269         case IRQ_CNT:
 270         wakeup |= ROTWE;
 271         break;
 272 #endif
 273         default:
 274         break;
 275         }
 276
 277         flags = hard_local_irq_save();
 278
 279         if (state) {
 280                 bfin_sic_iwr[bank] |= (1 << bit);
 281                 vr_wakeup  |= wakeup;
 282
 283         } else {
 284                 bfin_sic_iwr[bank] &= ~(1 << bit);
 285                 vr_wakeup  &= ~wakeup;
 286         }
 287
 288         hard_local_irq_restore(flags);
 289
 290         return 0;
 291 }
 292
 293 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 294 {
 295         return bfin_internal_set_wake(d->irq, state);
 296 }
 297 #endif
 298
 299 static struct irq_chip bfin_core_irqchip = {
 300         .name = "CORE",
 301         .irq_ack = bfin_ack_noop,
 302         .irq_mask = bfin_core_mask_irq,
 303         .irq_unmask = bfin_core_unmask_irq,
 304 };
 305
 306 static struct irq_chip bfin_internal_irqchip = {
 307         .name = "INTN",
 308         .irq_ack = bfin_ack_noop,
 309         .irq_mask = bfin_internal_mask_irq_chip,
 310         .irq_unmask = bfin_internal_unmask_irq_chip,
 311         .irq_mask_ack = bfin_internal_mask_irq_chip,
 312         .irq_disable = bfin_internal_mask_irq_chip,
 313         .irq_enable = bfin_internal_unmask_irq_chip,
 314 #ifdef CONFIG_SMP
 315         .irq_set_affinity = bfin_internal_set_affinity,
 316 #endif
 317 #ifdef CONFIG_PM
 318         .irq_set_wake = bfin_internal_set_wake_chip,
 319 #endif
 320 };
 321
 322 static void bfin_handle_irq(unsigned irq)
 323 {
 324 #ifdef CONFIG_IPIPE
 325         struct pt_regs regs;    /* Contents not used. */
 326         ipipe_trace_irq_entry(irq);
 327         __ipipe_handle_irq(irq, &regs);
 328         ipipe_trace_irq_exit(irq);
 329 #else /* !CONFIG_IPIPE */
 330         generic_handle_irq(irq);
 331 #endif  /* !CONFIG_IPIPE */
 332 }
 333
 334 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 335 static int error_int_mask;
 336
 337 static void bfin_generic_error_mask_irq(struct irq_data *d)
 338 {
 339         error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
 340         if (!error_int_mask)
 341                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 342 }
 343
 344 static void bfin_generic_error_unmask_irq(struct irq_data *d)
 345 {
 346         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 347         error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
 348 }
 349
 350 static struct irq_chip bfin_generic_error_irqchip = {
 351         .name = "ERROR",
 352         .irq_ack = bfin_ack_noop,
 353         .irq_mask_ack = bfin_generic_error_mask_irq,
 354         .irq_mask = bfin_generic_error_mask_irq,
 355         .irq_unmask = bfin_generic_error_unmask_irq,
 356 };
 357
 358 static void bfin_demux_error_irq(unsigned int int_err_irq,
 359                                  struct irq_desc *inta_desc)
 360 {
 361         int irq = 0;
 362
 363 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 364         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 365                 irq = IRQ_MAC_ERROR;
 366         else
 367 #endif
 368         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 369                 irq = IRQ_SPORT0_ERROR;
 370         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 371                 irq = IRQ_SPORT1_ERROR;
 372         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 373                 irq = IRQ_PPI_ERROR;
 374         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 375                 irq = IRQ_CAN_ERROR;
 376         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 377                 irq = IRQ_SPI_ERROR;
 378         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 379                 irq = IRQ_UART0_ERROR;
 380         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 381                 irq = IRQ_UART1_ERROR;
 382
 383         if (irq) {
 384                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
 385                         bfin_handle_irq(irq);
 386                 else {
 387
 388                         switch (irq) {
 389                         case IRQ_PPI_ERROR:
 390                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 391                                 break;
 392 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 393                         case IRQ_MAC_ERROR:
 394                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 395                                 break;
 396 #endif
 397                         case IRQ_SPORT0_ERROR:
 398                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 399                                 break;
 400
 401                         case IRQ_SPORT1_ERROR:
 402                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 403                                 break;
 404
 405                         case IRQ_CAN_ERROR:
 406                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 407                                 break;
 408
 409                         case IRQ_SPI_ERROR:
 410                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 411                                 break;
 412
 413                         default:
 414                                 break;
 415                         }
 416
 417                         pr_debug("IRQ %d:"
 418                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 419                                  irq);
 420                 }
 421         } else
 422                 printk(KERN_ERR
 423                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 424                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 425                        __func__, __FILE__, __LINE__);
 426
 427 }
 428 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 429
 430 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 431 static int mac_stat_int_mask;
 432
 433 static void bfin_mac_status_ack_irq(unsigned int irq)
 434 {
 435         switch (irq) {
 436         case IRQ_MAC_MMCINT:
 437                 bfin_write_EMAC_MMC_TIRQS(
 438                         bfin_read_EMAC_MMC_TIRQE() &
 439                         bfin_read_EMAC_MMC_TIRQS());
 440                 bfin_write_EMAC_MMC_RIRQS(
 441                         bfin_read_EMAC_MMC_RIRQE() &
 442                         bfin_read_EMAC_MMC_RIRQS());
 443                 break;
 444         case IRQ_MAC_RXFSINT:
 445                 bfin_write_EMAC_RX_STKY(
 446                         bfin_read_EMAC_RX_IRQE() &
 447                         bfin_read_EMAC_RX_STKY());
 448                 break;
 449         case IRQ_MAC_TXFSINT:
 450                 bfin_write_EMAC_TX_STKY(
 451                         bfin_read_EMAC_TX_IRQE() &
 452                         bfin_read_EMAC_TX_STKY());
 453                 break;
 454         case IRQ_MAC_WAKEDET:
 455                  bfin_write_EMAC_WKUP_CTL(
 456                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 457                 break;
 458         default:
 459                 /* These bits are W1C */
 460                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 461                 break;
 462         }
 463 }
 464
 465 static void bfin_mac_status_mask_irq(struct irq_data *d)
 466 {
 467         unsigned int irq = d->irq;
 468
 469         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 470 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 471         switch (irq) {
 472         case IRQ_MAC_PHYINT:
 473                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 474                 break;
 475         default:
 476                 break;
 477         }
 478 #else
 479         if (!mac_stat_int_mask)
 480                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 481 #endif
 482         bfin_mac_status_ack_irq(irq);
 483 }
 484
 485 static void bfin_mac_status_unmask_irq(struct irq_data *d)
 486 {
 487         unsigned int irq = d->irq;
 488
 489 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 490         switch (irq) {
 491         case IRQ_MAC_PHYINT:
 492                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 493                 break;
 494         default:
 495                 break;
 496         }
 497 #else
 498         if (!mac_stat_int_mask)
 499                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 500 #endif
 501         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 502 }
 503
 504 #ifdef CONFIG_PM
 505 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 506 {
 507 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 508         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 509 #else
 510         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 511 #endif
 512 }
 513 #endif
 514
 515 static struct irq_chip bfin_mac_status_irqchip = {
 516         .name = "MACST",
 517         .irq_ack = bfin_ack_noop,
 518         .irq_mask_ack = bfin_mac_status_mask_irq,
 519         .irq_mask = bfin_mac_status_mask_irq,
 520         .irq_unmask = bfin_mac_status_unmask_irq,
 521 #ifdef CONFIG_PM
 522         .irq_set_wake = bfin_mac_status_set_wake,
 523 #endif
 524 };
 525
 526 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 527                                  struct irq_desc *inta_desc)
 528 {
 529         int i, irq = 0;
 530         u32 status = bfin_read_EMAC_SYSTAT();
 531
 532         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 533                 if (status & (1L << i)) {
 534                         irq = IRQ_MAC_PHYINT + i;
 535                         break;
 536                 }
 537
 538         if (irq) {
 539                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 540                         bfin_handle_irq(irq);
 541                 } else {
 542                         bfin_mac_status_ack_irq(irq);
 543                         pr_debug("IRQ %d:"
 544                                  " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 545                                  irq);
 546                 }
 547         } else
 548                 printk(KERN_ERR
 549                        "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 550                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
 551                        "(EMAC_SYSTAT=0x%X)\n",
 552                        __func__, __FILE__, __LINE__, status);
 553 }
 554 #endif
 555
 556 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 557 {
 558 #ifdef CONFIG_IPIPE
 559         _set_irq_handler(irq, handle_level_irq);
 560 #else
 561         __set_irq_handler_unlocked(irq, handle);
 562 #endif
 563 }
 564
 565 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 566 extern void bfin_gpio_irq_prepare(unsigned gpio);
 567
 568 #if !defined(CONFIG_BF54x)
 569
 570 static void bfin_gpio_ack_irq(unsigned int irq)
 571 {
 572         /* AFAIK ack_irq in case mask_ack is provided
 573          * get's only called for edge sense irqs
 574          */
 575         set_gpio_data(irq_to_gpio(irq), 0);
 576 }
 577
 578 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 579 {
 580         struct irq_desc *desc = irq_to_desc(irq);
 581         u32 gpionr = irq_to_gpio(irq);
 582
 583         if (desc->handle_irq == handle_edge_irq)
 584                 set_gpio_data(gpionr, 0);
 585
 586         set_gpio_maska(gpionr, 0);
 587 }
 588
 589 static void bfin_gpio_mask_irq(unsigned int irq)
 590 {
 591         set_gpio_maska(irq_to_gpio(irq), 0);
 592 }
 593
 594 static void bfin_gpio_unmask_irq(unsigned int irq)
 595 {
 596         set_gpio_maska(irq_to_gpio(irq), 1);
 597 }
 598
 599 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 600 {
 601         u32 gpionr = irq_to_gpio(irq);
 602
 603         if (__test_and_set_bit(gpionr, gpio_enabled))
 604                 bfin_gpio_irq_prepare(gpionr);
 605
 606         bfin_gpio_unmask_irq(irq);
 607
 608         return 0;
 609 }
 610
 611 static void bfin_gpio_irq_shutdown(unsigned int irq)
 612 {
 613         u32 gpionr = irq_to_gpio(irq);
 614
 615         bfin_gpio_mask_irq(irq);
 616         __clear_bit(gpionr, gpio_enabled);
 617         bfin_gpio_irq_free(gpionr);
 618 }
 619
 620 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 621 {
 622         int ret;
 623         char buf[16];
 624         u32 gpionr = irq_to_gpio(irq);
 625
 626         if (type == IRQ_TYPE_PROBE) {
 627                 /* only probe unenabled GPIO interrupt lines */
 628                 if (test_bit(gpionr, gpio_enabled))
 629                         return 0;
 630                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 631         }
 632
 633         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 634                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 635
 636                 snprintf(buf, 16, "gpio-irq%d", irq);
 637                 ret = bfin_gpio_irq_request(gpionr, buf);
 638                 if (ret)
 639                         return ret;
 640
 641                 if (__test_and_set_bit(gpionr, gpio_enabled))
 642                         bfin_gpio_irq_prepare(gpionr);
 643
 644         } else {
 645                 __clear_bit(gpionr, gpio_enabled);
 646                 return 0;
 647         }
 648
 649         set_gpio_inen(gpionr, 0);
 650         set_gpio_dir(gpionr, 0);
 651
 652         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 653             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 654                 set_gpio_both(gpionr, 1);
 655         else
 656                 set_gpio_both(gpionr, 0);
 657
 658         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 659                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 660         else
 661                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 662
 663         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 664                 set_gpio_edge(gpionr, 1);
 665                 set_gpio_inen(gpionr, 1);
 666                 set_gpio_data(gpionr, 0);
 667
 668         } else {
 669                 set_gpio_edge(gpionr, 0);
 670                 set_gpio_inen(gpionr, 1);
 671         }
 672
 673         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 674                 bfin_set_irq_handler(irq, handle_edge_irq);
 675         else
 676                 bfin_set_irq_handler(irq, handle_level_irq);
 677
 678         return 0;
 679 }
 680
 681 #ifdef CONFIG_PM
 682 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 683 {
 684         return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state);
 685 }
 686 #endif
 687
 688 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 689                                 struct irq_desc *desc)
 690 {
 691         unsigned int i, gpio, mask, irq, search = 0;
 692
 693         switch (inta_irq) {
 694 #if defined(CONFIG_BF53x)
 695         case IRQ_PROG_INTA:
 696                 irq = IRQ_PF0;
 697                 search = 1;
 698                 break;
 699 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 700         case IRQ_MAC_RX:
 701                 irq = IRQ_PH0;
 702                 break;
 703 # endif
 704 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 705         case IRQ_PORTF_INTA:
 706                 irq = IRQ_PF0;
 707                 break;
 708 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 709         case IRQ_PORTF_INTA:
 710                 irq = IRQ_PF0;
 711                 break;
 712         case IRQ_PORTG_INTA:
 713                 irq = IRQ_PG0;
 714                 break;
 715         case IRQ_PORTH_INTA:
 716                 irq = IRQ_PH0;
 717                 break;
 718 #elif defined(CONFIG_BF561)
 719         case IRQ_PROG0_INTA:
 720                 irq = IRQ_PF0;
 721                 break;
 722         case IRQ_PROG1_INTA:
 723                 irq = IRQ_PF16;
 724                 break;
 725         case IRQ_PROG2_INTA:
 726                 irq = IRQ_PF32;
 727                 break;
 728 #endif
 729         default:
 730                 BUG();
 731                 return;
 732         }
 733
 734         if (search) {
 735                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 736                         irq += i;
 737
 738                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 739
 740                         while (mask) {
 741                                 if (mask & 1)
 742                                         bfin_handle_irq(irq);
 743                                 irq++;
 744                                 mask >>= 1;
 745                         }
 746                 }
 747         } else {
 748                         gpio = irq_to_gpio(irq);
 749                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 750
 751                         do {
 752                                 if (mask & 1)
 753                                         bfin_handle_irq(irq);
 754                                 irq++;
 755                                 mask >>= 1;
 756                         } while (mask);
 757         }
 758
 759 }
 760
 761 #else                           /* CONFIG_BF54x */
 762
 763 #define NR_PINT_SYS_IRQS        4
 764 #define NR_PINT_BITS            32
 765 #define NR_PINTS                160
 766 #define IRQ_NOT_AVAIL           0xFF
 767
 768 #define PINT_2_BANK(x)          ((x) >> 5)
 769 #define PINT_2_BIT(x)           ((x) & 0x1F)
 770 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 771
 772 static unsigned char irq2pint_lut[NR_PINTS];
 773 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 774
 775 struct pin_int_t {
 776         unsigned int mask_set;
 777         unsigned int mask_clear;
 778         unsigned int request;
 779         unsigned int assign;
 780         unsigned int edge_set;
 781         unsigned int edge_clear;
 782         unsigned int invert_set;
 783         unsigned int invert_clear;
 784         unsigned int pinstate;
 785         unsigned int latch;
 786 };
 787
 788 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 789         (struct pin_int_t *)PINT0_MASK_SET,
 790         (struct pin_int_t *)PINT1_MASK_SET,
 791         (struct pin_int_t *)PINT2_MASK_SET,
 792         (struct pin_int_t *)PINT3_MASK_SET,
 793 };
 794
 795 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 796 {
 797         unsigned int irq_base;
 798
 799         if (bank < 2) {         /*PA-PB */
 800                 irq_base = IRQ_PA0 + bmap * 16;
 801         } else {                /*PC-PJ */
 802                 irq_base = IRQ_PC0 + bmap * 16;
 803         }
 804
 805         return irq_base;
 806 }
 807
 808         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 809 void init_pint_lut(void)
 810 {
 811         u16 bank, bit, irq_base, bit_pos;
 812         u32 pint_assign;
 813         u8 bmap;
 814
 815         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 816
 817         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 818
 819                 pint_assign = pint[bank]->assign;
 820
 821                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 822
 823                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 824
 825                         irq_base = get_irq_base(bank, bmap);
 826
 827                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 828                         bit_pos = bit + bank * NR_PINT_BITS;
 829
 830                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 831                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 832                 }
 833         }
 834 }
 835
 836 static void bfin_gpio_ack_irq(unsigned int irq)
 837 {
 838         struct irq_desc *desc = irq_to_desc(irq);
 839         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 840         u32 pintbit = PINT_BIT(pint_val);
 841         u32 bank = PINT_2_BANK(pint_val);
 842
 843         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 844                 if (pint[bank]->invert_set & pintbit)
 845                         pint[bank]->invert_clear = pintbit;
 846                 else
 847                         pint[bank]->invert_set = pintbit;
 848         }
 849         pint[bank]->request = pintbit;
 850
 851 }
 852
 853 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 854 {
 855         struct irq_desc *desc = irq_to_desc(irq);
 856         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 857         u32 pintbit = PINT_BIT(pint_val);
 858         u32 bank = PINT_2_BANK(pint_val);
 859
 860         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 861                 if (pint[bank]->invert_set & pintbit)
 862                         pint[bank]->invert_clear = pintbit;
 863                 else
 864                         pint[bank]->invert_set = pintbit;
 865         }
 866
 867         pint[bank]->request = pintbit;
 868         pint[bank]->mask_clear = pintbit;
 869 }
 870
 871 static void bfin_gpio_mask_irq(unsigned int irq)
 872 {
 873         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 874
 875         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 876 }
 877
 878 static void bfin_gpio_unmask_irq(unsigned int irq)
 879 {
 880         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 881         u32 pintbit = PINT_BIT(pint_val);
 882         u32 bank = PINT_2_BANK(pint_val);
 883
 884         pint[bank]->mask_set = pintbit;
 885 }
 886
 887 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 888 {
 889         u32 gpionr = irq_to_gpio(irq);
 890         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 891
 892         if (pint_val == IRQ_NOT_AVAIL) {
 893                 printk(KERN_ERR
 894                 "GPIO IRQ %d :Not in PINT Assign table "
 895                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 896                 return -ENODEV;
 897         }
 898
 899         if (__test_and_set_bit(gpionr, gpio_enabled))
 900                 bfin_gpio_irq_prepare(gpionr);
 901
 902         bfin_gpio_unmask_irq(irq);
 903
 904         return 0;
 905 }
 906
 907 static void bfin_gpio_irq_shutdown(unsigned int irq)
 908 {
 909         u32 gpionr = irq_to_gpio(irq);
 910
 911         bfin_gpio_mask_irq(irq);
 912         __clear_bit(gpionr, gpio_enabled);
 913         bfin_gpio_irq_free(gpionr);
 914 }
 915
 916 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 917 {
 918         int ret;
 919         char buf[16];
 920         u32 gpionr = irq_to_gpio(irq);
 921         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 922         u32 pintbit = PINT_BIT(pint_val);
 923         u32 bank = PINT_2_BANK(pint_val);
 924
 925         if (pint_val == IRQ_NOT_AVAIL)
 926                 return -ENODEV;
 927
 928         if (type == IRQ_TYPE_PROBE) {
 929                 /* only probe unenabled GPIO interrupt lines */
 930                 if (test_bit(gpionr, gpio_enabled))
 931                         return 0;
 932                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 933         }
 934
 935         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 936                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 937
 938                 snprintf(buf, 16, "gpio-irq%d", irq);
 939                 ret = bfin_gpio_irq_request(gpionr, buf);
 940                 if (ret)
 941                         return ret;
 942
 943                 if (__test_and_set_bit(gpionr, gpio_enabled))
 944                         bfin_gpio_irq_prepare(gpionr);
 945
 946         } else {
 947                 __clear_bit(gpionr, gpio_enabled);
 948                 return 0;
 949         }
 950
 951         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 952                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 953         else
 954                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 955
 956         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 957             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 958                 if (gpio_get_value(gpionr))
 959                         pint[bank]->invert_set = pintbit;
 960                 else
 961                         pint[bank]->invert_clear = pintbit;
 962         }
 963
 964         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 965                 pint[bank]->edge_set = pintbit;
 966                 bfin_set_irq_handler(irq, handle_edge_irq);
 967         } else {
 968                 pint[bank]->edge_clear = pintbit;
 969                 bfin_set_irq_handler(irq, handle_level_irq);
 970         }
 971
 972         return 0;
 973 }
 974
 975 #ifdef CONFIG_PM
 976 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 977 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 978
 979 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 980 {
 981         u32 pint_irq;
 982         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 983         u32 bank = PINT_2_BANK(pint_val);
 984         u32 pintbit = PINT_BIT(pint_val);
 985
 986         switch (bank) {
 987         case 0:
 988                 pint_irq = IRQ_PINT0;
 989                 break;
 990         case 2:
 991                 pint_irq = IRQ_PINT2;
 992                 break;
 993         case 3:
 994                 pint_irq = IRQ_PINT3;
 995                 break;
 996         case 1:
 997                 pint_irq = IRQ_PINT1;
 998                 break;
 999         default:
1000                 return -EINVAL;
1001         }
1002
1003         bfin_internal_set_wake(pint_irq, state);
1004
1005         if (state)
1006                 pint_wakeup_masks[bank] |= pintbit;
1007         else
1008                 pint_wakeup_masks[bank] &= ~pintbit;
1009
1010         return 0;
1011 }
1012
1013 u32 bfin_pm_setup(void)
1014 {
1015         u32 val, i;
1016
1017         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1018                 val = pint[i]->mask_clear;
1019                 pint_saved_masks[i] = val;
1020                 if (val ^ pint_wakeup_masks[i]) {
1021                         pint[i]->mask_clear = val;
1022                         pint[i]->mask_set = pint_wakeup_masks[i];
1023                 }
1024         }
1025
1026         return 0;
1027 }
1028
1029 void bfin_pm_restore(void)
1030 {
1031         u32 i, val;
1032
1033         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1034                 val = pint_saved_masks[i];
1035                 if (val ^ pint_wakeup_masks[i]) {
1036                         pint[i]->mask_clear = pint[i]->mask_clear;
1037                         pint[i]->mask_set = val;
1038                 }
1039         }
1040 }
1041 #endif
1042
1043 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1044                                 struct irq_desc *desc)
1045 {
1046         u32 bank, pint_val;
1047         u32 request, irq;
1048
1049         switch (inta_irq) {
1050         case IRQ_PINT0:
1051                 bank = 0;
1052                 break;
1053         case IRQ_PINT2:
1054                 bank = 2;
1055                 break;
1056         case IRQ_PINT3:
1057                 bank = 3;
1058                 break;
1059         case IRQ_PINT1:
1060                 bank = 1;
1061                 break;
1062         default:
1063                 return;
1064         }
1065
1066         pint_val = bank * NR_PINT_BITS;
1067
1068         request = pint[bank]->request;
1069
1070         while (request) {
1071                 if (request & 1) {
1072                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1073                         bfin_handle_irq(irq);
1074                 }
1075                 pint_val++;
1076                 request >>= 1;
1077         }
1078
1079 }
1080 #endif
1081
1082 static struct irq_chip bfin_gpio_irqchip = {
1083         .name = "GPIO",
1084         .ack = bfin_gpio_ack_irq,
1085         .mask = bfin_gpio_mask_irq,
1086         .mask_ack = bfin_gpio_mask_ack_irq,
1087         .unmask = bfin_gpio_unmask_irq,
1088         .disable = bfin_gpio_mask_irq,
1089         .enable = bfin_gpio_unmask_irq,
1090         .set_type = bfin_gpio_irq_type,
1091         .startup = bfin_gpio_irq_startup,
1092         .shutdown = bfin_gpio_irq_shutdown,
1093 #ifdef CONFIG_PM
1094         .set_wake = bfin_gpio_set_wake,
1095 #endif
1096 };
1097
1098 void __cpuinit init_exception_vectors(void)
1099 {
1100         /* cannot program in software:
1101          * evt0 - emulation (jtag)
1102          * evt1 - reset
1103          */
1104         bfin_write_EVT2(evt_nmi);
1105         bfin_write_EVT3(trap);
1106         bfin_write_EVT5(evt_ivhw);
1107         bfin_write_EVT6(evt_timer);
1108         bfin_write_EVT7(evt_evt7);
1109         bfin_write_EVT8(evt_evt8);
1110         bfin_write_EVT9(evt_evt9);
1111         bfin_write_EVT10(evt_evt10);
1112         bfin_write_EVT11(evt_evt11);
1113         bfin_write_EVT12(evt_evt12);
1114         bfin_write_EVT13(evt_evt13);
1115         bfin_write_EVT14(evt_evt14);
1116         bfin_write_EVT15(evt_system_call);
1117         CSYNC();
1118 }
1119
1120 /*
1121  * This function should be called during kernel startup to initialize
1122  * the BFin IRQ handling routines.
1123  */
1124
1125 int __init init_arch_irq(void)
1126 {
1127         int irq;
1128         unsigned long ilat = 0;
1129         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1130 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1131         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1132         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1133         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1134 # ifdef CONFIG_BF54x
1135         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1136 # endif
1137 # ifdef CONFIG_SMP
1138         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1139         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1140 # endif
1141 #else
1142         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1143 #endif
1144
1145         local_irq_disable();
1146
1147 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1148         /* Clear EMAC Interrupt Status bits so we can demux it later */
1149         bfin_write_EMAC_SYSTAT(-1);
1150 #endif
1151
1152 #ifdef CONFIG_BF54x
1153 # ifdef CONFIG_PINTx_REASSIGN
1154         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1155         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1156         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1157         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1158 # endif
1159         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1160         init_pint_lut();
1161 #endif
1162
1163         for (irq = 0; irq <= SYS_IRQS; irq++) {
1164                 if (irq <= IRQ_CORETMR)
1165                         set_irq_chip(irq, &bfin_core_irqchip);
1166                 else
1167                         set_irq_chip(irq, &bfin_internal_irqchip);
1168
1169                 switch (irq) {
1170 #if defined(CONFIG_BF53x)
1171                 case IRQ_PROG_INTA:
1172 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1173                 case IRQ_MAC_RX:
1174 # endif
1175 #elif defined(CONFIG_BF54x)
1176                 case IRQ_PINT0:
1177                 case IRQ_PINT1:
1178                 case IRQ_PINT2:
1179                 case IRQ_PINT3:
1180 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1181                 case IRQ_PORTF_INTA:
1182                 case IRQ_PORTG_INTA:
1183                 case IRQ_PORTH_INTA:
1184 #elif defined(CONFIG_BF561)
1185                 case IRQ_PROG0_INTA:
1186                 case IRQ_PROG1_INTA:
1187                 case IRQ_PROG2_INTA:
1188 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1189                 case IRQ_PORTF_INTA:
1190 #endif
1191                         set_irq_chained_handler(irq,
1192                                                 bfin_demux_gpio_irq);
1193                         break;
1194 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1195                 case IRQ_GENERIC_ERROR:
1196                         set_irq_chained_handler(irq, bfin_demux_error_irq);
1197                         break;
1198 #endif
1199 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1200                 case IRQ_MAC_ERROR:
1201                         set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1202                         break;
1203 #endif
1204 #ifdef CONFIG_SMP
1205                 case IRQ_SUPPLE_0:
1206                 case IRQ_SUPPLE_1:
1207                         set_irq_handler(irq, handle_percpu_irq);
1208                         break;
1209 #endif
1210
1211 #ifdef CONFIG_TICKSOURCE_CORETMR
1212                 case IRQ_CORETMR:
1213 # ifdef CONFIG_SMP
1214                         set_irq_handler(irq, handle_percpu_irq);
1215                         break;
1216 # else
1217                         set_irq_handler(irq, handle_simple_irq);
1218                         break;
1219 # endif
1220 #endif
1221
1222 #ifdef CONFIG_TICKSOURCE_GPTMR0
1223                 case IRQ_TIMER0:
1224                         set_irq_handler(irq, handle_simple_irq);
1225                         break;
1226 #endif
1227
1228 #ifdef CONFIG_IPIPE
1229                 default:
1230                         set_irq_handler(irq, handle_level_irq);
1231                         break;
1232 #else /* !CONFIG_IPIPE */
1233                 default:
1234                         set_irq_handler(irq, handle_simple_irq);
1235                         break;
1236 #endif /* !CONFIG_IPIPE */
1237                 }
1238         }
1239
1240 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1241         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1242                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1243                                          handle_level_irq);
1244 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1245         set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1246 #endif
1247 #endif
1248
1249 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1250         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1251                 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1252                                          handle_level_irq);
1253 #endif
1254         /* if configured as edge, then will be changed to do_edge_IRQ */
1255         for (irq = GPIO_IRQ_BASE;
1256                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1257                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1258                                          handle_level_irq);
1259
1260         bfin_write_IMASK(0);
1261         CSYNC();
1262         ilat = bfin_read_ILAT();
1263         CSYNC();
1264         bfin_write_ILAT(ilat);
1265         CSYNC();
1266
1267         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1268         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1269          * local_irq_enable()
1270          */
1271         program_IAR();
1272         /* Therefore it's better to setup IARs before interrupts enabled */
1273         search_IAR();
1274
1275         /* Enable interrupts IVG7-15 */
1276         bfin_irq_flags |= IMASK_IVG15 |
1277             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1278             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1279
1280         /* This implicitly covers ANOMALY_05000171
1281          * Boot-ROM code modifies SICA_IWRx wakeup registers
1282          */
1283 #ifdef SIC_IWR0
1284         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1285 # ifdef SIC_IWR1
1286         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1287          * will screw up the bootrom as it relies on MDMA0/1 waking it
1288          * up from IDLE instructions.  See this report for more info:
1289          * http://blackfin.uclinux.org/gf/tracker/4323
1290          */
1291         if (ANOMALY_05000435)
1292                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1293         else
1294                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1295 # endif
1296 # ifdef SIC_IWR2
1297         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1298 # endif
1299 #else
1300         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1301 #endif
1302
1303         return 0;
1304 }
1305
1306 #ifdef CONFIG_DO_IRQ_L1
1307 __attribute__((l1_text))
1308 #endif
1309 void do_irq(int vec, struct pt_regs *fp)
1310 {
1311         if (vec == EVT_IVTMR_P) {
1312                 vec = IRQ_CORETMR;
1313         } else {
1314                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1315                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1316 #if defined(SIC_ISR0)
1317                 unsigned long sic_status[3];
1318
1319                 if (smp_processor_id()) {
1320 # ifdef SICB_ISR0
1321                         /* This will be optimized out in UP mode. */
1322                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1323                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1324 # endif
1325                 } else {
1326                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1327                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1328                 }
1329 # ifdef SIC_ISR2
1330                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1331 # endif
1332                 for (;; ivg++) {
1333                         if (ivg >= ivg_stop) {
1334                                 atomic_inc(&num_spurious);
1335                                 return;
1336                         }
1337                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1338                                 break;
1339                 }
1340 #else
1341                 unsigned long sic_status;
1342
1343                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1344
1345                 for (;; ivg++) {
1346                         if (ivg >= ivg_stop) {
1347                                 atomic_inc(&num_spurious);
1348                                 return;
1349                         } else if (sic_status & ivg->isrflag)
1350                                 break;
1351                 }
1352 #endif
1353                 vec = ivg->irqno;
1354         }
1355         asm_do_IRQ(vec, fp);
1356 }
1357
1358 #ifdef CONFIG_IPIPE
1359
1360 int __ipipe_get_irq_priority(unsigned irq)
1361 {
1362         int ient, prio;
1363
1364         if (irq <= IRQ_CORETMR)
1365                 return irq;
1366
1367         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1368                 struct ivgx *ivg = ivg_table + ient;
1369                 if (ivg->irqno == irq) {
1370                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1371                                 if (ivg7_13[prio].ifirst <= ivg &&
1372                                     ivg7_13[prio].istop > ivg)
1373                                         return IVG7 + prio;
1374                         }
1375                 }
1376         }
1377
1378         return IVG15;
1379 }
1380
1381 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1382 #ifdef CONFIG_DO_IRQ_L1
1383 __attribute__((l1_text))
1384 #endif
1385 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1386 {
1387         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1388         struct ipipe_domain *this_domain = __ipipe_current_domain;
1389         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1390         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1391         int irq, s;
1392
1393         if (likely(vec == EVT_IVTMR_P))
1394                 irq = IRQ_CORETMR;
1395         else {
1396 #if defined(SIC_ISR0)
1397                 unsigned long sic_status[3];
1398
1399                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1400                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1401 # ifdef SIC_ISR2
1402                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1403 # endif
1404                 for (;; ivg++) {
1405                         if (ivg >= ivg_stop) {
1406                                 atomic_inc(&num_spurious);
1407                                 return 0;
1408                         }
1409                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1410                                 break;
1411                 }
1412 #else
1413                 unsigned long sic_status;
1414
1415                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1416
1417                 for (;; ivg++) {
1418                         if (ivg >= ivg_stop) {
1419                                 atomic_inc(&num_spurious);
1420                                 return 0;
1421                         } else if (sic_status & ivg->isrflag)
1422                                 break;
1423                 }
1424 #endif
1425                 irq = ivg->irqno;
1426         }
1427
1428         if (irq == IRQ_SYSTMR) {
1429 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1430                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1431 #endif
1432                 /* This is basically what we need from the register frame. */
1433                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1434                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1435                 if (this_domain != ipipe_root_domain)
1436                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1437                 else
1438                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1439         }
1440
1441         if (this_domain == ipipe_root_domain) {
1442                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1443                 barrier();
1444         }
1445
1446         ipipe_trace_irq_entry(irq);
1447         __ipipe_handle_irq(irq, regs);
1448         ipipe_trace_irq_exit(irq);
1449
1450         if (this_domain == ipipe_root_domain) {
1451                 set_thread_flag(TIF_IRQ_SYNC);
1452                 if (!s) {
1453                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1454                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1455                 }
1456         }
1457
1458         return 0;
1459 }
1460
1461 #endif /* CONFIG_IPIPE */