arch/blackfin/mach-common/dpmc_modes.S

   1 /*
   2  * Copyright 2004-2008 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #include <linux/linkage.h>
   8 #include <asm/blackfin.h>
   9 #include <mach/irq.h>
  10 #include <asm/dpmc.h>
  11
  12 .section .l1.text
  13
  14 ENTRY(_sleep_mode)
  15         [--SP] = ( R7:0, P5:0 );
  16         [--SP] =  RETS;
  17
  18         call _set_sic_iwr;
  19
  20         P0.H = hi(PLL_CTL);
  21         P0.L = lo(PLL_CTL);
  22         R1 = W[P0](z);
  23         BITSET (R1, 3);
  24         W[P0] = R1.L;
  25
  26         CLI R2;
  27         SSYNC;
  28         IDLE;
  29         STI R2;
  30
  31         call _test_pll_locked;
  32
  33         R0 = IWR_ENABLE(0);
  34         R1 = IWR_DISABLE_ALL;
  35         R2 = IWR_DISABLE_ALL;
  36
  37         call _set_sic_iwr;
  38
  39         P0.H = hi(PLL_CTL);
  40         P0.L = lo(PLL_CTL);
  41         R7 = w[p0](z);
  42         BITCLR (R7, 3);
  43         BITCLR (R7, 5);
  44         w[p0] = R7.L;
  45         IDLE;
  46         call _test_pll_locked;
  47
  48         RETS = [SP++];
  49         ( R7:0, P5:0 ) = [SP++];
  50         RTS;
  51 ENDPROC(_sleep_mode)
  52
  53 ENTRY(_hibernate_mode)
  54         [--SP] = ( R7:0, P5:0 );
  55         [--SP] =  RETS;
  56
  57         R3 = R0;
  58         R0 = IWR_DISABLE_ALL;
  59         R1 = IWR_DISABLE_ALL;
  60         R2 = IWR_DISABLE_ALL;
  61         call _set_sic_iwr;
  62         call _set_dram_srfs;
  63         SSYNC;
  64
  65         P0.H = hi(VR_CTL);
  66         P0.L = lo(VR_CTL);
  67
  68         W[P0] = R3.L;
  69         CLI R2;
  70         IDLE;
  71 .Lforever:
  72         jump .Lforever;
  73 ENDPROC(_hibernate_mode)
  74
  75 ENTRY(_sleep_deeper)
  76         [--SP] = ( R7:0, P5:0 );
  77         [--SP] =  RETS;
  78
  79         CLI R4;
  80
  81         P3 = R0;
  82         P4 = R1;
  83         P5 = R2;
  84
  85         R0 = IWR_ENABLE(0);
  86         R1 = IWR_DISABLE_ALL;
  87         R2 = IWR_DISABLE_ALL;
  88
  89         call _set_sic_iwr;
  90         call _set_dram_srfs;    /* Set SDRAM Self Refresh */
  91
  92         P0.H = hi(PLL_DIV);
  93         P0.L = lo(PLL_DIV);
  94         R6 = W[P0](z);
  95         R0.L = 0xF;
  96         W[P0] = R0.l;           /* Set Max VCO to SCLK divider */
  97
  98         P0.H = hi(PLL_CTL);
  99         P0.L = lo(PLL_CTL);
 100         R5 = W[P0](z);
 101         R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
 102         W[P0] = R0.l;           /* Set Min CLKIN to VCO multiplier */
 103
 104         SSYNC;
 105         IDLE;
 106
 107         call _test_pll_locked;
 108
 109         P0.H = hi(VR_CTL);
 110         P0.L = lo(VR_CTL);
 111         R7 = W[P0](z);
 112         R1 = 0x6;
 113         R1 <<= 16;
 114         R2 = 0x0404(Z);
 115         R1 = R1|R2;
 116
 117         R2 = DEPOSIT(R7, R1);
 118         W[P0] = R2;             /* Set Min Core Voltage */
 119
 120         SSYNC;
 121         IDLE;
 122
 123         call _test_pll_locked;
 124
 125         R0 = P3;
 126         R1 = P4;
 127         R3 = P5;
 128         call _set_sic_iwr;      /* Set Awake from IDLE */
 129
 130         P0.H = hi(PLL_CTL);
 131         P0.L = lo(PLL_CTL);
 132         R0 = W[P0](z);
 133         BITSET (R0, 3);
 134         W[P0] = R0.L;           /* Turn CCLK OFF */
 135         SSYNC;
 136         IDLE;
 137
 138         call _test_pll_locked;
 139
 140         R0 = IWR_ENABLE(0);
 141         R1 = IWR_DISABLE_ALL;
 142         R2 = IWR_DISABLE_ALL;
 143
 144         call _set_sic_iwr;      /* Set Awake from IDLE PLL */
 145
 146         P0.H = hi(VR_CTL);
 147         P0.L = lo(VR_CTL);
 148         W[P0]= R7;
 149
 150         SSYNC;
 151         IDLE;
 152
 153         call _test_pll_locked;
 154
 155         P0.H = hi(PLL_DIV);
 156         P0.L = lo(PLL_DIV);
 157         W[P0]= R6;              /* Restore CCLK and SCLK divider */
 158
 159         P0.H = hi(PLL_CTL);
 160         P0.L = lo(PLL_CTL);
 161         w[p0] = R5;             /* Restore VCO multiplier */
 162         IDLE;
 163         call _test_pll_locked;
 164
 165         call _unset_dram_srfs;  /* SDRAM Self Refresh Off */
 166
 167         STI R4;
 168
 169         RETS = [SP++];
 170         ( R7:0, P5:0 ) = [SP++];
 171         RTS;
 172 ENDPROC(_sleep_deeper)
 173
 174 ENTRY(_set_dram_srfs)
 175         /*  set the dram to self refresh mode */
 176         SSYNC;
 177 #if defined(EBIU_RSTCTL)        /* DDR */
 178         P0.H = hi(EBIU_RSTCTL);
 179         P0.L = lo(EBIU_RSTCTL);
 180         R2 = [P0];
 181         BITSET(R2, 3); /* SRREQ enter self-refresh mode */
 182         [P0] = R2;
 183         SSYNC;
 184 1:
 185         R2 = [P0];
 186         CC = BITTST(R2, 4);
 187         if !CC JUMP 1b;
 188 #else                           /* SDRAM */
 189         P0.L = lo(EBIU_SDGCTL);
 190         P0.H = hi(EBIU_SDGCTL);
 191         R2 = [P0];
 192         BITSET(R2, 24); /* SRFS enter self-refresh mode */
 193         [P0] = R2;
 194         SSYNC;
 195
 196         P0.L = lo(EBIU_SDSTAT);
 197         P0.H = hi(EBIU_SDSTAT);
 198 1:
 199         R2 = w[P0];
 200         SSYNC;
 201         cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
 202         if !cc jump 1b;
 203
 204         P0.L = lo(EBIU_SDGCTL);
 205         P0.H = hi(EBIU_SDGCTL);
 206         R2 = [P0];
 207         BITCLR(R2, 0); /* SCTLE disable CLKOUT */
 208         [P0] = R2;
 209 #endif
 210         RTS;
 211 ENDPROC(_set_dram_srfs)
 212
 213 ENTRY(_unset_dram_srfs)
 214         /*  set the dram out of self refresh mode */
 215 #if defined(EBIU_RSTCTL)        /* DDR */
 216         P0.H = hi(EBIU_RSTCTL);
 217         P0.L = lo(EBIU_RSTCTL);
 218         R2 = [P0];
 219         BITCLR(R2, 3); /* clear SRREQ bit */
 220         [P0] = R2;
 221 #elif defined(EBIU_SDGCTL)      /* SDRAM */
 222
 223         P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
 224         P0.H = hi(EBIU_SDGCTL);
 225         R2 = [P0];
 226         BITSET(R2, 0); /* SCTLE enable CLKOUT */
 227         [P0] = R2
 228         SSYNC;
 229
 230         P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
 231         P0.H = hi(EBIU_SDGCTL);
 232         R2 = [P0];
 233         BITCLR(R2, 24); /* clear SRFS bit */
 234         [P0] = R2
 235 #endif
 236         SSYNC;
 237         RTS;
 238 ENDPROC(_unset_dram_srfs)
 239
 240 ENTRY(_set_sic_iwr)
 241 #ifdef SIC_IWR0
 242         P0.H = hi(SYSMMR_BASE);
 243         P0.L = lo(SYSMMR_BASE);
 244         [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
 245         [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
 246 # ifdef SIC_IWR2
 247         [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
 248 # endif
 249 #else
 250         P0.H = hi(SIC_IWR);
 251         P0.L = lo(SIC_IWR);
 252         [P0] = R0;
 253 #endif
 254
 255         SSYNC;
 256         RTS;
 257 ENDPROC(_set_sic_iwr)
 258
 259 ENTRY(_test_pll_locked)
 260         P0.H = hi(PLL_STAT);
 261         P0.L = lo(PLL_STAT);
 262 1:
 263         R0 = W[P0] (Z);
 264         CC = BITTST(R0,5);
 265         IF !CC JUMP 1b;
 266         RTS;
 267 ENDPROC(_test_pll_locked)
 268
 269 .section .text
 270
 271 ENTRY(_do_hibernate)
 272         [--SP] = ( R7:0, P5:0 );
 273         [--SP] =  RETS;
 274         /* Save System MMRs */
 275         R2 = R0;
 276         P0.H = hi(PLL_CTL);
 277         P0.L = lo(PLL_CTL);
 278
 279 #ifdef SIC_IMASK0
 280         PM_SYS_PUSH(SIC_IMASK0)
 281 #endif
 282 #ifdef SIC_IMASK1
 283         PM_SYS_PUSH(SIC_IMASK1)
 284 #endif
 285 #ifdef SIC_IMASK2
 286         PM_SYS_PUSH(SIC_IMASK2)
 287 #endif
 288 #ifdef SIC_IMASK
 289         PM_SYS_PUSH(SIC_IMASK)
 290 #endif
 291 #ifdef SIC_IAR0
 292         PM_SYS_PUSH(SIC_IAR0)
 293         PM_SYS_PUSH(SIC_IAR1)
 294         PM_SYS_PUSH(SIC_IAR2)
 295 #endif
 296 #ifdef SIC_IAR3
 297         PM_SYS_PUSH(SIC_IAR3)
 298 #endif
 299 #ifdef SIC_IAR4
 300         PM_SYS_PUSH(SIC_IAR4)
 301         PM_SYS_PUSH(SIC_IAR5)
 302         PM_SYS_PUSH(SIC_IAR6)
 303 #endif
 304 #ifdef SIC_IAR7
 305         PM_SYS_PUSH(SIC_IAR7)
 306 #endif
 307 #ifdef SIC_IAR8
 308         PM_SYS_PUSH(SIC_IAR8)
 309         PM_SYS_PUSH(SIC_IAR9)
 310         PM_SYS_PUSH(SIC_IAR10)
 311         PM_SYS_PUSH(SIC_IAR11)
 312 #endif
 313
 314 #ifdef SIC_IWR
 315         PM_SYS_PUSH(SIC_IWR)
 316 #endif
 317 #ifdef SIC_IWR0
 318         PM_SYS_PUSH(SIC_IWR0)
 319 #endif
 320 #ifdef SIC_IWR1
 321         PM_SYS_PUSH(SIC_IWR1)
 322 #endif
 323 #ifdef SIC_IWR2
 324         PM_SYS_PUSH(SIC_IWR2)
 325 #endif
 326
 327 #ifdef PINT0_ASSIGN
 328         PM_SYS_PUSH(PINT0_MASK_SET)
 329         PM_SYS_PUSH(PINT1_MASK_SET)
 330         PM_SYS_PUSH(PINT2_MASK_SET)
 331         PM_SYS_PUSH(PINT3_MASK_SET)
 332         PM_SYS_PUSH(PINT0_ASSIGN)
 333         PM_SYS_PUSH(PINT1_ASSIGN)
 334         PM_SYS_PUSH(PINT2_ASSIGN)
 335         PM_SYS_PUSH(PINT3_ASSIGN)
 336         PM_SYS_PUSH(PINT0_INVERT_SET)
 337         PM_SYS_PUSH(PINT1_INVERT_SET)
 338         PM_SYS_PUSH(PINT2_INVERT_SET)
 339         PM_SYS_PUSH(PINT3_INVERT_SET)
 340         PM_SYS_PUSH(PINT0_EDGE_SET)
 341         PM_SYS_PUSH(PINT1_EDGE_SET)
 342         PM_SYS_PUSH(PINT2_EDGE_SET)
 343         PM_SYS_PUSH(PINT3_EDGE_SET)
 344 #endif
 345
 346         PM_SYS_PUSH(EBIU_AMBCTL0)
 347         PM_SYS_PUSH(EBIU_AMBCTL1)
 348         PM_SYS_PUSH16(EBIU_AMGCTL)
 349
 350 #ifdef EBIU_FCTL
 351         PM_SYS_PUSH(EBIU_MBSCTL)
 352         PM_SYS_PUSH(EBIU_MODE)
 353         PM_SYS_PUSH(EBIU_FCTL)
 354 #endif
 355
 356 #ifdef PORTCIO_FER
 357         PM_SYS_PUSH16(PORTCIO_DIR)
 358         PM_SYS_PUSH16(PORTCIO_INEN)
 359         PM_SYS_PUSH16(PORTCIO)
 360         PM_SYS_PUSH16(PORTCIO_FER)
 361         PM_SYS_PUSH16(PORTDIO_DIR)
 362         PM_SYS_PUSH16(PORTDIO_INEN)
 363         PM_SYS_PUSH16(PORTDIO)
 364         PM_SYS_PUSH16(PORTDIO_FER)
 365         PM_SYS_PUSH16(PORTEIO_DIR)
 366         PM_SYS_PUSH16(PORTEIO_INEN)
 367         PM_SYS_PUSH16(PORTEIO)
 368         PM_SYS_PUSH16(PORTEIO_FER)
 369 #endif
 370
 371         PM_SYS_PUSH16(SYSCR)
 372
 373         /* Save Core MMRs */
 374         P0.H = hi(SRAM_BASE_ADDRESS);
 375         P0.L = lo(SRAM_BASE_ADDRESS);
 376
 377         PM_PUSH(DMEM_CONTROL)
 378         PM_PUSH(DCPLB_ADDR0)
 379         PM_PUSH(DCPLB_ADDR1)
 380         PM_PUSH(DCPLB_ADDR2)
 381         PM_PUSH(DCPLB_ADDR3)
 382         PM_PUSH(DCPLB_ADDR4)
 383         PM_PUSH(DCPLB_ADDR5)
 384         PM_PUSH(DCPLB_ADDR6)
 385         PM_PUSH(DCPLB_ADDR7)
 386         PM_PUSH(DCPLB_ADDR8)
 387         PM_PUSH(DCPLB_ADDR9)
 388         PM_PUSH(DCPLB_ADDR10)
 389         PM_PUSH(DCPLB_ADDR11)
 390         PM_PUSH(DCPLB_ADDR12)
 391         PM_PUSH(DCPLB_ADDR13)
 392         PM_PUSH(DCPLB_ADDR14)
 393         PM_PUSH(DCPLB_ADDR15)
 394         PM_PUSH(DCPLB_DATA0)
 395         PM_PUSH(DCPLB_DATA1)
 396         PM_PUSH(DCPLB_DATA2)
 397         PM_PUSH(DCPLB_DATA3)
 398         PM_PUSH(DCPLB_DATA4)
 399         PM_PUSH(DCPLB_DATA5)
 400         PM_PUSH(DCPLB_DATA6)
 401         PM_PUSH(DCPLB_DATA7)
 402         PM_PUSH(DCPLB_DATA8)
 403         PM_PUSH(DCPLB_DATA9)
 404         PM_PUSH(DCPLB_DATA10)
 405         PM_PUSH(DCPLB_DATA11)
 406         PM_PUSH(DCPLB_DATA12)
 407         PM_PUSH(DCPLB_DATA13)
 408         PM_PUSH(DCPLB_DATA14)
 409         PM_PUSH(DCPLB_DATA15)
 410         PM_PUSH(IMEM_CONTROL)
 411         PM_PUSH(ICPLB_ADDR0)
 412         PM_PUSH(ICPLB_ADDR1)
 413         PM_PUSH(ICPLB_ADDR2)
 414         PM_PUSH(ICPLB_ADDR3)
 415         PM_PUSH(ICPLB_ADDR4)
 416         PM_PUSH(ICPLB_ADDR5)
 417         PM_PUSH(ICPLB_ADDR6)
 418         PM_PUSH(ICPLB_ADDR7)
 419         PM_PUSH(ICPLB_ADDR8)
 420         PM_PUSH(ICPLB_ADDR9)
 421         PM_PUSH(ICPLB_ADDR10)
 422         PM_PUSH(ICPLB_ADDR11)
 423         PM_PUSH(ICPLB_ADDR12)
 424         PM_PUSH(ICPLB_ADDR13)
 425         PM_PUSH(ICPLB_ADDR14)
 426         PM_PUSH(ICPLB_ADDR15)
 427         PM_PUSH(ICPLB_DATA0)
 428         PM_PUSH(ICPLB_DATA1)
 429         PM_PUSH(ICPLB_DATA2)
 430         PM_PUSH(ICPLB_DATA3)
 431         PM_PUSH(ICPLB_DATA4)
 432         PM_PUSH(ICPLB_DATA5)
 433         PM_PUSH(ICPLB_DATA6)
 434         PM_PUSH(ICPLB_DATA7)
 435         PM_PUSH(ICPLB_DATA8)
 436         PM_PUSH(ICPLB_DATA9)
 437         PM_PUSH(ICPLB_DATA10)
 438         PM_PUSH(ICPLB_DATA11)
 439         PM_PUSH(ICPLB_DATA12)
 440         PM_PUSH(ICPLB_DATA13)
 441         PM_PUSH(ICPLB_DATA14)
 442         PM_PUSH(ICPLB_DATA15)
 443         PM_PUSH(EVT0)
 444         PM_PUSH(EVT1)
 445         PM_PUSH(EVT2)
 446         PM_PUSH(EVT3)
 447         PM_PUSH(EVT4)
 448         PM_PUSH(EVT5)
 449         PM_PUSH(EVT6)
 450         PM_PUSH(EVT7)
 451         PM_PUSH(EVT8)
 452         PM_PUSH(EVT9)
 453         PM_PUSH(EVT10)
 454         PM_PUSH(EVT11)
 455         PM_PUSH(EVT12)
 456         PM_PUSH(EVT13)
 457         PM_PUSH(EVT14)
 458         PM_PUSH(EVT15)
 459         PM_PUSH(IMASK)
 460         PM_PUSH(ILAT)
 461         PM_PUSH(IPRIO)
 462         PM_PUSH(TCNTL)
 463         PM_PUSH(TPERIOD)
 464         PM_PUSH(TSCALE)
 465         PM_PUSH(TCOUNT)
 466         PM_PUSH(TBUFCTL)
 467
 468         /* Save Core Registers */
 469         [--sp] = SYSCFG;
 470         [--sp] = ( R7:0, P5:0 );
 471         [--sp] = fp;
 472         [--sp] = usp;
 473
 474         [--sp] = i0;
 475         [--sp] = i1;
 476         [--sp] = i2;
 477         [--sp] = i3;
 478
 479         [--sp] = m0;
 480         [--sp] = m1;
 481         [--sp] = m2;
 482         [--sp] = m3;
 483
 484         [--sp] = l0;
 485         [--sp] = l1;
 486         [--sp] = l2;
 487         [--sp] = l3;
 488
 489         [--sp] = b0;
 490         [--sp] = b1;
 491         [--sp] = b2;
 492         [--sp] = b3;
 493         [--sp] = a0.x;
 494         [--sp] = a0.w;
 495         [--sp] = a1.x;
 496         [--sp] = a1.w;
 497
 498         [--sp] = LC0;
 499         [--sp] = LC1;
 500         [--sp] = LT0;
 501         [--sp] = LT1;
 502         [--sp] = LB0;
 503         [--sp] = LB1;
 504
 505         [--sp] = ASTAT;
 506         [--sp] = CYCLES;
 507         [--sp] = CYCLES2;
 508
 509         [--sp] = RETS;
 510         r0 = RETI;
 511         [--sp] = r0;
 512         [--sp] = RETX;
 513         [--sp] = SEQSTAT;
 514
 515         /* Save Magic, return address and Stack Pointer */
 516         P0.H = 0;
 517         P0.L = 0;
 518         R0.H = 0xDEAD;  /* Hibernate Magic */
 519         R0.L = 0xBEEF;
 520         [P0++] = R0;    /* Store Hibernate Magic */
 521         R0.H = .Lpm_resume_here;
 522         R0.L = .Lpm_resume_here;
 523         [P0++] = R0;    /* Save Return Address */
 524         [P0++] = SP;    /* Save Stack Pointer */
 525         P0.H = _hibernate_mode;
 526         P0.L = _hibernate_mode;
 527         R0 = R2;
 528         call (P0); /* Goodbye */
 529
 530 .Lpm_resume_here:
 531
 532         /* Restore Core Registers */
 533         SEQSTAT = [sp++];
 534         RETX = [sp++];
 535         r0 = [sp++];
 536         RETI = r0;
 537         RETS = [sp++];
 538
 539         CYCLES2 = [sp++];
 540         CYCLES = [sp++];
 541         ASTAT = [sp++];
 542
 543         LB1 = [sp++];
 544         LB0 = [sp++];
 545         LT1 = [sp++];
 546         LT0 = [sp++];
 547         LC1 = [sp++];
 548         LC0 = [sp++];
 549
 550         a1.w = [sp++];
 551         a1.x = [sp++];
 552         a0.w = [sp++];
 553         a0.x = [sp++];
 554         b3 = [sp++];
 555         b2 = [sp++];
 556         b1 = [sp++];
 557         b0 = [sp++];
 558
 559         l3 = [sp++];
 560         l2 = [sp++];
 561         l1 = [sp++];
 562         l0 = [sp++];
 563
 564         m3 = [sp++];
 565         m2 = [sp++];
 566         m1 = [sp++];
 567         m0 = [sp++];
 568
 569         i3 = [sp++];
 570         i2 = [sp++];
 571         i1 = [sp++];
 572         i0 = [sp++];
 573
 574         usp = [sp++];
 575         fp = [sp++];
 576
 577         ( R7 : 0, P5 : 0) = [ SP ++ ];
 578         SYSCFG = [sp++];
 579
 580         /* Restore Core MMRs */
 581
 582         PM_POP(TBUFCTL)
 583         PM_POP(TCOUNT)
 584         PM_POP(TSCALE)
 585         PM_POP(TPERIOD)
 586         PM_POP(TCNTL)
 587         PM_POP(IPRIO)
 588         PM_POP(ILAT)
 589         PM_POP(IMASK)
 590         PM_POP(EVT15)
 591         PM_POP(EVT14)
 592         PM_POP(EVT13)
 593         PM_POP(EVT12)
 594         PM_POP(EVT11)
 595         PM_POP(EVT10)
 596         PM_POP(EVT9)
 597         PM_POP(EVT8)
 598         PM_POP(EVT7)
 599         PM_POP(EVT6)
 600         PM_POP(EVT5)
 601         PM_POP(EVT4)
 602         PM_POP(EVT3)
 603         PM_POP(EVT2)
 604         PM_POP(EVT1)
 605         PM_POP(EVT0)
 606         PM_POP(ICPLB_DATA15)
 607         PM_POP(ICPLB_DATA14)
 608         PM_POP(ICPLB_DATA13)
 609         PM_POP(ICPLB_DATA12)
 610         PM_POP(ICPLB_DATA11)
 611         PM_POP(ICPLB_DATA10)
 612         PM_POP(ICPLB_DATA9)
 613         PM_POP(ICPLB_DATA8)
 614         PM_POP(ICPLB_DATA7)
 615         PM_POP(ICPLB_DATA6)
 616         PM_POP(ICPLB_DATA5)
 617         PM_POP(ICPLB_DATA4)
 618         PM_POP(ICPLB_DATA3)
 619         PM_POP(ICPLB_DATA2)
 620         PM_POP(ICPLB_DATA1)
 621         PM_POP(ICPLB_DATA0)
 622         PM_POP(ICPLB_ADDR15)
 623         PM_POP(ICPLB_ADDR14)
 624         PM_POP(ICPLB_ADDR13)
 625         PM_POP(ICPLB_ADDR12)
 626         PM_POP(ICPLB_ADDR11)
 627         PM_POP(ICPLB_ADDR10)
 628         PM_POP(ICPLB_ADDR9)
 629         PM_POP(ICPLB_ADDR8)
 630         PM_POP(ICPLB_ADDR7)
 631         PM_POP(ICPLB_ADDR6)
 632         PM_POP(ICPLB_ADDR5)
 633         PM_POP(ICPLB_ADDR4)
 634         PM_POP(ICPLB_ADDR3)
 635         PM_POP(ICPLB_ADDR2)
 636         PM_POP(ICPLB_ADDR1)
 637         PM_POP(ICPLB_ADDR0)
 638         PM_POP(IMEM_CONTROL)
 639         PM_POP(DCPLB_DATA15)
 640         PM_POP(DCPLB_DATA14)
 641         PM_POP(DCPLB_DATA13)
 642         PM_POP(DCPLB_DATA12)
 643         PM_POP(DCPLB_DATA11)
 644         PM_POP(DCPLB_DATA10)
 645         PM_POP(DCPLB_DATA9)
 646         PM_POP(DCPLB_DATA8)
 647         PM_POP(DCPLB_DATA7)
 648         PM_POP(DCPLB_DATA6)
 649         PM_POP(DCPLB_DATA5)
 650         PM_POP(DCPLB_DATA4)
 651         PM_POP(DCPLB_DATA3)
 652         PM_POP(DCPLB_DATA2)
 653         PM_POP(DCPLB_DATA1)
 654         PM_POP(DCPLB_DATA0)
 655         PM_POP(DCPLB_ADDR15)
 656         PM_POP(DCPLB_ADDR14)
 657         PM_POP(DCPLB_ADDR13)
 658         PM_POP(DCPLB_ADDR12)
 659         PM_POP(DCPLB_ADDR11)
 660         PM_POP(DCPLB_ADDR10)
 661         PM_POP(DCPLB_ADDR9)
 662         PM_POP(DCPLB_ADDR8)
 663         PM_POP(DCPLB_ADDR7)
 664         PM_POP(DCPLB_ADDR6)
 665         PM_POP(DCPLB_ADDR5)
 666         PM_POP(DCPLB_ADDR4)
 667         PM_POP(DCPLB_ADDR3)
 668         PM_POP(DCPLB_ADDR2)
 669         PM_POP(DCPLB_ADDR1)
 670         PM_POP(DCPLB_ADDR0)
 671         PM_POP(DMEM_CONTROL)
 672
 673         /* Restore System MMRs */
 674
 675         P0.H = hi(PLL_CTL);
 676         P0.L = lo(PLL_CTL);
 677         PM_SYS_POP16(SYSCR)
 678
 679 #ifdef PORTCIO_FER
 680         PM_SYS_POP16(PORTEIO_FER)
 681         PM_SYS_POP16(PORTEIO)
 682         PM_SYS_POP16(PORTEIO_INEN)
 683         PM_SYS_POP16(PORTEIO_DIR)
 684         PM_SYS_POP16(PORTDIO_FER)
 685         PM_SYS_POP16(PORTDIO)
 686         PM_SYS_POP16(PORTDIO_INEN)
 687         PM_SYS_POP16(PORTDIO_DIR)
 688         PM_SYS_POP16(PORTCIO_FER)
 689         PM_SYS_POP16(PORTCIO)
 690         PM_SYS_POP16(PORTCIO_INEN)
 691         PM_SYS_POP16(PORTCIO_DIR)
 692 #endif
 693
 694 #ifdef EBIU_FCTL
 695         PM_SYS_POP(EBIU_FCTL)
 696         PM_SYS_POP(EBIU_MODE)
 697         PM_SYS_POP(EBIU_MBSCTL)
 698 #endif
 699         PM_SYS_POP16(EBIU_AMGCTL)
 700         PM_SYS_POP(EBIU_AMBCTL1)
 701         PM_SYS_POP(EBIU_AMBCTL0)
 702
 703 #ifdef PINT0_ASSIGN
 704         PM_SYS_POP(PINT3_EDGE_SET)
 705         PM_SYS_POP(PINT2_EDGE_SET)
 706         PM_SYS_POP(PINT1_EDGE_SET)
 707         PM_SYS_POP(PINT0_EDGE_SET)
 708         PM_SYS_POP(PINT3_INVERT_SET)
 709         PM_SYS_POP(PINT2_INVERT_SET)
 710         PM_SYS_POP(PINT1_INVERT_SET)
 711         PM_SYS_POP(PINT0_INVERT_SET)
 712         PM_SYS_POP(PINT3_ASSIGN)
 713         PM_SYS_POP(PINT2_ASSIGN)
 714         PM_SYS_POP(PINT1_ASSIGN)
 715         PM_SYS_POP(PINT0_ASSIGN)
 716         PM_SYS_POP(PINT3_MASK_SET)
 717         PM_SYS_POP(PINT2_MASK_SET)
 718         PM_SYS_POP(PINT1_MASK_SET)
 719         PM_SYS_POP(PINT0_MASK_SET)
 720 #endif
 721
 722 #ifdef SIC_IWR2
 723         PM_SYS_POP(SIC_IWR2)
 724 #endif
 725 #ifdef SIC_IWR1
 726         PM_SYS_POP(SIC_IWR1)
 727 #endif
 728 #ifdef SIC_IWR0
 729         PM_SYS_POP(SIC_IWR0)
 730 #endif
 731 #ifdef SIC_IWR
 732         PM_SYS_POP(SIC_IWR)
 733 #endif
 734
 735 #ifdef SIC_IAR8
 736         PM_SYS_POP(SIC_IAR11)
 737         PM_SYS_POP(SIC_IAR10)
 738         PM_SYS_POP(SIC_IAR9)
 739         PM_SYS_POP(SIC_IAR8)
 740 #endif
 741 #ifdef SIC_IAR7
 742         PM_SYS_POP(SIC_IAR7)
 743 #endif
 744 #ifdef SIC_IAR6
 745         PM_SYS_POP(SIC_IAR6)
 746         PM_SYS_POP(SIC_IAR5)
 747         PM_SYS_POP(SIC_IAR4)
 748 #endif
 749 #ifdef SIC_IAR3
 750         PM_SYS_POP(SIC_IAR3)
 751 #endif
 752 #ifdef SIC_IAR0
 753         PM_SYS_POP(SIC_IAR2)
 754         PM_SYS_POP(SIC_IAR1)
 755         PM_SYS_POP(SIC_IAR0)
 756 #endif
 757 #ifdef SIC_IMASK
 758         PM_SYS_POP(SIC_IMASK)
 759 #endif
 760 #ifdef SIC_IMASK2
 761         PM_SYS_POP(SIC_IMASK2)
 762 #endif
 763 #ifdef SIC_IMASK1
 764         PM_SYS_POP(SIC_IMASK1)
 765 #endif
 766 #ifdef SIC_IMASK0
 767         PM_SYS_POP(SIC_IMASK0)
 768 #endif
 769
 770         [--sp] = RETI;  /* Clear Global Interrupt Disable */
 771         SP += 4;
 772
 773         RETS = [SP++];
 774         ( R7:0, P5:0 ) = [SP++];
 775         RTS;
 776 ENDPROC(_do_hibernate)