2 * Copyright 2005-2008 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
10 /* Include all Core registers and bit definitions */
11 #include <asm/def_LPBlackfin.h>
13 /************************************************************************************
14 ** System MMR Register Map
15 *************************************************************************************/
16 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
17 #define PLL_CTL 0xFFC00000 /* PLL Control Register */
18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */
19 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
20 #define PLL_STAT 0xFFC0000C /* PLL Status Register */
21 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
22 #define CHIPID 0xFFC00014 /* Chip ID Register */
24 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
25 #define SWRST 0xFFC00100 /* Software Reset Register */
26 #define SYSCR 0xFFC00104 /* System Configuration Register */
27 #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
28 #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
29 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
30 #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
31 #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
32 #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
33 #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
34 #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
36 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
37 #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
38 #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
39 #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
41 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
42 #define RTC_STAT 0xFFC00300 /* RTC Status Register */
43 #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
44 #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
45 #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
46 #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
47 #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
48 #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
50 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
51 #define UART0_THR 0xFFC00400 /* Transmit Holding register */
52 #define UART0_RBR 0xFFC00400 /* Receive Buffer register */
53 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
54 #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
55 #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
56 #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
57 #define UART0_LCR 0xFFC0040C /* Line Control Register */
58 #define UART0_MCR 0xFFC00410 /* Modem Control Register */
59 #define UART0_LSR 0xFFC00414 /* Line Status Register */
60 #define UART0_MSR 0xFFC00418 /* Modem Status Register */
61 #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
62 #define UART0_GCTL 0xFFC00424 /* Global Control Register */
64 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
65 #define SPI0_REGBASE 0xFFC00500
66 #define SPI_CTL 0xFFC00500 /* SPI Control Register */
67 #define SPI_FLG 0xFFC00504 /* SPI Flag register */
68 #define SPI_STAT 0xFFC00508 /* SPI Status register */
69 #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
70 #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
71 #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
72 #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
74 /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
75 #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
76 #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
77 #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
78 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
80 #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
81 #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
82 #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
83 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
85 #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
86 #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
87 #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
88 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
90 #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
91 #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
92 #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
93 #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
95 #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
96 #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
97 #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
98 #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
100 #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
101 #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
102 #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
103 #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
105 #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
106 #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
107 #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
108 #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
110 #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
111 #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
112 #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
113 #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
115 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
116 #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
117 #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
119 /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
120 #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
121 #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
122 #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
123 #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
124 #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
125 #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
126 #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
127 #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
128 #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
129 #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
130 #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
131 #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
132 #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
133 #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
134 #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
135 #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
136 #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
138 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
139 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
140 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
141 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
142 #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
143 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
144 #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
145 #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
146 #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
147 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
148 #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
149 #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
150 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
151 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
152 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
153 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
154 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
155 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
156 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
157 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
158 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
159 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
160 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
162 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
163 #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
164 #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
165 #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
166 #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
167 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
168 #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
169 #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
170 #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
171 #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
172 #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
173 #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
174 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
175 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
176 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
177 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
178 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
179 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
180 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
181 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
182 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
183 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
184 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
186 /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
187 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
188 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
189 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
190 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
191 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
192 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
193 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
195 /* DMA Traffic Control Registers */
196 #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
197 #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
199 /* Alternate deprecated register names (below) provided for backwards code compatibility */
200 #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
201 #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
203 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
204 #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
205 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
206 #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
207 #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
208 #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
209 #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
210 #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
211 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
212 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
213 #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
214 #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
215 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
216 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
218 #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
219 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
220 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
221 #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
222 #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
223 #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
224 #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
225 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
226 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
227 #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
228 #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
229 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
230 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
232 #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
233 #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
234 #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
235 #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
236 #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
237 #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
238 #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
239 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
240 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
241 #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
242 #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
243 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
244 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
246 #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
247 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
248 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
249 #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
250 #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
251 #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
252 #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
253 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
254 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
255 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
256 #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
257 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
258 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
260 #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
261 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
262 #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
263 #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
264 #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
265 #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
266 #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
267 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
268 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
269 #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
270 #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
271 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
272 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
274 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
275 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
276 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
277 #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
278 #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
279 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
280 #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
281 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
282 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
283 #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
284 #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
285 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
286 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
288 #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
289 #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
290 #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
291 #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
292 #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
293 #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
294 #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
295 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
296 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
297 #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
298 #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
299 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
300 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
302 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
303 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
304 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
305 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
306 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
307 #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
308 #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
309 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
310 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
311 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
312 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
313 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
314 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
316 #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
317 #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
318 #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
319 #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
320 #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
321 #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
322 #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
323 #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
324 #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
325 #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
326 #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
327 #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
328 #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
330 #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
331 #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
332 #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
333 #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
334 #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
335 #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
336 #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
337 #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
338 #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
339 #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
340 #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
341 #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
342 #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
344 #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
345 #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
346 #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
347 #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
348 #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
349 #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
350 #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
351 #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
352 #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
353 #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
354 #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
355 #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
356 #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
358 #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
359 #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
360 #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
361 #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
362 #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
363 #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
364 #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
365 #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
366 #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
367 #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
368 #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
369 #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
370 #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
372 #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
373 #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
374 #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
375 #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
376 #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
377 #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
378 #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
379 #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
380 #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
381 #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
382 #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
383 #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
384 #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
386 #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
387 #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
388 #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
389 #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
390 #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
391 #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
392 #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
393 #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
394 #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
395 #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
396 #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
397 #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
398 #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
400 #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
401 #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
402 #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
403 #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
404 #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
405 #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
406 #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
407 #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
408 #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
409 #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
410 #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
411 #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
412 #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
414 #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
415 #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
416 #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
417 #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
418 #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
419 #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
420 #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
421 #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
422 #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
423 #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
424 #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
425 #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
426 #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
428 /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
429 #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
430 #define PPI_STATUS 0xFFC01004 /* PPI Status Register */
431 #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
432 #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
433 #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
435 /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
436 #define TWI0_REGBASE 0xFFC01400
437 #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
438 #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
439 #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
440 #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
441 #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
442 #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
443 #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
444 #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
445 #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
446 #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
447 #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
448 #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
449 #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
450 #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
451 #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
452 #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
454 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
455 #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
456 #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
457 #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
458 #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
459 #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
460 #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
461 #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
462 #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
463 #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
464 #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
465 #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
466 #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
467 #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
468 #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
469 #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
470 #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
471 #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
473 /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
474 #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
475 #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
476 #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
477 #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
478 #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
479 #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
480 #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
481 #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
482 #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
483 #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
484 #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
485 #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
486 #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
487 #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
488 #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
489 #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
490 #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
492 /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
493 #define UART1_THR 0xFFC02000 /* Transmit Holding register */
494 #define UART1_RBR 0xFFC02000 /* Receive Buffer register */
495 #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
496 #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
497 #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
498 #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
499 #define UART1_LCR 0xFFC0200C /* Line Control Register */
500 #define UART1_MCR 0xFFC02010 /* Modem Control Register */
501 #define UART1_LSR 0xFFC02014 /* Line Status Register */
502 #define UART1_MSR 0xFFC02018 /* Modem Status Register */
503 #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
504 #define UART1_GCTL 0xFFC02024 /* Global Control Register */
506 /* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
507 /* For Mailboxes 0-15 */
508 #define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
509 #define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
510 #define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
511 #define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
512 #define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
513 #define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
514 #define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
515 #define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
516 #define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
517 #define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
518 #define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
519 #define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
520 #define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
522 /* For Mailboxes 16-31 */
523 #define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
524 #define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
525 #define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
526 #define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
527 #define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
528 #define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
529 #define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
530 #define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
531 #define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
532 #define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
533 #define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
534 #define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
535 #define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
537 /* CAN Configuration, Control, and Status Registers */
538 #define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
539 #define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
540 #define CAN_DEBUG 0xFFC02A88 /* Debug Register */
541 #define CAN_STATUS 0xFFC02A8C /* Global Status Register */
542 #define CAN_CEC 0xFFC02A90 /* Error Counter Register */
543 #define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
544 #define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
545 #define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
546 #define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
547 #define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
549 #define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
550 #define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
551 #define CAN_ESR 0xFFC02AB4 /* Error Status Register */
552 #define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
553 #define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
554 #define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
555 #define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
557 /* Mailbox Acceptance Masks */
558 #define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
559 #define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
560 #define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
561 #define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
562 #define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
563 #define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
564 #define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
565 #define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
566 #define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
567 #define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
568 #define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
569 #define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
570 #define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
571 #define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
572 #define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
573 #define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
574 #define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
575 #define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
576 #define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
577 #define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
578 #define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
579 #define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
580 #define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
581 #define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
582 #define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
583 #define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
584 #define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
585 #define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
586 #define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
587 #define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
588 #define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
589 #define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
591 #define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
592 #define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
593 #define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
594 #define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
595 #define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
596 #define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
597 #define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
598 #define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
599 #define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
600 #define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
601 #define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
602 #define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
603 #define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
604 #define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
605 #define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
606 #define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
607 #define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
608 #define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
609 #define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
610 #define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
611 #define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
612 #define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
613 #define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
614 #define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
615 #define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
616 #define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
617 #define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
618 #define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
619 #define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
620 #define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
621 #define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
622 #define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
624 /* CAN Acceptance Mask Macros */
625 #define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
626 #define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
628 /* Mailbox Registers */
629 #define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
630 #define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
631 #define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
632 #define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
633 #define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
634 #define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
635 #define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
636 #define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
638 #define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
639 #define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
640 #define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
641 #define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
642 #define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
643 #define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
644 #define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
645 #define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
647 #define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
648 #define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
649 #define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
650 #define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
651 #define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
652 #define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
653 #define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
654 #define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
656 #define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
657 #define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
658 #define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
659 #define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
660 #define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
661 #define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
662 #define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
663 #define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
665 #define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
666 #define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
667 #define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
668 #define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
669 #define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
670 #define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
671 #define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
672 #define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
674 #define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
675 #define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
676 #define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
677 #define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
678 #define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
679 #define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
680 #define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
681 #define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
683 #define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
684 #define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
685 #define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
686 #define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
687 #define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
688 #define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
689 #define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
690 #define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
692 #define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
693 #define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
694 #define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
695 #define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
696 #define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
697 #define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
698 #define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
699 #define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
701 #define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
702 #define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
703 #define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
704 #define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
705 #define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
706 #define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
707 #define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
708 #define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
710 #define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
711 #define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
712 #define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
713 #define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
714 #define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
715 #define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
716 #define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
717 #define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
719 #define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
720 #define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
721 #define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
722 #define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
723 #define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
724 #define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
725 #define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
726 #define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
728 #define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
729 #define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
730 #define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
731 #define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
732 #define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
733 #define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
734 #define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
735 #define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
737 #define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
738 #define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
739 #define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
740 #define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
741 #define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
742 #define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
743 #define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
744 #define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
746 #define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
747 #define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
748 #define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
749 #define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
750 #define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
751 #define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
752 #define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
753 #define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
755 #define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
756 #define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
757 #define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
758 #define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
759 #define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
760 #define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
761 #define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
762 #define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
764 #define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
765 #define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
766 #define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
767 #define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
768 #define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
769 #define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
770 #define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
771 #define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
773 #define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
774 #define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
775 #define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
776 #define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
777 #define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
778 #define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
779 #define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
780 #define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
782 #define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
783 #define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
784 #define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
785 #define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
786 #define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
787 #define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
788 #define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
789 #define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
791 #define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
792 #define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
793 #define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
794 #define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
795 #define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
796 #define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
797 #define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
798 #define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
800 #define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
801 #define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
802 #define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
803 #define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
804 #define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
805 #define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
806 #define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
807 #define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
809 #define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
810 #define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
811 #define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
812 #define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
813 #define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
814 #define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
815 #define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
816 #define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
818 #define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
819 #define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
820 #define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
821 #define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
822 #define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
823 #define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
824 #define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
825 #define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
827 #define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
828 #define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
829 #define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
830 #define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
831 #define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
832 #define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
833 #define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
834 #define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
836 #define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
837 #define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
838 #define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
839 #define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
840 #define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
841 #define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
842 #define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
843 #define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
845 #define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
846 #define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
847 #define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
848 #define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
849 #define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
850 #define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
851 #define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
852 #define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
854 #define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
855 #define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
856 #define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
857 #define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
858 #define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
859 #define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
860 #define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
861 #define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
863 #define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
864 #define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
865 #define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
866 #define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
867 #define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
868 #define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
869 #define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
870 #define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
872 #define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
873 #define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
874 #define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
875 #define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
876 #define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
877 #define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
878 #define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
879 #define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
881 #define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
882 #define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
883 #define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
884 #define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
885 #define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
886 #define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
887 #define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
888 #define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
890 #define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
891 #define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
892 #define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
893 #define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
894 #define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
895 #define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
896 #define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
897 #define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
899 #define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
900 #define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
901 #define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
902 #define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
903 #define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
904 #define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
905 #define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
906 #define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
908 #define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
909 #define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
910 #define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
911 #define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
912 #define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
913 #define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
914 #define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
915 #define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
917 /* CAN Mailbox Area Macros */
918 #define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
919 #define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
920 #define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
921 #define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
922 #define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
923 #define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
924 #define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
925 #define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
927 /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
928 #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
929 #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
930 #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
931 #define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
933 /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
934 #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
935 #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
936 #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
937 #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
938 #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
939 #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
940 #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
942 #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
943 #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
944 #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
945 #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
946 #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
947 #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
948 #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
950 /***********************************************************************************
951 ** System MMR Register Bits And Macros
953 ** Disclaimer: All macros are intended to make C and Assembly code more readable.
954 ** Use these macros carefully, as any that do left shifts for field
955 ** depositing will result in the lower order bits being destroyed. Any
956 ** macro that shifts left to properly position the bit-field should be
957 ** used as part of an OR to initialize a register and NOT as a dynamic
958 ** modifier UNLESS the lower order bits are saved and ORed back in when
959 ** the macro is used.
960 *************************************************************************************/
963 #define CHIPID_VERSION 0xF0000000
964 #define CHIPID_FAMILY 0x0FFFF000
965 #define CHIPID_MANUFACTURE 0x00000FFE
968 #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
969 #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
970 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
971 #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
972 #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
975 #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
976 #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
978 /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
980 /* SIC_IAR0 Macros */
981 #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
982 #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
983 #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
984 #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
985 #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
986 #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
987 #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
988 #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
990 /* SIC_IAR1 Macros */
991 #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
992 #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
993 #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
994 #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
995 #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
996 #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
997 #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
998 #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
1000 /* SIC_IAR2 Macros */
1001 #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
1002 #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
1003 #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
1004 #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
1005 #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
1006 #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
1007 #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
1008 #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
1010 /* SIC_IAR3 Macros */
1011 #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
1012 #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
1013 #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
1014 #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
1015 #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
1016 #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
1017 #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
1018 #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
1020 /* SIC_IMASK Masks */
1021 #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1022 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1023 #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1024 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1027 #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1028 #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1029 #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1030 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1032 /* ************** UART CONTROLLER MASKS *************************/
1033 /* UARTx_LCR Masks */
1034 #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1035 #define STB 0x04 /* Stop Bits */
1036 #define PEN 0x08 /* Parity Enable */
1037 #define EPS 0x10 /* Even Parity Select */
1038 #define STP 0x20 /* Stick Parity */
1039 #define SB 0x40 /* Set Break */
1040 #define DLAB 0x80 /* Divisor Latch Access */
1042 /* UARTx_MCR Mask */
1043 #define LOOP_ENA 0x10 /* Loopback Mode Enable */
1044 #define LOOP_ENA_P 0x04
1045 /* UARTx_LSR Masks */
1046 #define DR 0x01 /* Data Ready */
1047 #define OE 0x02 /* Overrun Error */
1048 #define PE 0x04 /* Parity Error */
1049 #define FE 0x08 /* Framing Error */
1050 #define BI 0x10 /* Break Interrupt */
1051 #define THRE 0x20 /* THR Empty */
1052 #define TEMT 0x40 /* TSR and UART_THR Empty */
1054 /* UARTx_IER Masks */
1055 #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1056 #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1057 #define ELSI 0x04 /* Enable RX Status Interrupt */
1059 /* UARTx_IIR Masks */
1060 #define NINT 0x01 /* Pending Interrupt */
1061 #define IIR_TX_READY 0x02 /* UART_THR empty */
1062 #define IIR_RX_READY 0x04 /* Receive data ready */
1063 #define IIR_LINE_CHANGE 0x06 /* Receive line status */
1064 #define IIR_STATUS 0x06
1066 /* UARTx_GCTL Masks */
1067 #define UCEN 0x01 /* Enable UARTx Clocks */
1068 #define IREN 0x02 /* Enable IrDA Mode */
1069 #define TPOLC 0x04 /* IrDA TX Polarity Change */
1070 #define RPOLC 0x08 /* IrDA RX Polarity Change */
1071 #define FPE 0x10 /* Force Parity Error On Transmit */
1072 #define FFE 0x20 /* Force Framing Error On Transmit */
1074 /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1076 #define TIMOD 0x0003 /* Transfer Initiate Mode */
1077 #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1078 #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1079 #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1080 #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1081 #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1082 #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1083 #define PSSE 0x0010 /* Slave-Select Input Enable */
1084 #define EMISO 0x0020 /* Enable MISO As Output */
1085 #define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1086 #define LSBF 0x0200 /* LSB First */
1087 #define CPHA 0x0400 /* Clock Phase */
1088 #define CPOL 0x0800 /* Clock Polarity */
1089 #define MSTR 0x1000 /* Master/Slave* */
1090 #define WOM 0x2000 /* Write Open Drain Master */
1091 #define SPE 0x4000 /* SPI Enable */
1094 #define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1095 #define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1096 #define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1097 #define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1098 #define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1099 #define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1100 #define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1101 #define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1102 #define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1103 #define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1104 #define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1105 #define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1106 #define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1107 #define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1109 /* SPI_STAT Masks */
1110 #define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1111 #define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1112 #define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1113 #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1114 #define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1115 #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1116 #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1118 /* **************** GENERAL PURPOSE TIMER MASKS **********************/
1119 /* TIMER_ENABLE Masks */
1120 #define TIMEN0 0x0001 /* Enable Timer 0 */
1121 #define TIMEN1 0x0002 /* Enable Timer 1 */
1122 #define TIMEN2 0x0004 /* Enable Timer 2 */
1123 #define TIMEN3 0x0008 /* Enable Timer 3 */
1124 #define TIMEN4 0x0010 /* Enable Timer 4 */
1125 #define TIMEN5 0x0020 /* Enable Timer 5 */
1126 #define TIMEN6 0x0040 /* Enable Timer 6 */
1127 #define TIMEN7 0x0080 /* Enable Timer 7 */
1129 /* TIMER_DISABLE Masks */
1130 #define TIMDIS0 TIMEN0 /* Disable Timer 0 */
1131 #define TIMDIS1 TIMEN1 /* Disable Timer 1 */
1132 #define TIMDIS2 TIMEN2 /* Disable Timer 2 */
1133 #define TIMDIS3 TIMEN3 /* Disable Timer 3 */
1134 #define TIMDIS4 TIMEN4 /* Disable Timer 4 */
1135 #define TIMDIS5 TIMEN5 /* Disable Timer 5 */
1136 #define TIMDIS6 TIMEN6 /* Disable Timer 6 */
1137 #define TIMDIS7 TIMEN7 /* Disable Timer 7 */
1139 /* TIMER_STATUS Masks */
1140 #define TIMIL0 0x00000001 /* Timer 0 Interrupt */
1141 #define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1142 #define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1143 #define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1144 #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1145 #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1146 #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1147 #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1148 #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1149 #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1150 #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
1151 #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
1152 #define TIMIL4 0x00010000 /* Timer 4 Interrupt */
1153 #define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1154 #define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1155 #define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1156 #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1157 #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1158 #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1159 #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1160 #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1161 #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1162 #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1163 #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1165 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1166 #define TOVL_ERR0 TOVF_ERR0
1167 #define TOVL_ERR1 TOVF_ERR1
1168 #define TOVL_ERR2 TOVF_ERR2
1169 #define TOVL_ERR3 TOVF_ERR3
1170 #define TOVL_ERR4 TOVF_ERR4
1171 #define TOVL_ERR5 TOVF_ERR5
1172 #define TOVL_ERR6 TOVF_ERR6
1173 #define TOVL_ERR7 TOVF_ERR7
1174 /* TIMERx_CONFIG Masks */
1175 #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1176 #define WDTH_CAP 0x0002 /* Width Capture Input Mode */
1177 #define EXT_CLK 0x0003 /* External Clock Mode */
1178 #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
1179 #define PERIOD_CNT 0x0008 /* Period Count */
1180 #define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1181 #define TIN_SEL 0x0020 /* Timer Input Select */
1182 #define OUT_DIS 0x0040 /* Output Pad Disable */
1183 #define CLK_SEL 0x0080 /* Timer Clock Select */
1184 #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1185 #define EMU_RUN 0x0200 /* Emulation Behavior Select */
1186 #define ERR_TYP 0xC000 /* Error Type */
1188 /* ****************** GPIO PORTS F, G, H MASKS ***********************/
1189 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1244 /* ******************* SERIAL PORT MASKS **************************************/
1245 /* SPORTx_TCR1 Masks */
1246 #define TSPEN 0x0001 /* Transmit Enable */
1247 #define ITCLK 0x0002 /* Internal Transmit Clock Select */
1248 #define DTYPE_NORM 0x0004 /* Data Format Normal */
1249 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1250 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1251 #define TLSBIT 0x0010 /* Transmit Bit Order */
1252 #define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1253 #define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1254 #define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1255 #define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1256 #define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1257 #define TCKFE 0x4000 /* Clock Falling Edge Select */
1259 /* SPORTx_TCR2 Masks and Macro */
1260 #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1261 #define TXSE 0x0100 /* TX Secondary Enable */
1262 #define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1263 #define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1265 /* SPORTx_RCR1 Masks */
1266 #define RSPEN 0x0001 /* Receive Enable */
1267 #define IRCLK 0x0002 /* Internal Receive Clock Select */
1268 #define DTYPE_NORM 0x0004 /* Data Format Normal */
1269 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1270 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1271 #define RLSBIT 0x0010 /* Receive Bit Order */
1272 #define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1273 #define RFSR 0x0400 /* Receive Frame Sync Required Select */
1274 #define LRFS 0x1000 /* Low Receive Frame Sync Select */
1275 #define LARFS 0x2000 /* Late Receive Frame Sync Select */
1276 #define RCKFE 0x4000 /* Clock Falling Edge Select */
1278 /* SPORTx_RCR2 Masks */
1279 #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1280 #define RXSE 0x0100 /* RX Secondary Enable */
1281 #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1282 #define RRFST 0x0400 /* Right-First Data Order */
1284 /* SPORTx_STAT Masks */
1285 #define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1286 #define RUVF 0x0002 /* Sticky Receive Underflow Status */
1287 #define ROVF 0x0004 /* Sticky Receive Overflow Status */
1288 #define TXF 0x0008 /* Transmit FIFO Full Status */
1289 #define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1290 #define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1291 #define TXHRE 0x0040 /* Transmit Hold Register Empty */
1293 /* SPORTx_MCMC1 Macros */
1294 #define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1296 /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1297 #define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1299 /* SPORTx_MCMC2 Masks */
1300 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1301 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1302 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1303 #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1304 #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1305 #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1306 #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1307 #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1308 #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1309 #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1310 #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1311 #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1312 #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1313 #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1314 #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1315 #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1316 #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1317 #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1318 #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1319 #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1320 #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1321 #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1322 #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1324 /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1325 /* EBIU_AMGCTL Masks */
1326 #define AMCKEN 0x0001 /* Enable CLKOUT */
1327 #define AMBEN_NONE 0x0000 /* All Banks Disabled */
1328 #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1329 #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1330 #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1331 #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1333 /* EBIU_AMBCTL0 Masks */
1334 #define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1335 #define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1336 #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1337 #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1338 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1339 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1340 #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1341 #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1342 #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1343 #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1344 #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1345 #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1346 #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1347 #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1348 #define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1349 #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1350 #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1351 #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1352 #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1353 #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1354 #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1355 #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1356 #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1357 #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1358 #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1359 #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1360 #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1361 #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1362 #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1363 #define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1364 #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1365 #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1366 #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1367 #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1368 #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1369 #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1370 #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1371 #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1372 #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1373 #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1374 #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1375 #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1376 #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1377 #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1379 #define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1380 #define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1381 #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1382 #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1383 #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1384 #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1385 #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1386 #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1387 #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1388 #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1389 #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1390 #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1391 #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1392 #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1393 #define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1394 #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1395 #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1396 #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1397 #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1398 #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1399 #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1400 #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1401 #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1402 #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1403 #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1404 #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1405 #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1406 #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1407 #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1408 #define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1409 #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1410 #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1411 #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1412 #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1413 #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1414 #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1415 #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1416 #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1417 #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1418 #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1419 #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1420 #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1421 #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1422 #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1424 /* EBIU_AMBCTL1 Masks */
1425 #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1426 #define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1427 #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1428 #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1429 #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1430 #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1431 #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1432 #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1433 #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1434 #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1435 #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1436 #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1437 #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1438 #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1439 #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1440 #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1441 #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1442 #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1443 #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1444 #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1445 #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1446 #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1447 #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1448 #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1449 #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1450 #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1451 #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1452 #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1453 #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1454 #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1455 #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1456 #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1457 #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1458 #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1459 #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1460 #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1461 #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1462 #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1463 #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1464 #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1465 #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1466 #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1467 #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1468 #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1470 #define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1471 #define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1472 #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1473 #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1474 #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1475 #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1476 #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1477 #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1478 #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1479 #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1480 #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1481 #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1482 #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1483 #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1484 #define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1485 #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1486 #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1487 #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1488 #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1489 #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1490 #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1491 #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1492 #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1493 #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1494 #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1495 #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1496 #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1497 #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1498 #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1499 #define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1500 #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1501 #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1502 #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1503 #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1504 #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1505 #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1506 #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1507 #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1508 #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1509 #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1510 #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1511 #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1512 #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1513 #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1515 /* ********************** SDRAM CONTROLLER MASKS **********************************************/
1516 /* EBIU_SDGCTL Masks */
1517 #define SCTLE 0x00000001 /* Enable SDRAM Signals */
1518 #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1519 #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1520 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1521 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1522 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1523 #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1524 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1525 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1526 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1527 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1528 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1529 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1530 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1531 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1532 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1533 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1534 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1535 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1536 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1537 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1538 #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1539 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1540 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1541 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1542 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1543 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1544 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1545 #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1546 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1547 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1548 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1549 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1550 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1551 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1552 #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1553 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1554 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1555 #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1556 #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1557 #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1558 #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1559 #define EBUFE 0x02000000 /* Enable External Buffering Timing */
1560 #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1561 #define EMREN 0x10000000 /* Extended Mode Register Enable */
1562 #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1563 #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1565 /* EBIU_SDBCTL Masks */
1566 #define EBE 0x0001 /* Enable SDRAM External Bank */
1567 #define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1568 #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1569 #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1570 #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1571 #define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1572 #define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1573 #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1574 #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1575 #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1576 #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1578 /* EBIU_SDSTAT Masks */
1579 #define SDCI 0x0001 /* SDRAM Controller Idle */
1580 #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1581 #define SDPUA 0x0004 /* SDRAM Power-Up Active */
1582 #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1583 #define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1584 #define BGSTAT 0x0020 /* Bus Grant Status */
1586 /* ************************** DMA CONTROLLER MASKS ********************************/
1588 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1589 #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1590 #define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1591 #define PMAP_PPI 0x0000 /* PPI Port DMA */
1592 #define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1593 #define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1594 #define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1595 #define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1596 #define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1597 #define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1598 #define PMAP_SPI 0x7000 /* SPI Port DMA */
1599 #define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1600 #define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1601 #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1602 #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1604 /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1605 /* PPI_CONTROL Masks */
1606 #define PORT_EN 0x0001 /* PPI Port Enable */
1607 #define PORT_DIR 0x0002 /* PPI Port Direction */
1608 #define XFR_TYPE 0x000C /* PPI Transfer Type */
1609 #define PORT_CFG 0x0030 /* PPI Port Configuration */
1610 #define FLD_SEL 0x0040 /* PPI Active Field Select */
1611 #define PACK_EN 0x0080 /* PPI Packing Mode */
1612 #define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1613 #define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1614 #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1615 #define DLENGTH 0x3800 /* PPI Data Length */
1616 #define DLEN_8 0x0000 /* Data Length = 8 Bits */
1617 #define DLEN_10 0x0800 /* Data Length = 10 Bits */
1618 #define DLEN_11 0x1000 /* Data Length = 11 Bits */
1619 #define DLEN_12 0x1800 /* Data Length = 12 Bits */
1620 #define DLEN_13 0x2000 /* Data Length = 13 Bits */
1621 #define DLEN_14 0x2800 /* Data Length = 14 Bits */
1622 #define DLEN_15 0x3000 /* Data Length = 15 Bits */
1623 #define DLEN_16 0x3800 /* Data Length = 16 Bits */
1624 #define POLC 0x4000 /* PPI Clock Polarity */
1625 #define POLS 0x8000 /* PPI Frame Sync Polarity */
1627 /* PPI_STATUS Masks */
1628 #define FLD 0x0400 /* Field Indicator */
1629 #define FT_ERR 0x0800 /* Frame Track Error */
1630 #define OVR 0x1000 /* FIFO Overflow Error */
1631 #define UNDR 0x2000 /* FIFO Underrun Error */
1632 #define ERR_DET 0x4000 /* Error Detected Indicator */
1633 #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1635 /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1636 /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1637 #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1638 #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1640 /* TWI_PRESCALE Masks */
1641 #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1642 #define TWI_ENA 0x0080 /* TWI Enable */
1643 #define SCCB 0x0200 /* SCCB Compatibility Enable */
1645 /* TWI_SLAVE_CTRL Masks */
1646 #define SEN 0x0001 /* Slave Enable */
1647 #define SADD_LEN 0x0002 /* Slave Address Length */
1648 #define STDVAL 0x0004 /* Slave Transmit Data Valid */
1649 #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1650 #define GEN 0x0010 /* General Call Adrress Matching Enabled */
1652 /* TWI_SLAVE_STAT Masks */
1653 #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1654 #define GCALL 0x0002 /* General Call Indicator */
1656 /* TWI_MASTER_CTRL Masks */
1657 #define MEN 0x0001 /* Master Mode Enable */
1658 #define MADD_LEN 0x0002 /* Master Address Length */
1659 #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1660 #define FAST 0x0008 /* Use Fast Mode Timing Specs */
1661 #define STOP 0x0010 /* Issue Stop Condition */
1662 #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1663 #define DCNT 0x3FC0 /* Data Bytes To Transfer */
1664 #define SDAOVR 0x4000 /* Serial Data Override */
1665 #define SCLOVR 0x8000 /* Serial Clock Override */
1667 /* TWI_MASTER_STAT Masks */
1668 #define MPROG 0x0001 /* Master Transfer In Progress */
1669 #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1670 #define ANAK 0x0004 /* Address Not Acknowledged */
1671 #define DNAK 0x0008 /* Data Not Acknowledged */
1672 #define BUFRDERR 0x0010 /* Buffer Read Error */
1673 #define BUFWRERR 0x0020 /* Buffer Write Error */
1674 #define SDASEN 0x0040 /* Serial Data Sense */
1675 #define SCLSEN 0x0080 /* Serial Clock Sense */
1676 #define BUSBUSY 0x0100 /* Bus Busy Indicator */
1678 /* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1679 #define SINIT 0x0001 /* Slave Transfer Initiated */
1680 #define SCOMP 0x0002 /* Slave Transfer Complete */
1681 #define SERR 0x0004 /* Slave Transfer Error */
1682 #define SOVF 0x0008 /* Slave Overflow */
1683 #define MCOMP 0x0010 /* Master Transfer Complete */
1684 #define MERR 0x0020 /* Master Transfer Error */
1685 #define XMTSERV 0x0040 /* Transmit FIFO Service */
1686 #define RCVSERV 0x0080 /* Receive FIFO Service */
1688 /* TWI_FIFO_CTRL Masks */
1689 #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1690 #define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1691 #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1692 #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1694 /* TWI_FIFO_STAT Masks */
1695 #define XMTSTAT 0x0003 /* Transmit FIFO Status */
1696 #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1697 #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1698 #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1700 #define RCVSTAT 0x000C /* Receive FIFO Status */
1701 #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1702 #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1703 #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1705 /* ******************* PIN CONTROL REGISTER MASKS ************************/
1706 /* PORT_MUX Masks */
1707 #define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1708 #define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1709 #define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1711 #define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1712 #define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1713 #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1714 #define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1716 #define PFDE 0x0008 /* Port F DMA Request Enable */
1717 #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1718 #define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1720 #define PFTE 0x0010 /* Port F Timer Enable */
1721 #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1722 #define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1724 #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1725 #define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1726 #define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1728 #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1729 #define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1730 #define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1732 #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1733 #define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1734 #define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1736 #define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1737 #define PFFE_TIMER 0x0000 /* Enable TMR2 */
1738 #define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1740 #define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1741 #define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1742 #define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1744 #define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1745 #define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1746 #define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1748 #define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1749 #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1750 #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1752 /* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1753 /* HDMAx_CTL Masks */
1754 #define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1755 #define REP 0x0002 /* HDMA Request Polarity */
1756 #define UTE 0x0004 /* Urgency Threshold Enable */
1757 #define OIE 0x0010 /* Overflow Interrupt Enable */
1758 #define BDIE 0x0020 /* Block Done Interrupt Enable */
1759 #define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1760 #define DRQ 0x0300 /* HDMA Request Type */
1761 #define DRQ_NONE 0x0000 /* No Request */
1762 #define DRQ_SINGLE 0x0100 /* Channels Request Single */
1763 #define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1764 #define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1765 #define RBC 0x1000 /* Reload BCNT With IBCNT */
1766 #define PS 0x2000 /* HDMA Pin Status */
1767 #define OI 0x4000 /* Overflow Interrupt Generated */
1768 #define BDI 0x8000 /* Block Done Interrupt Generated */
1770 /* entry addresses of the user-callable Boot ROM functions */
1772 #define _BOOTROM_RESET 0xEF000000
1773 #define _BOOTROM_FINAL_INIT 0xEF000002
1774 #define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1775 #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1776 #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1777 #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1778 #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1779 #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1780 #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1782 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1783 #define PGDE_UART PFDE_UART
1784 #define PGDE_DMA PFDE_DMA
1785 #define CKELOW SCKELOW
1786 #endif /* _DEF_BF534_H */
git.openpandora.org / pandora-kernel.git / blob