2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Cambridge Signal Processing
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
7 * Licensed under the GPL-2 or later.
10 #include <linux/device.h>
11 #include <linux/platform_device.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/partitions.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/flash.h>
16 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
17 #include <linux/usb/isp1362.h>
19 #include <linux/ata_platform.h>
20 #include <linux/irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/usb/sl811.h>
24 #include <asm/bfin5xx_spi.h>
25 #include <asm/reboot.h>
26 #include <asm/portmux.h>
27 #include <linux/spi/ad7877.h>
30 * Name the Board for the /proc/cpuinfo
32 const char bfin_board_name[] = "CamSig Minotaur BF537";
34 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
35 static struct resource bfin_pcmcia_cf_resources[] = {
37 .start = 0x20310000, /* IO PORT */
39 .flags = IORESOURCE_MEM,
41 .start = 0x20311000, /* Attribute Memory */
43 .flags = IORESOURCE_MEM,
47 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
49 .start = IRQ_PF6, /* Card Detect PF6 */
51 .flags = IORESOURCE_IRQ,
55 static struct platform_device bfin_pcmcia_cf_device = {
56 .name = "bfin_cf_pcmcia",
58 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
59 .resource = bfin_pcmcia_cf_resources,
63 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
64 static struct platform_device rtc_device = {
70 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
71 #include <linux/bfin_mac.h>
72 static const unsigned short bfin_mac_peripherals[] = P_MII0;
74 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
77 .irq = IRQ_MAC_PHYINT,
81 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
83 .phydev_data = bfin_phydev_data,
84 .phy_mode = PHY_INTERFACE_MODE_MII,
85 .mac_peripherals = bfin_mac_peripherals,
88 static struct platform_device bfin_mii_bus = {
89 .name = "bfin_mii_bus",
91 .platform_data = &bfin_mii_bus_data,
95 static struct platform_device bfin_mac_device = {
98 .platform_data = &bfin_mii_bus,
103 #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
104 static struct resource net2272_bfin_resources[] = {
107 .end = 0x20300000 + 0x100,
108 .flags = IORESOURCE_MEM,
112 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
116 static struct platform_device net2272_bfin_device = {
119 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
120 .resource = net2272_bfin_resources,
124 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
125 /* all SPI peripherals info goes here */
127 #if defined(CONFIG_MTD_M25P80) \
128 || defined(CONFIG_MTD_M25P80_MODULE)
130 /* Partition sizes */
131 #define FLASH_SIZE 0x00400000
132 #define PSIZE_UBOOT 0x00030000
133 #define PSIZE_INITRAMFS 0x00240000
135 static struct mtd_partition bfin_spi_flash_partitions[] = {
137 .name = "bootloader(spi)",
140 .mask_flags = MTD_CAP_ROM
142 .name = "initramfs(spi)",
143 .size = PSIZE_INITRAMFS,
144 .offset = PSIZE_UBOOT
147 .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
148 .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
152 static struct flash_platform_data bfin_spi_flash_data = {
154 .parts = bfin_spi_flash_partitions,
155 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
159 /* SPI flash chip (m25p64) */
160 static struct bfin5xx_spi_chip spi_flash_chip_info = {
161 .enable_dma = 0, /* use dma transfer with this chip*/
166 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
167 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
173 static struct spi_board_info bfin_spi_board_info[] __initdata = {
174 #if defined(CONFIG_MTD_M25P80) \
175 || defined(CONFIG_MTD_M25P80_MODULE)
177 /* the modalias must be the same as spi device driver name */
178 .modalias = "m25p80", /* Name of spi_driver for this device */
179 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
180 .bus_num = 0, /* Framework bus number */
181 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
182 .platform_data = &bfin_spi_flash_data,
183 .controller_data = &spi_flash_chip_info,
188 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
190 .modalias = "mmc_spi",
191 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
194 .controller_data = &mmc_spi_chip_info,
200 /* SPI controller data */
201 static struct bfin5xx_spi_master bfin_spi0_info = {
203 .enable_dma = 1, /* master has the ability to do dma transfer */
207 static struct resource bfin_spi0_resource[] = {
209 .start = SPI0_REGBASE,
210 .end = SPI0_REGBASE + 0xFF,
211 .flags = IORESOURCE_MEM,
216 .flags = IORESOURCE_DMA,
221 .flags = IORESOURCE_IRQ,
225 static struct platform_device bfin_spi0_device = {
227 .id = 0, /* Bus number */
228 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
229 .resource = bfin_spi0_resource,
231 .platform_data = &bfin_spi0_info, /* Passed to driver */
234 #endif /* spi master and devices */
236 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
237 #ifdef CONFIG_SERIAL_BFIN_UART0
238 static struct resource bfin_uart0_resources[] = {
242 .flags = IORESOURCE_MEM,
245 .start = IRQ_UART0_RX,
246 .end = IRQ_UART0_RX+1,
247 .flags = IORESOURCE_IRQ,
250 .start = IRQ_UART0_ERROR,
251 .end = IRQ_UART0_ERROR,
252 .flags = IORESOURCE_IRQ,
255 .start = CH_UART0_TX,
257 .flags = IORESOURCE_DMA,
260 .start = CH_UART0_RX,
262 .flags = IORESOURCE_DMA,
266 static unsigned short bfin_uart0_peripherals[] = {
267 P_UART0_TX, P_UART0_RX, 0
270 static struct platform_device bfin_uart0_device = {
273 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
274 .resource = bfin_uart0_resources,
276 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
280 #ifdef CONFIG_SERIAL_BFIN_UART1
281 static struct resource bfin_uart1_resources[] = {
285 .flags = IORESOURCE_MEM,
288 .start = IRQ_UART1_RX,
289 .end = IRQ_UART1_RX+1,
290 .flags = IORESOURCE_IRQ,
293 .start = IRQ_UART1_ERROR,
294 .end = IRQ_UART1_ERROR,
295 .flags = IORESOURCE_IRQ,
298 .start = CH_UART1_TX,
300 .flags = IORESOURCE_DMA,
303 .start = CH_UART1_RX,
305 .flags = IORESOURCE_DMA,
309 static unsigned short bfin_uart1_peripherals[] = {
310 P_UART1_TX, P_UART1_RX, 0
313 static struct platform_device bfin_uart1_device = {
316 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
317 .resource = bfin_uart1_resources,
319 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
325 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
326 #ifdef CONFIG_BFIN_SIR0
327 static struct resource bfin_sir0_resources[] = {
331 .flags = IORESOURCE_MEM,
334 .start = IRQ_UART0_RX,
335 .end = IRQ_UART0_RX+1,
336 .flags = IORESOURCE_IRQ,
339 .start = CH_UART0_RX,
340 .end = CH_UART0_RX+1,
341 .flags = IORESOURCE_DMA,
345 static struct platform_device bfin_sir0_device = {
348 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
349 .resource = bfin_sir0_resources,
352 #ifdef CONFIG_BFIN_SIR1
353 static struct resource bfin_sir1_resources[] = {
357 .flags = IORESOURCE_MEM,
360 .start = IRQ_UART1_RX,
361 .end = IRQ_UART1_RX+1,
362 .flags = IORESOURCE_IRQ,
365 .start = CH_UART1_RX,
366 .end = CH_UART1_RX+1,
367 .flags = IORESOURCE_DMA,
371 static struct platform_device bfin_sir1_device = {
374 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
375 .resource = bfin_sir1_resources,
380 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
381 static struct resource bfin_twi0_resource[] = {
383 .start = TWI0_REGBASE,
384 .end = TWI0_REGBASE + 0xFF,
385 .flags = IORESOURCE_MEM,
390 .flags = IORESOURCE_IRQ,
394 static struct platform_device i2c_bfin_twi_device = {
395 .name = "i2c-bfin-twi",
397 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
398 .resource = bfin_twi0_resource,
402 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
403 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
404 static struct resource bfin_sport0_uart_resources[] = {
406 .start = SPORT0_TCR1,
407 .end = SPORT0_MRCS3+4,
408 .flags = IORESOURCE_MEM,
411 .start = IRQ_SPORT0_RX,
412 .end = IRQ_SPORT0_RX+1,
413 .flags = IORESOURCE_IRQ,
416 .start = IRQ_SPORT0_ERROR,
417 .end = IRQ_SPORT0_ERROR,
418 .flags = IORESOURCE_IRQ,
422 static unsigned short bfin_sport0_peripherals[] = {
423 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
424 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
427 static struct platform_device bfin_sport0_uart_device = {
428 .name = "bfin-sport-uart",
430 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
431 .resource = bfin_sport0_uart_resources,
433 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
437 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
438 static struct resource bfin_sport1_uart_resources[] = {
440 .start = SPORT1_TCR1,
441 .end = SPORT1_MRCS3+4,
442 .flags = IORESOURCE_MEM,
445 .start = IRQ_SPORT1_RX,
446 .end = IRQ_SPORT1_RX+1,
447 .flags = IORESOURCE_IRQ,
450 .start = IRQ_SPORT1_ERROR,
451 .end = IRQ_SPORT1_ERROR,
452 .flags = IORESOURCE_IRQ,
456 static unsigned short bfin_sport1_peripherals[] = {
457 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
458 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
461 static struct platform_device bfin_sport1_uart_device = {
462 .name = "bfin-sport-uart",
464 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
465 .resource = bfin_sport1_uart_resources,
467 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
473 static struct platform_device *minotaur_devices[] __initdata = {
474 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
475 &bfin_pcmcia_cf_device,
478 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
482 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
487 #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
488 &net2272_bfin_device,
491 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
495 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
496 #ifdef CONFIG_SERIAL_BFIN_UART0
499 #ifdef CONFIG_SERIAL_BFIN_UART1
504 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
505 #ifdef CONFIG_BFIN_SIR0
508 #ifdef CONFIG_BFIN_SIR1
513 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
514 &i2c_bfin_twi_device,
517 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
518 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
519 &bfin_sport0_uart_device,
521 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
522 &bfin_sport1_uart_device,
528 static int __init minotaur_init(void)
530 printk(KERN_INFO "%s(): registering device resources\n", __func__);
531 platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
532 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
533 spi_register_board_info(bfin_spi_board_info,
534 ARRAY_SIZE(bfin_spi_board_info));
540 arch_initcall(minotaur_init);
542 static struct platform_device *minotaur_early_devices[] __initdata = {
543 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
544 #ifdef CONFIG_SERIAL_BFIN_UART0
547 #ifdef CONFIG_SERIAL_BFIN_UART1
552 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
553 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
554 &bfin_sport0_uart_device,
556 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
557 &bfin_sport1_uart_device,
562 void __init native_machine_early_platform_add_devices(void)
564 printk(KERN_INFO "register early platform devices\n");
565 early_platform_add_devices(minotaur_early_devices,
566 ARRAY_SIZE(minotaur_early_devices));
569 void native_machine_restart(char *cmd)
571 /* workaround reboot hang when booting from SPI */
572 if ((bfin_read_SYSCR() & 0x7) == 0x3)
573 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);