2 * Based on arm clockevents implementation and old bfin time tick.
4 * Copyright 2008-2009 Analog Devics Inc.
8 * Licensed under the GPL-2
11 #include <linux/module.h>
12 #include <linux/profile.h>
13 #include <linux/interrupt.h>
14 #include <linux/time.h>
15 #include <linux/timex.h>
16 #include <linux/irq.h>
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpufreq.h>
21 #include <asm/blackfin.h>
23 #include <asm/gptimers.h>
25 /* Accelerators for sched_clock()
26 * convert from cycles(64bits) => nanoseconds (64bits)
28 * ns = cycles / (freq / ns_per_sec)
29 * ns = cycles * (ns_per_sec / freq)
30 * ns = cycles * (10^9 / (cpu_khz * 10^3))
31 * ns = cycles * (10^6 / cpu_khz)
33 * Then we use scaling math (suggested by george@mvista.com) to get:
34 * ns = cycles * (10^6 * SC / cpu_khz) / SC
35 * ns = cycles * cyc2ns_scale / SC
37 * And since SC is a constant power of two, we can convert the div
40 * We can use khz divisor instead of mhz to keep a better precision, since
41 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
42 * (mathieu.desnoyers@polymtl.ca)
44 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
47 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
49 static inline unsigned long cyc2ns_scale(unsigned long cpu_khz)
51 return (1000000 << CYC2NS_SCALE_FACTOR) / cpu_khz;
54 static inline unsigned long long cycles_2_ns(cycle_t cyc, unsigned long cyc2ns_scale)
56 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
59 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
61 static unsigned long cycles_cyc2ns_scale;
63 static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
65 return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
68 static struct clocksource bfin_cs_cycles = {
69 .name = "bfin_cs_cycles",
71 .read = bfin_read_cycles,
72 .mask = CLOCKSOURCE_MASK(64),
74 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
77 static inline unsigned long long bfin_cs_cycles_sched_clock(void)
79 return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles), cycles_cyc2ns_scale);
82 static int __init bfin_cs_cycles_init(void)
84 cycles_cyc2ns_scale = cyc2ns_scale(get_cclk() / 1000);
86 bfin_cs_cycles.mult = \
87 clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
89 if (clocksource_register(&bfin_cs_cycles))
90 panic("failed to register clocksource");
95 # define bfin_cs_cycles_init()
98 #ifdef CONFIG_GPTMR0_CLOCKSOURCE
100 unsigned long gptimer0_cyc2ns_scale;
102 void __init setup_gptimer0(void)
104 disable_gptimers(TIMER0bit);
106 set_gptimer_config(TIMER0_id, \
107 TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
108 set_gptimer_period(TIMER0_id, -1);
109 set_gptimer_pwidth(TIMER0_id, -2);
111 enable_gptimers(TIMER0bit);
114 static cycle_t bfin_read_gptimer0(struct clocksource *cs)
116 return bfin_read_TIMER0_COUNTER();
119 static struct clocksource bfin_cs_gptimer0 = {
120 .name = "bfin_cs_gptimer0",
122 .read = bfin_read_gptimer0,
123 .mask = CLOCKSOURCE_MASK(32),
125 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
128 static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
130 return cycles_2_ns(bfin_read_TIMER0_COUNTER(), gptimer0_cyc2ns_scale);
133 static int __init bfin_cs_gptimer0_init(void)
135 gptimer0_cyc2ns_scale = cyc2ns_scale(get_sclk() / 1000);
139 bfin_cs_gptimer0.mult = \
140 clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift);
142 if (clocksource_register(&bfin_cs_gptimer0))
143 panic("failed to register clocksource");
148 # define bfin_cs_gptimer0_init()
152 #if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
153 /* prefer to use cycles since it has higher rating */
154 notrace unsigned long long sched_clock(void)
156 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
157 return bfin_cs_cycles_sched_clock();
159 return bfin_cs_gptimer0_sched_clock();
164 #ifdef CONFIG_CORE_TIMER_IRQ_L1
165 __attribute__((l1_text))
167 irqreturn_t timer_interrupt(int irq, void *dev_id);
169 static int bfin_timer_set_next_event(unsigned long, \
170 struct clock_event_device *);
172 static void bfin_timer_set_mode(enum clock_event_mode, \
173 struct clock_event_device *);
175 static struct clock_event_device clockevent_bfin = {
176 #if defined(CONFIG_TICKSOURCE_GPTMR0)
177 .name = "bfin_gptimer0",
181 .name = "bfin_core_timer",
186 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
187 .set_next_event = bfin_timer_set_next_event,
188 .set_mode = bfin_timer_set_mode,
191 static struct irqaction bfin_timer_irq = {
192 #if defined(CONFIG_TICKSOURCE_GPTMR0)
193 .name = "Blackfin GPTimer0",
195 .name = "Blackfin CoreTimer",
197 .flags = IRQF_DISABLED | IRQF_TIMER | \
198 IRQF_IRQPOLL | IRQF_PERCPU,
199 .handler = timer_interrupt,
200 .dev_id = &clockevent_bfin,
203 #if defined(CONFIG_TICKSOURCE_GPTMR0)
204 static int bfin_timer_set_next_event(unsigned long cycles,
205 struct clock_event_device *evt)
207 disable_gptimers(TIMER0bit);
209 /* it starts counting three SCLK cycles after the TIMENx bit is set */
210 set_gptimer_pwidth(TIMER0_id, cycles - 3);
211 enable_gptimers(TIMER0bit);
215 static void bfin_timer_set_mode(enum clock_event_mode mode,
216 struct clock_event_device *evt)
219 case CLOCK_EVT_MODE_PERIODIC: {
220 set_gptimer_config(TIMER0_id, \
221 TIMER_OUT_DIS | TIMER_IRQ_ENA | \
222 TIMER_PERIOD_CNT | TIMER_MODE_PWM);
223 set_gptimer_period(TIMER0_id, get_sclk() / HZ);
224 set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
225 enable_gptimers(TIMER0bit);
228 case CLOCK_EVT_MODE_ONESHOT:
229 disable_gptimers(TIMER0bit);
230 set_gptimer_config(TIMER0_id, \
231 TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
232 set_gptimer_period(TIMER0_id, 0);
234 case CLOCK_EVT_MODE_UNUSED:
235 case CLOCK_EVT_MODE_SHUTDOWN:
236 disable_gptimers(TIMER0bit);
238 case CLOCK_EVT_MODE_RESUME:
243 static void bfin_timer_ack(void)
245 set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
248 static void __init bfin_timer_init(void)
250 disable_gptimers(TIMER0bit);
253 static unsigned long __init bfin_clockevent_check(void)
255 setup_irq(IRQ_TIMER0, &bfin_timer_irq);
259 #else /* CONFIG_TICKSOURCE_CORETMR */
261 static int bfin_timer_set_next_event(unsigned long cycles,
262 struct clock_event_device *evt)
264 bfin_write_TCNTL(TMPWR);
266 bfin_write_TCOUNT(cycles);
268 bfin_write_TCNTL(TMPWR | TMREN);
272 static void bfin_timer_set_mode(enum clock_event_mode mode,
273 struct clock_event_device *evt)
276 case CLOCK_EVT_MODE_PERIODIC: {
277 unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
278 bfin_write_TCNTL(TMPWR);
280 bfin_write_TSCALE(TIME_SCALE - 1);
281 bfin_write_TPERIOD(tcount);
282 bfin_write_TCOUNT(tcount);
284 bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
287 case CLOCK_EVT_MODE_ONESHOT:
288 bfin_write_TCNTL(TMPWR);
290 bfin_write_TSCALE(TIME_SCALE - 1);
291 bfin_write_TPERIOD(0);
292 bfin_write_TCOUNT(0);
294 case CLOCK_EVT_MODE_UNUSED:
295 case CLOCK_EVT_MODE_SHUTDOWN:
299 case CLOCK_EVT_MODE_RESUME:
304 static void bfin_timer_ack(void)
308 static void __init bfin_timer_init(void)
310 /* power up the timer, but don't enable it just yet */
311 bfin_write_TCNTL(TMPWR);
315 * the TSCALE prescaler counter.
317 bfin_write_TSCALE(TIME_SCALE - 1);
318 bfin_write_TPERIOD(0);
319 bfin_write_TCOUNT(0);
324 static unsigned long __init bfin_clockevent_check(void)
326 setup_irq(IRQ_CORETMR, &bfin_timer_irq);
327 return get_cclk() / TIME_SCALE;
330 void __init setup_core_timer(void)
333 bfin_timer_set_mode(CLOCK_EVT_MODE_PERIODIC, NULL);
335 #endif /* CONFIG_TICKSOURCE_GPTMR0 */
338 * timer_interrupt() needs to keep up the real-time clock,
339 * as well as call the "do_timer()" routine every clocktick
341 irqreturn_t timer_interrupt(int irq, void *dev_id)
343 struct clock_event_device *evt = dev_id;
345 evt->event_handler(evt);
350 static int __init bfin_clockevent_init(void)
352 unsigned long timer_clk;
354 timer_clk = bfin_clockevent_check();
358 clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift);
359 clockevent_bfin.max_delta_ns = clockevent_delta2ns(-1, &clockevent_bfin);
360 clockevent_bfin.min_delta_ns = clockevent_delta2ns(100, &clockevent_bfin);
361 clockevent_bfin.cpumask = cpumask_of(0);
362 clockevents_register_device(&clockevent_bfin);
367 void __init time_init(void)
369 time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
371 #ifdef CONFIG_RTC_DRV_BFIN
372 /* [#2663] hack to filter junk RTC values that would cause
373 * userspace to have to deal with time values greater than
374 * 2^31 seconds (which uClibc cannot cope with yet)
376 if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
377 printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
378 bfin_write_RTC_STAT(0);
382 /* Initialize xtime. From now on, xtime is updated with timer interrupts */
383 xtime.tv_sec = secs_since_1970;
385 set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
387 bfin_cs_cycles_init();
388 bfin_cs_gptimer0_init();
389 bfin_clockevent_init();