2 * Copyright 2004-2010 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
7 #include <linux/delay.h>
8 #include <linux/console.h>
9 #include <linux/bootmem.h>
10 #include <linux/seq_file.h>
11 #include <linux/cpu.h>
13 #include <linux/module.h>
14 #include <linux/tty.h>
15 #include <linux/pfn.h>
17 #ifdef CONFIG_MTD_UCLINUX
18 #include <linux/mtd/map.h>
19 #include <linux/ext2_fs.h>
20 #include <linux/cramfs_fs.h>
21 #include <linux/romfs_fs.h>
25 #include <asm/cacheflush.h>
26 #include <asm/blackfin.h>
27 #include <asm/cplbinit.h>
28 #include <asm/clocks.h>
29 #include <asm/div64.h>
31 #include <asm/fixed_code.h>
32 #include <asm/early_printk.h>
33 #include <asm/irq_handler.h>
40 EXPORT_SYMBOL(_bfin_swrst);
42 unsigned long memory_start, memory_end, physical_mem_end;
43 unsigned long _rambase, _ramstart, _ramend;
44 unsigned long reserved_mem_dcache_on;
45 unsigned long reserved_mem_icache_on;
46 EXPORT_SYMBOL(memory_start);
47 EXPORT_SYMBOL(memory_end);
48 EXPORT_SYMBOL(physical_mem_end);
49 EXPORT_SYMBOL(_ramend);
50 EXPORT_SYMBOL(reserved_mem_dcache_on);
52 #ifdef CONFIG_MTD_UCLINUX
53 extern struct map_info uclinux_ram_map;
54 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
56 EXPORT_SYMBOL(memory_mtd_end);
57 EXPORT_SYMBOL(memory_mtd_start);
58 EXPORT_SYMBOL(mtd_size);
61 char __initdata command_line[COMMAND_LINE_SIZE];
62 struct blackfin_initial_pda __initdata initial_pda;
64 /* boot memmap, for parsing "memmap=" */
65 #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
66 #define BFIN_MEMMAP_RAM 1
67 #define BFIN_MEMMAP_RESERVED 2
68 static struct bfin_memmap {
70 struct bfin_memmap_entry {
71 unsigned long long addr; /* start of memory segment */
72 unsigned long long size;
74 } map[BFIN_MEMMAP_MAX];
75 } bfin_memmap __initdata;
77 /* for memmap sanitization */
78 struct change_member {
79 struct bfin_memmap_entry *pentry; /* pointer to original entry */
80 unsigned long long addr; /* address for this change point */
82 static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
83 static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
84 static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
85 static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
87 DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
89 static int early_init_clkin_hz(char *buf);
91 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
92 void __init generate_cplb_tables(void)
96 generate_cplb_tables_all();
97 /* Generate per-CPU I&D CPLB tables */
98 for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
99 generate_cplb_tables_cpu(cpu);
103 void __cpuinit bfin_setup_caches(unsigned int cpu)
105 #ifdef CONFIG_BFIN_ICACHE
106 bfin_icache_init(icplb_tbl[cpu]);
109 #ifdef CONFIG_BFIN_DCACHE
110 bfin_dcache_init(dcplb_tbl[cpu]);
113 bfin_setup_cpudata(cpu);
116 * In cache coherence emulation mode, we need to have the
117 * D-cache enabled before running any atomic operation which
118 * might involve cache invalidation (i.e. spinlock, rwlock).
119 * So printk's are deferred until then.
121 #ifdef CONFIG_BFIN_ICACHE
122 printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
123 printk(KERN_INFO " External memory:"
124 # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
129 " in instruction cache\n");
131 printk(KERN_INFO " L2 SRAM :"
132 # ifdef CONFIG_BFIN_L2_ICACHEABLE
137 " in instruction cache\n");
140 printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
143 #ifdef CONFIG_BFIN_DCACHE
144 printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
145 printk(KERN_INFO " External memory:"
146 # if defined CONFIG_BFIN_EXTMEM_WRITEBACK
147 " cacheable (write-back)"
148 # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
149 " cacheable (write-through)"
155 printk(KERN_INFO " L2 SRAM :"
156 # if defined CONFIG_BFIN_L2_WRITEBACK
157 " cacheable (write-back)"
158 # elif defined CONFIG_BFIN_L2_WRITETHROUGH
159 " cacheable (write-through)"
165 printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
169 void __cpuinit bfin_setup_cpudata(unsigned int cpu)
171 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
173 cpudata->imemctl = bfin_read_IMEM_CONTROL();
174 cpudata->dmemctl = bfin_read_DMEM_CONTROL();
177 void __init bfin_cache_init(void)
179 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
180 generate_cplb_tables();
182 bfin_setup_caches(0);
185 void __init bfin_relocate_l1_mem(void)
187 unsigned long text_l1_len = (unsigned long)_text_l1_len;
188 unsigned long data_l1_len = (unsigned long)_data_l1_len;
189 unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
190 unsigned long l2_len = (unsigned long)_l2_len;
192 early_shadow_stamp();
195 * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
196 * we know that everything about l1 text/data is nice and aligned,
197 * so copy by 4 byte chunks, and don't worry about overlapping
200 * We can't use the dma_memcpy functions, since they can call
201 * scheduler functions which might be in L1 :( and core writes
202 * into L1 instruction cause bad access errors, so we are stuck,
203 * we are required to use DMA, but can't use the common dma
204 * functions. We can't use memcpy either - since that might be
205 * going to be in the relocated L1
208 blackfin_dma_early_init();
210 /* if necessary, copy L1 text to L1 instruction SRAM */
211 if (L1_CODE_LENGTH && text_l1_len)
212 early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
214 /* if necessary, copy L1 data to L1 data bank A SRAM */
215 if (L1_DATA_A_LENGTH && data_l1_len)
216 early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
218 /* if necessary, copy L1 data B to L1 data bank B SRAM */
219 if (L1_DATA_B_LENGTH && data_b_l1_len)
220 early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
222 early_dma_memcpy_done();
224 #if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
225 blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
228 /* if necessary, copy L2 text/data to L2 SRAM */
229 if (L2_LENGTH && l2_len)
230 memcpy(_stext_l2, _l2_lma, l2_len);
234 void __init bfin_relocate_coreb_l1_mem(void)
236 unsigned long text_l1_len = (unsigned long)_text_l1_len;
237 unsigned long data_l1_len = (unsigned long)_data_l1_len;
238 unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
240 blackfin_dma_early_init();
242 /* if necessary, copy L1 text to L1 instruction SRAM */
243 if (L1_CODE_LENGTH && text_l1_len)
244 early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
247 /* if necessary, copy L1 data to L1 data bank A SRAM */
248 if (L1_DATA_A_LENGTH && data_l1_len)
249 early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
252 /* if necessary, copy L1 data B to L1 data bank B SRAM */
253 if (L1_DATA_B_LENGTH && data_b_l1_len)
254 early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
257 early_dma_memcpy_done();
259 #ifdef CONFIG_ICACHE_FLUSH_L1
260 blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
261 (unsigned long)_stext_l1 + COREB_L1_CODE_START;
266 #ifdef CONFIG_ROMKERNEL
267 void __init bfin_relocate_xip_data(void)
269 early_shadow_stamp();
271 memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info));
272 memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len);
276 /* add_memory_region to memmap */
277 static void __init add_memory_region(unsigned long long start,
278 unsigned long long size, int type)
282 i = bfin_memmap.nr_map;
284 if (i == BFIN_MEMMAP_MAX) {
285 printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
289 bfin_memmap.map[i].addr = start;
290 bfin_memmap.map[i].size = size;
291 bfin_memmap.map[i].type = type;
292 bfin_memmap.nr_map++;
296 * Sanitize the boot memmap, removing overlaps.
298 static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
300 struct change_member *change_tmp;
301 unsigned long current_type, last_type;
302 unsigned long long last_addr;
303 int chgidx, still_changing;
306 int old_nr, new_nr, chg_nr;
310 Visually we're performing the following (1,2,3,4 = memory types)
312 Sample memory map (w/overlaps):
313 ____22__________________
314 ______________________4_
315 ____1111________________
316 _44_____________________
317 11111111________________
318 ____________________33__
319 ___________44___________
320 __________33333_________
321 ______________22________
322 ___________________2222_
323 _________111111111______
324 _____________________11_
325 _________________4______
327 Sanitized equivalent (no overlap):
328 1_______________________
329 _44_____________________
330 ___1____________________
331 ____22__________________
332 ______11________________
333 _________1______________
334 __________3_____________
335 ___________44___________
336 _____________33_________
337 _______________2________
338 ________________1_______
339 _________________4______
340 ___________________2____
341 ____________________33__
342 ______________________4_
344 /* if there's only one memory region, don't bother */
350 /* bail out if we find any unreasonable addresses in memmap */
351 for (i = 0; i < old_nr; i++)
352 if (map[i].addr + map[i].size < map[i].addr)
355 /* create pointers for initial change-point information (for sorting) */
356 for (i = 0; i < 2*old_nr; i++)
357 change_point[i] = &change_point_list[i];
359 /* record all known change-points (starting and ending addresses),
360 omitting those that are for empty memory regions */
362 for (i = 0; i < old_nr; i++) {
363 if (map[i].size != 0) {
364 change_point[chgidx]->addr = map[i].addr;
365 change_point[chgidx++]->pentry = &map[i];
366 change_point[chgidx]->addr = map[i].addr + map[i].size;
367 change_point[chgidx++]->pentry = &map[i];
370 chg_nr = chgidx; /* true number of change-points */
372 /* sort change-point list by memory addresses (low -> high) */
374 while (still_changing) {
376 for (i = 1; i < chg_nr; i++) {
377 /* if <current_addr> > <last_addr>, swap */
378 /* or, if current=<start_addr> & last=<end_addr>, swap */
379 if ((change_point[i]->addr < change_point[i-1]->addr) ||
380 ((change_point[i]->addr == change_point[i-1]->addr) &&
381 (change_point[i]->addr == change_point[i]->pentry->addr) &&
382 (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
384 change_tmp = change_point[i];
385 change_point[i] = change_point[i-1];
386 change_point[i-1] = change_tmp;
392 /* create a new memmap, removing overlaps */
393 overlap_entries = 0; /* number of entries in the overlap table */
394 new_entry = 0; /* index for creating new memmap entries */
395 last_type = 0; /* start with undefined memory type */
396 last_addr = 0; /* start with 0 as last starting address */
397 /* loop through change-points, determining affect on the new memmap */
398 for (chgidx = 0; chgidx < chg_nr; chgidx++) {
399 /* keep track of all overlapping memmap entries */
400 if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
401 /* add map entry to overlap list (> 1 entry implies an overlap) */
402 overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
404 /* remove entry from list (order independent, so swap with last) */
405 for (i = 0; i < overlap_entries; i++) {
406 if (overlap_list[i] == change_point[chgidx]->pentry)
407 overlap_list[i] = overlap_list[overlap_entries-1];
411 /* if there are overlapping entries, decide which "type" to use */
412 /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
414 for (i = 0; i < overlap_entries; i++)
415 if (overlap_list[i]->type > current_type)
416 current_type = overlap_list[i]->type;
417 /* continue building up new memmap based on this information */
418 if (current_type != last_type) {
419 if (last_type != 0) {
420 new_map[new_entry].size =
421 change_point[chgidx]->addr - last_addr;
422 /* move forward only if the new size was non-zero */
423 if (new_map[new_entry].size != 0)
424 if (++new_entry >= BFIN_MEMMAP_MAX)
425 break; /* no more space left for new entries */
427 if (current_type != 0) {
428 new_map[new_entry].addr = change_point[chgidx]->addr;
429 new_map[new_entry].type = current_type;
430 last_addr = change_point[chgidx]->addr;
432 last_type = current_type;
435 new_nr = new_entry; /* retain count for new entries */
437 /* copy new mapping into original location */
438 memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
444 static void __init print_memory_map(char *who)
448 for (i = 0; i < bfin_memmap.nr_map; i++) {
449 printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
450 bfin_memmap.map[i].addr,
451 bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
452 switch (bfin_memmap.map[i].type) {
453 case BFIN_MEMMAP_RAM:
454 printk(KERN_CONT "(usable)\n");
456 case BFIN_MEMMAP_RESERVED:
457 printk(KERN_CONT "(reserved)\n");
460 printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
466 static __init int parse_memmap(char *arg)
468 unsigned long long start_at, mem_size;
473 mem_size = memparse(arg, &arg);
475 start_at = memparse(arg+1, &arg);
476 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
477 } else if (*arg == '$') {
478 start_at = memparse(arg+1, &arg);
479 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
486 * Initial parsing of the command line. Currently, we support:
487 * - Controlling the linux memory size: mem=xxx[KMG]
488 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
489 * $ -> reserved memory is dcacheable
490 * # -> reserved memory is icacheable
491 * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
492 * @ from <start> to <start>+<mem>, type RAM
493 * $ from <start> to <start>+<mem>, type RESERVED
495 static __init void parse_cmdline_early(char *cmdline_p)
497 char c = ' ', *to = cmdline_p;
498 unsigned int memsize;
501 if (!memcmp(to, "mem=", 4)) {
503 memsize = memparse(to, &to);
507 } else if (!memcmp(to, "max_mem=", 8)) {
509 memsize = memparse(to, &to);
511 physical_mem_end = memsize;
515 reserved_mem_dcache_on = 1;
518 reserved_mem_icache_on = 1;
521 } else if (!memcmp(to, "clkin_hz=", 9)) {
523 early_init_clkin_hz(to);
524 #ifdef CONFIG_EARLY_PRINTK
525 } else if (!memcmp(to, "earlyprintk=", 12)) {
527 setup_early_printk(to);
529 } else if (!memcmp(to, "memmap=", 7)) {
541 * Setup memory defaults from user config.
542 * The physical memory layout looks like:
544 * [_rambase, _ramstart]: kernel image
545 * [memory_start, memory_end]: dynamic memory managed by kernel
546 * [memory_end, _ramend]: reserved memory
547 * [memory_mtd_start(memory_end),
548 * memory_mtd_start + mtd_size]: rootfs (if any)
549 * [_ramend - DMA_UNCACHED_REGION,
550 * _ramend]: uncached DMA region
551 * [_ramend, physical_mem_end]: memory not managed by kernel
553 static __init void memory_setup(void)
555 #ifdef CONFIG_MTD_UCLINUX
556 unsigned long mtd_phys = 0;
558 unsigned long max_mem;
560 _rambase = CONFIG_BOOT_LOAD;
561 _ramstart = (unsigned long)_end;
563 if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
565 panic("DMA region exceeds memory limit: %lu.",
566 _ramend - _ramstart);
568 max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
570 #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
571 /* Due to a Hardware Anomaly we need to limit the size of usable
572 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
573 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
575 # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
576 if (max_mem >= 56 * 1024 * 1024)
577 max_mem = 56 * 1024 * 1024;
579 if (max_mem >= 60 * 1024 * 1024)
580 max_mem = 60 * 1024 * 1024;
581 # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
582 #endif /* ANOMALY_05000263 */
586 /* Round up to multiple of 4MB */
587 memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
589 memory_start = PAGE_ALIGN(_ramstart);
592 #if defined(CONFIG_MTD_UCLINUX)
593 /* generic memory mapped MTD driver */
594 memory_mtd_end = memory_end;
596 mtd_phys = _ramstart;
597 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
599 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
600 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
602 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
605 # if defined(CONFIG_CRAMFS)
606 if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
607 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
610 # if defined(CONFIG_ROMFS_FS)
611 if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
612 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
614 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
616 /* ROM_FS is XIP, so if we found it, we need to limit memory */
617 if (memory_end > max_mem) {
618 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
619 (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
620 memory_end = max_mem;
623 # endif /* CONFIG_ROMFS_FS */
625 /* Since the default MTD_UCLINUX has no magic number, we just blindly
626 * read 8 past the end of the kernel's image, and look at it.
627 * When no image is attached, mtd_size is set to a random number
628 * Do some basic sanity checks before operating on things
630 if (mtd_size == 0 || memory_end <= mtd_size) {
631 pr_emerg("Could not find valid ram mtd attached.\n");
633 memory_end -= mtd_size;
635 /* Relocate MTD image to the top of memory after the uncached memory area */
636 uclinux_ram_map.phys = memory_mtd_start = memory_end;
637 uclinux_ram_map.size = mtd_size;
638 pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
639 _end, mtd_size, (void *)memory_mtd_start);
640 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
642 #endif /* CONFIG_MTD_UCLINUX */
644 /* We need lo limit memory, since everything could have a text section
645 * of userspace in it, and expose anomaly 05000263. If the anomaly
646 * doesn't exist, or we don't need to - then dont.
648 if (memory_end > max_mem) {
649 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
650 (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
651 memory_end = max_mem;
655 #if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
656 page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
657 ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
659 page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
661 page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
664 init_mm.start_code = (unsigned long)_stext;
665 init_mm.end_code = (unsigned long)_etext;
666 init_mm.end_data = (unsigned long)_edata;
667 init_mm.brk = (unsigned long)0;
669 printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
670 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
672 printk(KERN_INFO "Memory map:\n"
673 " fixedcode = 0x%p-0x%p\n"
674 " text = 0x%p-0x%p\n"
675 " rodata = 0x%p-0x%p\n"
677 " data = 0x%p-0x%p\n"
678 " stack = 0x%p-0x%p\n"
679 " init = 0x%p-0x%p\n"
680 " available = 0x%p-0x%p\n"
681 #ifdef CONFIG_MTD_UCLINUX
682 " rootfs = 0x%p-0x%p\n"
684 #if DMA_UNCACHED_REGION > 0
685 " DMA Zone = 0x%p-0x%p\n"
687 , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
689 __start_rodata, __end_rodata,
690 __bss_start, __bss_stop,
692 (void *)&init_thread_union,
693 (void *)((int)(&init_thread_union) + THREAD_SIZE),
694 __init_begin, __init_end,
695 (void *)_ramstart, (void *)memory_end
696 #ifdef CONFIG_MTD_UCLINUX
697 , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
699 #if DMA_UNCACHED_REGION > 0
700 , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
706 * Find the lowest, highest page frame number we have available
708 void __init find_min_max_pfn(void)
713 min_low_pfn = PFN_DOWN(memory_end);
715 for (i = 0; i < bfin_memmap.nr_map; i++) {
716 unsigned long start, end;
718 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
720 start = PFN_UP(bfin_memmap.map[i].addr);
721 end = PFN_DOWN(bfin_memmap.map[i].addr +
722 bfin_memmap.map[i].size);
727 if (start < min_low_pfn)
732 static __init void setup_bootmem_allocator(void)
736 unsigned long start_pfn, end_pfn;
737 unsigned long curr_pfn, last_pfn, size;
739 /* mark memory between memory_start and memory_end usable */
740 add_memory_region(memory_start,
741 memory_end - memory_start, BFIN_MEMMAP_RAM);
742 /* sanity check for overlap */
743 sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
744 print_memory_map("boot memmap");
746 /* initialize globals in linux/bootmem.h */
748 /* pfn of the last usable page frame */
749 if (max_pfn > memory_end >> PAGE_SHIFT)
750 max_pfn = memory_end >> PAGE_SHIFT;
751 /* pfn of last page frame directly mapped by kernel */
752 max_low_pfn = max_pfn;
753 /* pfn of the first usable page frame after kernel image*/
754 if (min_low_pfn < memory_start >> PAGE_SHIFT)
755 min_low_pfn = memory_start >> PAGE_SHIFT;
756 start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
757 end_pfn = memory_end >> PAGE_SHIFT;
760 * give all the memory to the bootmap allocator, tell it to put the
761 * boot mem_map at the start of memory.
763 bootmap_size = init_bootmem_node(NODE_DATA(0),
764 memory_start >> PAGE_SHIFT, /* map goes here */
767 /* register the memmap regions with the bootmem allocator */
768 for (i = 0; i < bfin_memmap.nr_map; i++) {
770 * Reserve usable memory
772 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
775 * We are rounding up the start address of usable memory:
777 curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
778 if (curr_pfn >= end_pfn)
781 * ... and at the end of the usable range downwards:
783 last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
784 bfin_memmap.map[i].size);
786 if (last_pfn > end_pfn)
790 * .. finally, did all the rounding and playing
791 * around just make the area go away?
793 if (last_pfn <= curr_pfn)
796 size = last_pfn - curr_pfn;
797 free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
800 /* reserve memory before memory_start, including bootmap */
801 reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
802 memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
806 #define EBSZ_TO_MEG(ebsz) \
809 switch (ebsz & 0xf) { \
810 case 0x1: meg = 16; break; \
811 case 0x3: meg = 32; break; \
812 case 0x5: meg = 64; break; \
813 case 0x7: meg = 128; break; \
814 case 0x9: meg = 256; break; \
815 case 0xb: meg = 512; break; \
819 static inline int __init get_mem_size(void)
821 #if defined(EBIU_SDBCTL)
822 # if defined(BF561_FAMILY)
824 u32 sdbctl = bfin_read_EBIU_SDBCTL();
825 ret += EBSZ_TO_MEG(sdbctl >> 0);
826 ret += EBSZ_TO_MEG(sdbctl >> 8);
827 ret += EBSZ_TO_MEG(sdbctl >> 16);
828 ret += EBSZ_TO_MEG(sdbctl >> 24);
831 return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
833 #elif defined(EBIU_DDRCTL1)
834 u32 ddrctl = bfin_read_EBIU_DDRCTL1();
836 switch (ddrctl & 0xc0000) {
850 switch (ddrctl & 0x30000) {
858 if ((ddrctl & 0xc000) == 0x4000)
861 #elif defined(CONFIG_BF60x)
862 u32 ddrctl = bfin_read_DMC0_CFG();
864 switch (ddrctl & 0xf00) {
889 __attribute__((weak))
890 void __init native_machine_early_platform_add_devices(void)
895 static inline u_long bfin_get_clk(char *name)
900 clk = clk_get(NULL, name);
904 clk_rate = clk_get_rate(clk);
910 void __init setup_arch(char **cmdline_p)
913 unsigned long sclk, cclk;
915 native_machine_early_platform_add_devices();
917 enable_shadow_console();
919 /* Check to make sure we are running on the right processor */
921 if (unlikely(CPUID != bfin_cpuid()))
922 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
923 CPU, bfin_cpuid(), bfin_revid());
925 #ifdef CONFIG_DUMMY_CONSOLE
926 conswitchp = &dummy_con;
929 #if defined(CONFIG_CMDLINE_BOOL)
930 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
931 command_line[sizeof(command_line) - 1] = 0;
934 /* Keep a copy of command line */
935 *cmdline_p = &command_line[0];
936 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
937 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
939 memset(&bfin_memmap, 0, sizeof(bfin_memmap));
942 /* Should init clock device before parse command early */
945 /* If the user does not specify things on the command line, use
946 * what the bootloader set things up as
948 physical_mem_end = 0;
949 parse_cmdline_early(&command_line[0]);
952 _ramend = get_mem_size() * 1024 * 1024;
954 if (physical_mem_end == 0)
955 physical_mem_end = _ramend;
960 /* Initialize Async memory banks */
961 bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
962 bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
963 bfin_write_EBIU_AMGCTL(AMGCTLVAL);
964 #ifdef CONFIG_EBIU_MBSCTLVAL
965 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
966 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
967 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
970 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
971 bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
972 bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
973 bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
974 bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
975 ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
981 if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
982 panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
985 if (ANOMALY_05000266) {
986 bfin_read_IMDMA_D0_IRQ_STATUS();
987 bfin_read_IMDMA_D1_IRQ_STATUS();
991 mmr = bfin_read_TBUFCTL();
992 printk(KERN_INFO "Hardware Trace %s and %sabled\n",
993 (mmr & 0x1) ? "active" : "off",
994 (mmr & 0x2) ? "en" : "dis");
996 mmr = bfin_read_SYSCR();
997 printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
999 /* Newer parts mirror SWRST bits in SYSCR */
1000 #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
1001 defined(CONFIG_BF538) || defined(CONFIG_BF539)
1002 _bfin_swrst = bfin_read_SWRST();
1004 /* Clear boot mode field */
1005 _bfin_swrst = mmr & ~0xf;
1008 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
1009 bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
1011 #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
1012 bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
1016 if (_bfin_swrst & SWRST_DBL_FAULT_A) {
1018 if (_bfin_swrst & RESET_DOUBLE) {
1020 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
1021 #ifdef CONFIG_DEBUG_DOUBLEFAULT
1022 /* We assume the crashing kernel, and the current symbol table match */
1023 printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
1024 initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
1025 initial_pda.retx_doublefault);
1026 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
1027 initial_pda.dcplb_doublefault_addr);
1028 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
1029 initial_pda.icplb_doublefault_addr);
1031 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
1033 } else if (_bfin_swrst & RESET_WDOG)
1034 printk(KERN_INFO "Recovering from Watchdog event\n");
1035 else if (_bfin_swrst & RESET_SOFTWARE)
1036 printk(KERN_NOTICE "Reset caused by Software reset\n");
1038 printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
1039 if (bfin_compiled_revid() == 0xffff)
1040 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
1041 else if (bfin_compiled_revid() == -1)
1042 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
1044 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
1046 if (likely(CPUID == bfin_cpuid())) {
1047 if (bfin_revid() != bfin_compiled_revid()) {
1048 if (bfin_compiled_revid() == -1)
1049 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
1051 else if (bfin_compiled_revid() != 0xffff) {
1052 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
1053 bfin_compiled_revid(), bfin_revid());
1054 if (bfin_compiled_revid() > bfin_revid())
1055 panic("Error: you are missing anomaly workarounds for this rev");
1058 if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
1059 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
1063 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
1066 printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
1067 cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
1069 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
1070 cclk / 1000000, sclk / 1000000);
1073 setup_bootmem_allocator();
1077 /* Copy atomic sequences to their fixed location, and sanity check that
1078 these locations are the ones that we advertise to userspace. */
1079 memcpy((void *)FIXED_CODE_START, &fixed_code_start,
1080 FIXED_CODE_END - FIXED_CODE_START);
1081 BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
1082 != SIGRETURN_STUB - FIXED_CODE_START);
1083 BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
1084 != ATOMIC_XCHG32 - FIXED_CODE_START);
1085 BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
1086 != ATOMIC_CAS32 - FIXED_CODE_START);
1087 BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
1088 != ATOMIC_ADD32 - FIXED_CODE_START);
1089 BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
1090 != ATOMIC_SUB32 - FIXED_CODE_START);
1091 BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
1092 != ATOMIC_IOR32 - FIXED_CODE_START);
1093 BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
1094 != ATOMIC_AND32 - FIXED_CODE_START);
1095 BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
1096 != ATOMIC_XOR32 - FIXED_CODE_START);
1097 BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
1098 != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
1101 platform_init_cpus();
1103 init_exception_vectors();
1104 bfin_cache_init(); /* Initialize caches for the boot CPU */
1107 static int __init topology_init(void)
1111 for_each_possible_cpu(cpu) {
1112 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
1118 subsys_initcall(topology_init);
1120 /* Get the input clock frequency */
1121 static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
1122 #ifndef CONFIG_BF60x
1123 static u_long get_clkin_hz(void)
1125 return cached_clkin_hz;
1128 static int __init early_init_clkin_hz(char *buf)
1130 cached_clkin_hz = simple_strtoul(buf, NULL, 0);
1131 #ifdef BFIN_KERNEL_CLOCK
1132 if (cached_clkin_hz != CONFIG_CLKIN_HZ)
1133 panic("cannot change clkin_hz when reprogramming clocks");
1137 early_param("clkin_hz=", early_init_clkin_hz);
1139 #ifndef CONFIG_BF60x
1140 /* Get the voltage input multiplier */
1141 static u_long get_vco(void)
1143 static u_long cached_vco;
1144 u_long msel, pll_ctl;
1146 /* The assumption here is that VCO never changes at runtime.
1147 * If, someday, we support that, then we'll have to change this.
1152 pll_ctl = bfin_read_PLL_CTL();
1153 msel = (pll_ctl >> 9) & 0x3F;
1157 cached_vco = get_clkin_hz();
1158 cached_vco >>= (1 & pll_ctl); /* DF bit */
1164 /* Get the Core clock */
1165 u_long get_cclk(void)
1168 return bfin_get_clk("CCLK");
1170 static u_long cached_cclk_pll_div, cached_cclk;
1173 if (bfin_read_PLL_STAT() & 0x1)
1174 return get_clkin_hz();
1176 ssel = bfin_read_PLL_DIV();
1177 if (ssel == cached_cclk_pll_div)
1180 cached_cclk_pll_div = ssel;
1182 csel = ((ssel >> 4) & 0x03);
1184 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
1185 cached_cclk = get_vco() / ssel;
1187 cached_cclk = get_vco() >> csel;
1191 EXPORT_SYMBOL(get_cclk);
1194 /* Get the bf60x clock of SCLK0 domain */
1195 u_long get_sclk0(void)
1197 return bfin_get_clk("SCLK0");
1199 EXPORT_SYMBOL(get_sclk0);
1201 /* Get the bf60x clock of SCLK1 domain */
1202 u_long get_sclk1(void)
1204 return bfin_get_clk("SCLK1");
1206 EXPORT_SYMBOL(get_sclk1);
1208 /* Get the bf60x DRAM clock */
1209 u_long get_dclk(void)
1211 return bfin_get_clk("DCLK");
1213 EXPORT_SYMBOL(get_dclk);
1216 /* Get the default system clock */
1217 u_long get_sclk(void)
1222 static u_long cached_sclk;
1225 /* The assumption here is that SCLK never changes at runtime.
1226 * If, someday, we support that, then we'll have to change this.
1231 if (bfin_read_PLL_STAT() & 0x1)
1232 return get_clkin_hz();
1234 ssel = bfin_read_PLL_DIV() & 0xf;
1236 printk(KERN_WARNING "Invalid System Clock\n");
1240 cached_sclk = get_vco() / ssel;
1244 EXPORT_SYMBOL(get_sclk);
1246 unsigned long sclk_to_usecs(unsigned long sclk)
1248 u64 tmp = USEC_PER_SEC * (u64)sclk;
1249 do_div(tmp, get_sclk());
1252 EXPORT_SYMBOL(sclk_to_usecs);
1254 unsigned long usecs_to_sclk(unsigned long usecs)
1256 u64 tmp = get_sclk() * (u64)usecs;
1257 do_div(tmp, USEC_PER_SEC);
1260 EXPORT_SYMBOL(usecs_to_sclk);
1263 * Get CPU information for use by the procfs.
1265 static int show_cpuinfo(struct seq_file *m, void *v)
1267 char *cpu, *mmu, *fpu, *vendor, *cache;
1269 int cpu_num = *(unsigned int *)v;
1271 u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
1272 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
1277 revid = bfin_revid();
1282 switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
1284 vendor = "Analog Devices";
1291 seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
1293 if (CPUID == bfin_cpuid())
1294 seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
1296 seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
1297 CPUID, bfin_cpuid());
1299 seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
1301 cpu, cclk/1000000, sclk/1000000,
1309 if (bfin_revid() != bfin_compiled_revid()) {
1310 if (bfin_compiled_revid() == -1)
1311 seq_printf(m, "(Compiled for Rev none)");
1312 else if (bfin_compiled_revid() == 0xffff)
1313 seq_printf(m, "(Compiled for Rev any)");
1315 seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
1318 seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
1319 cclk/1000000, cclk%1000000,
1320 sclk/1000000, sclk%1000000);
1321 seq_printf(m, "bogomips\t: %lu.%02lu\n"
1322 "Calibration\t: %lu loops\n",
1323 (loops_per_jiffy * HZ) / 500000,
1324 ((loops_per_jiffy * HZ) / 5000) % 100,
1325 (loops_per_jiffy * HZ));
1327 /* Check Cache configutation */
1328 switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
1330 cache = "dbank-A/B\t: cache/sram";
1335 cache = "dbank-A/B\t: cache/cache";
1340 cache = "dbank-A/B\t: sram/sram";
1351 /* Is it turned on? */
1352 if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
1355 if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
1358 seq_printf(m, "cache size\t: %d KB(L1 icache) "
1359 "%d KB(L1 dcache) %d KB(L2 cache)\n",
1360 icache_size, dcache_size, 0);
1361 seq_printf(m, "%s\n", cache);
1362 seq_printf(m, "external memory\t: "
1363 #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
1368 " in instruction cache\n");
1369 seq_printf(m, "external memory\t: "
1370 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
1371 "cacheable (write-back)"
1372 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
1373 "cacheable (write-through)"
1377 " in data cache\n");
1380 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
1381 BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
1383 seq_printf(m, "icache setup\t: off\n");
1386 "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
1387 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
1389 #ifdef __ARCH_SYNC_CORE_DCACHE
1390 seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
1392 #ifdef __ARCH_SYNC_CORE_ICACHE
1393 seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
1396 seq_printf(m, "\n");
1398 if (cpu_num != num_possible_cpus() - 1)
1402 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
1403 seq_printf(m, "L2 SRAM\t\t: "
1404 #if defined(CONFIG_BFIN_L2_ICACHEABLE)
1409 " in instruction cache\n");
1410 seq_printf(m, "L2 SRAM\t\t: "
1411 #if defined(CONFIG_BFIN_L2_WRITEBACK)
1412 "cacheable (write-back)"
1413 #elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
1414 "cacheable (write-through)"
1418 " in data cache\n");
1420 seq_printf(m, "board name\t: %s\n", bfin_board_name);
1421 seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
1422 physical_mem_end >> 10, 0ul, physical_mem_end);
1423 seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
1424 ((int)memory_end - (int)_rambase) >> 10,
1425 _rambase, memory_end);
1430 static void *c_start(struct seq_file *m, loff_t *pos)
1433 *pos = cpumask_first(cpu_online_mask);
1434 if (*pos >= num_online_cpus())
1440 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1442 *pos = cpumask_next(*pos, cpu_online_mask);
1444 return c_start(m, pos);
1447 static void c_stop(struct seq_file *m, void *v)
1451 const struct seq_operations cpuinfo_op = {
1455 .show = show_cpuinfo,
1458 void __init cmdline_init(const char *r0)
1460 early_shadow_stamp();
1462 strncpy(command_line, r0, COMMAND_LINE_SIZE);