2 * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
4 * Copyright 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #if defined(EBIU_SDGCTL)
10 #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
11 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
12 defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
13 defined(CONFIG_MEM_GENERIC_BOARD) || \
14 defined(CONFIG_MEM_MT48LC32M8A2_75) || \
15 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
16 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
17 defined(CONFIG_MEM_MT48LC32M8A2_75)
18 #if (CONFIG_SCLK_HZ > 119402985)
19 #define SDRAM_tRP TRP_2
20 #define SDRAM_tRP_num 2
21 #define SDRAM_tRAS TRAS_7
22 #define SDRAM_tRAS_num 7
23 #define SDRAM_tRCD TRCD_2
24 #define SDRAM_tWR TWR_2
26 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
27 #define SDRAM_tRP TRP_2
28 #define SDRAM_tRP_num 2
29 #define SDRAM_tRAS TRAS_6
30 #define SDRAM_tRAS_num 6
31 #define SDRAM_tRCD TRCD_2
32 #define SDRAM_tWR TWR_2
34 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
35 #define SDRAM_tRP TRP_2
36 #define SDRAM_tRP_num 2
37 #define SDRAM_tRAS TRAS_5
38 #define SDRAM_tRAS_num 5
39 #define SDRAM_tRCD TRCD_2
40 #define SDRAM_tWR TWR_2
42 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
43 #define SDRAM_tRP TRP_2
44 #define SDRAM_tRP_num 2
45 #define SDRAM_tRAS TRAS_4
46 #define SDRAM_tRAS_num 4
47 #define SDRAM_tRCD TRCD_2
48 #define SDRAM_tWR TWR_2
50 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
51 #define SDRAM_tRP TRP_2
52 #define SDRAM_tRP_num 2
53 #define SDRAM_tRAS TRAS_3
54 #define SDRAM_tRAS_num 3
55 #define SDRAM_tRCD TRCD_2
56 #define SDRAM_tWR TWR_2
58 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
59 #define SDRAM_tRP TRP_1
60 #define SDRAM_tRP_num 1
61 #define SDRAM_tRAS TRAS_4
62 #define SDRAM_tRAS_num 4
63 #define SDRAM_tRCD TRCD_1
64 #define SDRAM_tWR TWR_2
66 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
67 #define SDRAM_tRP TRP_1
68 #define SDRAM_tRP_num 1
69 #define SDRAM_tRAS TRAS_3
70 #define SDRAM_tRAS_num 3
71 #define SDRAM_tRCD TRCD_1
72 #define SDRAM_tWR TWR_2
74 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
75 #define SDRAM_tRP TRP_1
76 #define SDRAM_tRP_num 1
77 #define SDRAM_tRAS TRAS_2
78 #define SDRAM_tRAS_num 2
79 #define SDRAM_tRCD TRCD_1
80 #define SDRAM_tWR TWR_2
82 #if (CONFIG_SCLK_HZ <= 29850746)
83 #define SDRAM_tRP TRP_1
84 #define SDRAM_tRP_num 1
85 #define SDRAM_tRAS TRAS_1
86 #define SDRAM_tRAS_num 1
87 #define SDRAM_tRCD TRCD_1
88 #define SDRAM_tWR TWR_2
93 * The BF526-EZ-Board changed SDRAM chips between revisions,
94 * so we use below timings to accommodate both.
96 #if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
97 #if (CONFIG_SCLK_HZ > 119402985)
98 #define SDRAM_tRP TRP_2
99 #define SDRAM_tRP_num 2
100 #define SDRAM_tRAS TRAS_8
101 #define SDRAM_tRAS_num 8
102 #define SDRAM_tRCD TRCD_2
103 #define SDRAM_tWR TWR_2
105 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
106 #define SDRAM_tRP TRP_2
107 #define SDRAM_tRP_num 2
108 #define SDRAM_tRAS TRAS_7
109 #define SDRAM_tRAS_num 7
110 #define SDRAM_tRCD TRCD_2
111 #define SDRAM_tWR TWR_2
113 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
114 #define SDRAM_tRP TRP_2
115 #define SDRAM_tRP_num 2
116 #define SDRAM_tRAS TRAS_6
117 #define SDRAM_tRAS_num 6
118 #define SDRAM_tRCD TRCD_2
119 #define SDRAM_tWR TWR_2
121 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
122 #define SDRAM_tRP TRP_2
123 #define SDRAM_tRP_num 2
124 #define SDRAM_tRAS TRAS_5
125 #define SDRAM_tRAS_num 5
126 #define SDRAM_tRCD TRCD_2
127 #define SDRAM_tWR TWR_2
129 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
130 #define SDRAM_tRP TRP_2
131 #define SDRAM_tRP_num 2
132 #define SDRAM_tRAS TRAS_4
133 #define SDRAM_tRAS_num 4
134 #define SDRAM_tRCD TRCD_2
135 #define SDRAM_tWR TWR_2
137 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
138 #define SDRAM_tRP TRP_2
139 #define SDRAM_tRP_num 2
140 #define SDRAM_tRAS TRAS_4
141 #define SDRAM_tRAS_num 4
142 #define SDRAM_tRCD TRCD_1
143 #define SDRAM_tWR TWR_2
145 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
146 #define SDRAM_tRP TRP_2
147 #define SDRAM_tRP_num 2
148 #define SDRAM_tRAS TRAS_3
149 #define SDRAM_tRAS_num 3
150 #define SDRAM_tRCD TRCD_1
151 #define SDRAM_tWR TWR_2
153 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
154 #define SDRAM_tRP TRP_1
155 #define SDRAM_tRP_num 1
156 #define SDRAM_tRAS TRAS_3
157 #define SDRAM_tRAS_num 3
158 #define SDRAM_tRCD TRCD_1
159 #define SDRAM_tWR TWR_2
161 #if (CONFIG_SCLK_HZ <= 29850746)
162 #define SDRAM_tRP TRP_1
163 #define SDRAM_tRP_num 1
164 #define SDRAM_tRAS TRAS_2
165 #define SDRAM_tRAS_num 2
166 #define SDRAM_tRCD TRCD_1
167 #define SDRAM_tWR TWR_2
171 #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
172 defined(CONFIG_MEM_MT48LC8M32B2B5_7)
173 /*SDRAM INFORMATION: */
174 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
175 #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
176 #define SDRAM_CL CL_3
179 #if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
180 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
181 defined(CONFIG_MEM_GENERIC_BOARD) || \
182 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
183 defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
184 defined(CONFIG_MEM_MT48LC32M8A2_75)
185 /*SDRAM INFORMATION: */
186 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
187 #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
188 #define SDRAM_CL CL_3
191 #if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
192 /*SDRAM INFORMATION: */
193 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
194 #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
195 #define SDRAM_CL CL_2
199 #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
200 /* Equation from section 17 (p17-46) of BF533 HRM */
201 #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
203 /* Enable SCLK Out */
204 #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
206 #define mem_SDRRC CONFIG_MEM_SDRRC
207 #define mem_SDGCTL CONFIG_MEM_SDGCTL
212 #if defined(EBIU_DDRCTL0)
213 #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
214 #define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
215 #define DDR_CLK_HZ(x) (1000*1000*1000/x)
217 #if defined(CONFIG_MEM_MT46V32M16_6T)
218 #define DDR_SIZE DEVSZ_512
219 #define DDR_WIDTH DEVWD_16
220 #define DDR_MAX_tCK 13
222 #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
223 #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
224 #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
225 #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
226 #define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
228 #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
229 #define DDR_tWTR DDR_TWTR(1)
230 #define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
231 #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
234 #if defined(CONFIG_MEM_MT46V32M16_5B)
235 #define DDR_SIZE DEVSZ_512
236 #define DDR_WIDTH DEVWD_16
237 #define DDR_MAX_tCK 13
239 #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
240 #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
241 #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
242 #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
243 #define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
245 #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
246 #define DDR_tWTR DDR_TWTR(2)
247 #define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
248 #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
251 #if defined(CONFIG_MEM_GENERIC_BOARD)
252 #define DDR_SIZE DEVSZ_512
253 #define DDR_WIDTH DEVWD_16
254 #define DDR_MAX_tCK 13
256 #define DDR_tRCD DDR_TRCD(3)
257 #define DDR_tWTR DDR_TWTR(2)
258 #define DDR_tWR DDR_TWR(2)
259 #define DDR_tMRD DDR_TMRD(2)
260 #define DDR_tRP DDR_TRP(3)
261 #define DDR_tRAS DDR_TRAS(7)
262 #define DDR_tRC DDR_TRC(10)
263 #define DDR_tRFC DDR_TRFC(12)
264 #define DDR_tREFI DDR_TREFI(1288)
267 #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
268 # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
269 #elif(CONFIG_SCLK_HZ <= 133333333)
272 # error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
275 #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
276 #define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
277 #define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
278 | DDR_tMRD | DDR_tWR | DDR_tRCD)
279 #define mem_DDRCTL2 DDR_CL
281 #define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
282 #define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
283 #define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
287 #if defined CONFIG_CLKIN_HALF
293 #if defined CONFIG_PLL_BYPASS
299 /***************************************Currently Not Being Used *********************************/
301 #if defined(CONFIG_FLASH_SPEED_BWAT) && \
302 defined(CONFIG_FLASH_SPEED_BRAT) && \
303 defined(CONFIG_FLASH_SPEED_BHT) && \
304 defined(CONFIG_FLASH_SPEED_BST) && \
305 defined(CONFIG_FLASH_SPEED_BTT)
307 #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
308 #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
309 #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
310 #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
311 #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
313 #if (flash_EBIU_AMBCTL_TT > 3)
314 #define flash_EBIU_AMBCTL0_TT B0TT_4
316 #if (flash_EBIU_AMBCTL_TT == 3)
317 #define flash_EBIU_AMBCTL0_TT B0TT_3
319 #if (flash_EBIU_AMBCTL_TT == 2)
320 #define flash_EBIU_AMBCTL0_TT B0TT_2
322 #if (flash_EBIU_AMBCTL_TT < 2)
323 #define flash_EBIU_AMBCTL0_TT B0TT_1
326 #if (flash_EBIU_AMBCTL_ST > 3)
327 #define flash_EBIU_AMBCTL0_ST B0ST_4
329 #if (flash_EBIU_AMBCTL_ST == 3)
330 #define flash_EBIU_AMBCTL0_ST B0ST_3
332 #if (flash_EBIU_AMBCTL_ST == 2)
333 #define flash_EBIU_AMBCTL0_ST B0ST_2
335 #if (flash_EBIU_AMBCTL_ST < 2)
336 #define flash_EBIU_AMBCTL0_ST B0ST_1
339 #if (flash_EBIU_AMBCTL_HT > 2)
340 #define flash_EBIU_AMBCTL0_HT B0HT_3
342 #if (flash_EBIU_AMBCTL_HT == 2)
343 #define flash_EBIU_AMBCTL0_HT B0HT_2
345 #if (flash_EBIU_AMBCTL_HT == 1)
346 #define flash_EBIU_AMBCTL0_HT B0HT_1
348 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
349 #define flash_EBIU_AMBCTL0_HT B0HT_0
351 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
352 #define flash_EBIU_AMBCTL0_HT B0HT_1
355 #if (flash_EBIU_AMBCTL_WAT > 14)
356 #define flash_EBIU_AMBCTL0_WAT B0WAT_15
358 #if (flash_EBIU_AMBCTL_WAT == 14)
359 #define flash_EBIU_AMBCTL0_WAT B0WAT_14
361 #if (flash_EBIU_AMBCTL_WAT == 13)
362 #define flash_EBIU_AMBCTL0_WAT B0WAT_13
364 #if (flash_EBIU_AMBCTL_WAT == 12)
365 #define flash_EBIU_AMBCTL0_WAT B0WAT_12
367 #if (flash_EBIU_AMBCTL_WAT == 11)
368 #define flash_EBIU_AMBCTL0_WAT B0WAT_11
370 #if (flash_EBIU_AMBCTL_WAT == 10)
371 #define flash_EBIU_AMBCTL0_WAT B0WAT_10
373 #if (flash_EBIU_AMBCTL_WAT == 9)
374 #define flash_EBIU_AMBCTL0_WAT B0WAT_9
376 #if (flash_EBIU_AMBCTL_WAT == 8)
377 #define flash_EBIU_AMBCTL0_WAT B0WAT_8
379 #if (flash_EBIU_AMBCTL_WAT == 7)
380 #define flash_EBIU_AMBCTL0_WAT B0WAT_7
382 #if (flash_EBIU_AMBCTL_WAT == 6)
383 #define flash_EBIU_AMBCTL0_WAT B0WAT_6
385 #if (flash_EBIU_AMBCTL_WAT == 5)
386 #define flash_EBIU_AMBCTL0_WAT B0WAT_5
388 #if (flash_EBIU_AMBCTL_WAT == 4)
389 #define flash_EBIU_AMBCTL0_WAT B0WAT_4
391 #if (flash_EBIU_AMBCTL_WAT == 3)
392 #define flash_EBIU_AMBCTL0_WAT B0WAT_3
394 #if (flash_EBIU_AMBCTL_WAT == 2)
395 #define flash_EBIU_AMBCTL0_WAT B0WAT_2
397 #if (flash_EBIU_AMBCTL_WAT == 1)
398 #define flash_EBIU_AMBCTL0_WAT B0WAT_1
401 #if (flash_EBIU_AMBCTL_RAT > 14)
402 #define flash_EBIU_AMBCTL0_RAT B0RAT_15
404 #if (flash_EBIU_AMBCTL_RAT == 14)
405 #define flash_EBIU_AMBCTL0_RAT B0RAT_14
407 #if (flash_EBIU_AMBCTL_RAT == 13)
408 #define flash_EBIU_AMBCTL0_RAT B0RAT_13
410 #if (flash_EBIU_AMBCTL_RAT == 12)
411 #define flash_EBIU_AMBCTL0_RAT B0RAT_12
413 #if (flash_EBIU_AMBCTL_RAT == 11)
414 #define flash_EBIU_AMBCTL0_RAT B0RAT_11
416 #if (flash_EBIU_AMBCTL_RAT == 10)
417 #define flash_EBIU_AMBCTL0_RAT B0RAT_10
419 #if (flash_EBIU_AMBCTL_RAT == 9)
420 #define flash_EBIU_AMBCTL0_RAT B0RAT_9
422 #if (flash_EBIU_AMBCTL_RAT == 8)
423 #define flash_EBIU_AMBCTL0_RAT B0RAT_8
425 #if (flash_EBIU_AMBCTL_RAT == 7)
426 #define flash_EBIU_AMBCTL0_RAT B0RAT_7
428 #if (flash_EBIU_AMBCTL_RAT == 6)
429 #define flash_EBIU_AMBCTL0_RAT B0RAT_6
431 #if (flash_EBIU_AMBCTL_RAT == 5)
432 #define flash_EBIU_AMBCTL0_RAT B0RAT_5
434 #if (flash_EBIU_AMBCTL_RAT == 4)
435 #define flash_EBIU_AMBCTL0_RAT B0RAT_4
437 #if (flash_EBIU_AMBCTL_RAT == 3)
438 #define flash_EBIU_AMBCTL0_RAT B0RAT_3
440 #if (flash_EBIU_AMBCTL_RAT == 2)
441 #define flash_EBIU_AMBCTL0_RAT B0RAT_2
443 #if (flash_EBIU_AMBCTL_RAT == 1)
444 #define flash_EBIU_AMBCTL0_RAT B0RAT_1
447 #define flash_EBIU_AMBCTL0 \
448 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
449 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)