2 * bfin_crc.h - interface to Blackfin CRC controllers
4 * Copyright 2012 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
10 #define __BFIN_CRC_H__
12 /* Function driver which use hardware crc must initialize the structure */
14 /* Input data address */
15 unsigned char *in_addr;
16 /* Output data address */
17 unsigned char *out_addr;
18 /* Input or output bytes */
19 unsigned long datasize;
21 /* CRC to compare with that of input buffer */
22 unsigned long crc_compare;
23 /* Value to compare with input data */
24 unsigned long val_verify;
26 unsigned long val_fill;
28 /* Value to program the 32b CRC Polynomial */
29 unsigned long crc_poly;
31 /* CRC calculated from the input data */
32 unsigned long crc_result;
33 /* First failed position to verify input data */
34 unsigned long pos_verify;
36 /* CRC mirror flags */
37 unsigned int bitmirr:1;
38 unsigned int bytmirr:1;
39 unsigned int w16swp:1;
41 unsigned int rsltmirr:1;
42 unsigned int polymirr:1;
43 unsigned int cmpmirr:1;
46 /* Userspace interface */
47 #define CRC_IOC_MAGIC 'C'
48 #define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int)
49 #define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int)
50 #define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int)
51 #define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int)
56 #include <linux/types.h>
57 #include <linux/spinlock.h>
58 #include <linux/miscdevice.h>
83 struct miscdevice mdev;
84 struct list_head list;
88 volatile struct crc_register *regs;
89 struct crc_info *info;
92 unsigned short opmode;
96 /* CRC_STATUS Masks */
97 #define CMPERR 0x00000002 /* Compare error */
98 #define DCNTEXP 0x00000010 /* datacnt register expired */
99 #define IBR 0x00010000 /* Input buffer ready */
100 #define OBR 0x00020000 /* Output buffer ready */
101 #define IRR 0x00040000 /* Immediate result readt */
102 #define LUTDONE 0x00080000 /* Look-up table generation done */
103 #define FSTAT 0x00700000 /* FIFO status */
104 #define MAX_FIFO 4 /* Max fifo size */
106 /* CRC_CONTROL Masks */
107 #define BLKEN 0x00000001 /* Block enable */
108 #define OPMODE 0x000000F0 /* Operation mode */
109 #define OPMODE_OFFSET 4 /* Operation mode mask offset*/
110 #define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */
111 #define MODE_DATA_FILL 2 /* MTM data fill */
112 #define MODE_CALC_CRC 3 /* MSM CRC compute and compare */
113 #define MODE_DATA_VERIFY 4 /* MSM data verify */
114 #define AUTOCLRZ 0x00000100 /* Auto clear to zero */
115 #define AUTOCLRF 0x00000200 /* Auto clear to one */
116 #define OBRSTALL 0x00001000 /* Stall on output buffer ready */
117 #define IRRSTALL 0x00002000 /* Stall on immediate result ready */
118 #define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */
119 #define BITMIRR_OFFSET 16 /* Mirror bits offset */
120 #define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */
121 #define BYTMIRR_OFFSET 17 /* Mirror bytes offset */
122 #define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */
123 #define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */
124 #define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */
125 #define FDSEL_OFFSET 19 /* Mirror FIFO offset */
126 #define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */
127 #define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */
128 #define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */
129 #define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */
130 #define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */
131 #define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */
133 /* CRC_INTREN Masks */
134 #define CMPERRI 0x02 /* CRC_ERROR_INTR */
135 #define DCNTEXPI 0x10 /* CRC_STATUS_INTR */