2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
23 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_BZIP2
25 select HAVE_KERNEL_LZMA
27 select ARCH_WANT_OPTIONAL_GPIOLIB
36 config GENERIC_FIND_NEXT_BIT
39 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
45 config GENERIC_IRQ_PROBE
51 config FORCE_MAX_ZONEORDER
55 config GENERIC_CALIBRATE_DELAY
58 config STACKTRACE_SUPPORT
61 config TRACE_IRQFLAGS_SUPPORT
66 source "kernel/Kconfig.preempt"
68 source "kernel/Kconfig.freezer"
70 menu "Blackfin Processor Options"
72 comment "Processor and Board Settings"
81 BF512 Processor Support.
86 BF514 Processor Support.
91 BF516 Processor Support.
96 BF518 Processor Support.
101 BF522 Processor Support.
106 BF523 Processor Support.
111 BF524 Processor Support.
116 BF525 Processor Support.
121 BF526 Processor Support.
126 BF527 Processor Support.
131 BF531 Processor Support.
136 BF532 Processor Support.
141 BF533 Processor Support.
146 BF534 Processor Support.
151 BF536 Processor Support.
156 BF537 Processor Support.
161 BF538 Processor Support.
166 BF539 Processor Support.
171 BF542 Processor Support.
176 BF542 Processor Support.
181 BF544 Processor Support.
186 BF544 Processor Support.
191 BF547 Processor Support.
196 BF547 Processor Support.
201 BF548 Processor Support.
206 BF548 Processor Support.
211 BF549 Processor Support.
216 BF549 Processor Support.
221 BF561 Processor Support.
228 bool "Symmetric multi-processing support"
230 This enables support for systems with more than one CPU,
231 like the dual core BF561. If you have a system with only one
232 CPU, say N. If you have a system with more than one CPU, say Y.
234 If you don't know what to do here, say N.
248 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
249 default 2 if (BF537 || BF536 || BF534)
250 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
251 default 4 if (BF538 || BF539)
255 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
256 default 3 if (BF537 || BF536 || BF534 || BF54xM)
257 default 5 if (BF561 || BF538 || BF539)
258 default 6 if (BF533 || BF532 || BF531)
262 default BF_REV_0_0 if (BF51x || BF52x)
263 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
264 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
268 depends on (BF51x || BF52x || (BF54x && !BF54xM))
272 depends on (BF52x || (BF54x && !BF54xM))
276 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
280 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
284 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
288 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
292 depends on (BF533 || BF532 || BF531)
304 depends on (BF512 || BF514 || BF516 || BF518)
309 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
314 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
319 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
324 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
327 config MEM_GENERIC_BOARD
329 depends on GENERIC_BOARD
332 config MEM_MT48LC64M4A2FB_7E
334 depends on (BFIN533_STAMP)
337 config MEM_MT48LC16M16A2TG_75
339 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
340 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
341 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
344 config MEM_MT48LC32M8A2_75
346 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
349 config MEM_MT48LC8M32B2B5_7
351 depends on (BFIN561_BLUETECHNIX_CM)
354 config MEM_MT48LC32M16A2TG_75
356 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
359 config MEM_MT48LC32M8A2_75
361 depends on (BFIN518F_EZBRD)
364 source "arch/blackfin/mach-bf518/Kconfig"
365 source "arch/blackfin/mach-bf527/Kconfig"
366 source "arch/blackfin/mach-bf533/Kconfig"
367 source "arch/blackfin/mach-bf561/Kconfig"
368 source "arch/blackfin/mach-bf537/Kconfig"
369 source "arch/blackfin/mach-bf538/Kconfig"
370 source "arch/blackfin/mach-bf548/Kconfig"
372 menu "Board customizations"
375 bool "Default bootloader kernel arguments"
378 string "Initial kernel command string"
379 depends on CMDLINE_BOOL
380 default "console=ttyBF0,57600"
382 If you don't have a boot loader capable of passing a command line string
383 to the kernel, you may specify one here. As a minimum, you should specify
384 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
387 hex "Kernel load address for booting"
389 range 0x1000 0x20000000
391 This option allows you to set the load address of the kernel.
392 This can be useful if you are on a board which has a small amount
393 of memory or you wish to reserve some memory at the beginning of
396 Note that you need to keep this value above 4k (0x1000) as this
397 memory region is used to capture NULL pointer references as well
398 as some core kernel functions.
401 hex "Kernel ROM Base"
404 range 0x20000000 0x20400000 if !(BF54x || BF561)
405 range 0x20000000 0x30000000 if (BF54x || BF561)
408 comment "Clock/PLL Setup"
411 int "Frequency of the crystal on the board in Hz"
412 default "11059200" if BFIN533_STAMP
413 default "27000000" if BFIN533_EZKIT
414 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
415 default "30000000" if BFIN561_EZKIT
416 default "24576000" if PNAV10
417 default "10000000" if BFIN532_IP0X
419 The frequency of CLKIN crystal oscillator on the board in Hz.
420 Warning: This value should match the crystal on the board. Otherwise,
421 peripherals won't work properly.
423 config BFIN_KERNEL_CLOCK
424 bool "Re-program Clocks while Kernel boots?"
427 This option decides if kernel clocks are re-programed from the
428 bootloader settings. If the clocks are not set, the SDRAM settings
429 are also not changed, and the Bootloader does 100% of the hardware
434 depends on BFIN_KERNEL_CLOCK
439 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
442 If this is set the clock will be divided by 2, before it goes to the PLL.
446 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
448 default "22" if BFIN533_EZKIT
449 default "45" if BFIN533_STAMP
450 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
451 default "22" if BFIN533_BLUETECHNIX_CM
452 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
453 default "20" if BFIN561_EZKIT
454 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
456 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
457 PLL Frequency = (Crystal Frequency) * (this setting)
460 prompt "Core Clock Divider"
461 depends on BFIN_KERNEL_CLOCK
464 This sets the frequency of the core. It can be 1, 2, 4 or 8
465 Core Frequency = (PLL frequency) / (this setting)
481 int "System Clock Divider"
482 depends on BFIN_KERNEL_CLOCK
486 This sets the frequency of the system clock (including SDRAM or DDR).
487 This can be between 1 and 15
488 System Clock = (PLL frequency) / (this setting)
491 prompt "DDR SDRAM Chip Type"
492 depends on BFIN_KERNEL_CLOCK
494 default MEM_MT46V32M16_5B
496 config MEM_MT46V32M16_6T
499 config MEM_MT46V32M16_5B
504 prompt "DDR/SDRAM Timing"
505 depends on BFIN_KERNEL_CLOCK
506 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
508 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
509 The calculated SDRAM timing parameters may not be 100%
510 accurate - This option is therefore marked experimental.
512 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
513 bool "Calculate Timings (EXPERIMENTAL)"
514 depends on EXPERIMENTAL
516 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
517 bool "Provide accurate Timings based on target SCLK"
519 Please consult the Blackfin Hardware Reference Manuals as well
520 as the memory device datasheet.
521 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
524 menu "Memory Init Control"
525 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
542 config MEM_EBIU_DDRQUE
559 # Max & Min Speeds for various Chips
563 default 400000000 if BF512
564 default 400000000 if BF514
565 default 400000000 if BF516
566 default 400000000 if BF518
567 default 600000000 if BF522
568 default 400000000 if BF523
569 default 400000000 if BF524
570 default 600000000 if BF525
571 default 400000000 if BF526
572 default 600000000 if BF527
573 default 400000000 if BF531
574 default 400000000 if BF532
575 default 750000000 if BF533
576 default 500000000 if BF534
577 default 400000000 if BF536
578 default 600000000 if BF537
579 default 533333333 if BF538
580 default 533333333 if BF539
581 default 600000000 if BF542
582 default 533333333 if BF544
583 default 600000000 if BF547
584 default 600000000 if BF548
585 default 533333333 if BF549
586 default 600000000 if BF561
600 comment "Kernel Timer/Scheduler"
602 source kernel/Kconfig.hz
608 config GENERIC_CLOCKEVENTS
609 bool "Generic clock events"
610 depends on GENERIC_TIME
614 prompt "Kernel Tick Source"
615 depends on GENERIC_CLOCKEVENTS
616 default TICKSOURCE_CORETMR
618 config TICKSOURCE_GPTMR0
619 bool "Gptimer0 (SCLK domain)"
623 config TICKSOURCE_CORETMR
624 bool "Core timer (CCLK domain)"
628 config CYCLES_CLOCKSOURCE
629 bool "Use 'CYCLES' as a clocksource"
630 depends on GENERIC_CLOCKEVENTS
631 depends on !BFIN_SCRATCH_REG_CYCLES
634 If you say Y here, you will enable support for using the 'cycles'
635 registers as a clock source. Doing so means you will be unable to
636 safely write to the 'cycles' register during runtime. You will
637 still be able to read it (such as for performance monitoring), but
638 writing the registers will most likely crash the kernel.
640 config GPTMR0_CLOCKSOURCE
641 bool "Use GPTimer0 as a clocksource (higher rating)"
642 depends on GENERIC_CLOCKEVENTS
643 depends on !TICKSOURCE_GPTMR0
645 source kernel/time/Kconfig
650 prompt "Blackfin Exception Scratch Register"
651 default BFIN_SCRATCH_REG_RETN
653 Select the resource to reserve for the Exception handler:
654 - RETN: Non-Maskable Interrupt (NMI)
655 - RETE: Exception Return (JTAG/ICE)
656 - CYCLES: Performance counter
658 If you are unsure, please select "RETN".
660 config BFIN_SCRATCH_REG_RETN
663 Use the RETN register in the Blackfin exception handler
664 as a stack scratch register. This means you cannot
665 safely use NMI on the Blackfin while running Linux, but
666 you can debug the system with a JTAG ICE and use the
667 CYCLES performance registers.
669 If you are unsure, please select "RETN".
671 config BFIN_SCRATCH_REG_RETE
674 Use the RETE register in the Blackfin exception handler
675 as a stack scratch register. This means you cannot
676 safely use a JTAG ICE while debugging a Blackfin board,
677 but you can safely use the CYCLES performance registers
680 If you are unsure, please select "RETN".
682 config BFIN_SCRATCH_REG_CYCLES
685 Use the CYCLES register in the Blackfin exception handler
686 as a stack scratch register. This means you cannot
687 safely use the CYCLES performance registers on a Blackfin
688 board at anytime, but you can debug the system with a JTAG
691 If you are unsure, please select "RETN".
698 menu "Blackfin Kernel Optimizations"
701 comment "Memory Optimizations"
704 bool "Locate interrupt entry code in L1 Memory"
707 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
708 into L1 instruction memory. (less latency)
710 config EXCPT_IRQ_SYSC_L1
711 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
714 If enabled, the entire ASM lowlevel exception and interrupt entry code
715 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
719 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
722 If enabled, the frequently called do_irq dispatcher function is linked
723 into L1 instruction memory. (less latency)
725 config CORE_TIMER_IRQ_L1
726 bool "Locate frequently called timer_interrupt() function in L1 Memory"
729 If enabled, the frequently called timer_interrupt() function is linked
730 into L1 instruction memory. (less latency)
733 bool "Locate frequently idle function in L1 Memory"
736 If enabled, the frequently called idle function is linked
737 into L1 instruction memory. (less latency)
740 bool "Locate kernel schedule function in L1 Memory"
743 If enabled, the frequently called kernel schedule is linked
744 into L1 instruction memory. (less latency)
746 config ARITHMETIC_OPS_L1
747 bool "Locate kernel owned arithmetic functions in L1 Memory"
750 If enabled, arithmetic functions are linked
751 into L1 instruction memory. (less latency)
754 bool "Locate access_ok function in L1 Memory"
757 If enabled, the access_ok function is linked
758 into L1 instruction memory. (less latency)
761 bool "Locate memset function in L1 Memory"
764 If enabled, the memset function is linked
765 into L1 instruction memory. (less latency)
768 bool "Locate memcpy function in L1 Memory"
771 If enabled, the memcpy function is linked
772 into L1 instruction memory. (less latency)
774 config SYS_BFIN_SPINLOCK_L1
775 bool "Locate sys_bfin_spinlock function in L1 Memory"
778 If enabled, sys_bfin_spinlock function is linked
779 into L1 instruction memory. (less latency)
781 config IP_CHECKSUM_L1
782 bool "Locate IP Checksum function in L1 Memory"
785 If enabled, the IP Checksum function is linked
786 into L1 instruction memory. (less latency)
788 config CACHELINE_ALIGNED_L1
789 bool "Locate cacheline_aligned data to L1 Data Memory"
794 If enabled, cacheline_aligned data is linked
795 into L1 data memory. (less latency)
797 config SYSCALL_TAB_L1
798 bool "Locate Syscall Table L1 Data Memory"
802 If enabled, the Syscall LUT is linked
803 into L1 data memory. (less latency)
805 config CPLB_SWITCH_TAB_L1
806 bool "Locate CPLB Switch Tables L1 Data Memory"
810 If enabled, the CPLB Switch Tables are linked
811 into L1 data memory. (less latency)
814 bool "Support locating application stack in L1 Scratch Memory"
817 If enabled the application stack can be located in L1
818 scratch memory (less latency).
820 Currently only works with FLAT binaries.
822 config EXCEPTION_L1_SCRATCH
823 bool "Locate exception stack in L1 Scratch Memory"
825 depends on !APP_STACK_L1
827 Whenever an exception occurs, use the L1 Scratch memory for
828 stack storage. You cannot place the stacks of FLAT binaries
829 in L1 when using this option.
831 If you don't use L1 Scratch, then you should say Y here.
833 comment "Speed Optimizations"
834 config BFIN_INS_LOWOVERHEAD
835 bool "ins[bwl] low overhead, higher interrupt latency"
838 Reads on the Blackfin are speculative. In Blackfin terms, this means
839 they can be interrupted at any time (even after they have been issued
840 on to the external bus), and re-issued after the interrupt occurs.
841 For memory - this is not a big deal, since memory does not change if
844 If a FIFO is sitting on the end of the read, it will see two reads,
845 when the core only sees one since the FIFO receives both the read
846 which is cancelled (and not delivered to the core) and the one which
847 is re-issued (which is delivered to the core).
849 To solve this, interrupts are turned off before reads occur to
850 I/O space. This option controls which the overhead/latency of
851 controlling interrupts during this time
852 "n" turns interrupts off every read
853 (higher overhead, but lower interrupt latency)
854 "y" turns interrupts off every loop
855 (low overhead, but longer interrupt latency)
857 default behavior is to leave this set to on (type "Y"). If you are experiencing
858 interrupt latency issues, it is safe and OK to turn this off.
863 prompt "Kernel executes from"
865 Choose the memory type that the kernel will be running in.
870 The kernel will be resident in RAM when running.
875 The kernel will be resident in FLASH/ROM when running.
882 tristate "Enable Blackfin General Purpose Timers API"
885 Enable support for the General Purpose Timers API. If you
888 To compile this driver as a module, choose M here: the module
889 will be called gptimers.ko.
892 prompt "Uncached DMA region"
893 default DMA_UNCACHED_1M
894 config DMA_UNCACHED_4M
895 bool "Enable 4M DMA region"
896 config DMA_UNCACHED_2M
897 bool "Enable 2M DMA region"
898 config DMA_UNCACHED_1M
899 bool "Enable 1M DMA region"
900 config DMA_UNCACHED_NONE
901 bool "Disable DMA region"
905 comment "Cache Support"
910 config BFIN_DCACHE_BANKA
911 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
912 depends on BFIN_DCACHE && !BF531
914 config BFIN_ICACHE_LOCK
915 bool "Enable Instruction Cache Locking"
918 prompt "External memory cache policy"
919 depends on BFIN_DCACHE
920 default BFIN_WB if !SMP
921 default BFIN_WT if SMP
927 Cached data will be written back to SDRAM only when needed.
928 This can give a nice increase in performance, but beware of
929 broken drivers that do not properly invalidate/flush their
932 Write Through Policy:
933 Cached data will always be written back to SDRAM when the
934 cache is updated. This is a completely safe setting, but
935 performance is worse than Write Back.
937 If you are unsure of the options and you want to be safe,
938 then go with Write Through.
944 Cached data will be written back to SDRAM only when needed.
945 This can give a nice increase in performance, but beware of
946 broken drivers that do not properly invalidate/flush their
949 Write Through Policy:
950 Cached data will always be written back to SDRAM when the
951 cache is updated. This is a completely safe setting, but
952 performance is worse than Write Back.
954 If you are unsure of the options and you want to be safe,
955 then go with Write Through.
960 prompt "L2 SRAM cache policy"
961 depends on (BF54x || BF561)
971 config BFIN_L2_NOT_CACHED
977 bool "Enable the memory protection unit (EXPERIMENTAL)"
980 Use the processor's MPU to protect applications from accessing
981 memory they do not own. This comes at a performance penalty
982 and is recommended only for debugging.
984 comment "Asynchronous Memory Configuration"
986 menu "EBIU_AMGCTL Global Control"
992 bool "DMA has priority over core for ext. accesses"
997 bool "Bank 0 16 bit packing enable"
1002 bool "Bank 1 16 bit packing enable"
1007 bool "Bank 2 16 bit packing enable"
1012 bool "Bank 3 16 bit packing enable"
1016 prompt "Enable Asynchronous Memory Banks"
1020 bool "Disable All Banks"
1023 bool "Enable Bank 0"
1025 config C_AMBEN_B0_B1
1026 bool "Enable Bank 0 & 1"
1028 config C_AMBEN_B0_B1_B2
1029 bool "Enable Bank 0 & 1 & 2"
1032 bool "Enable All Banks"
1036 menu "EBIU_AMBCTL Control"
1038 hex "Bank 0 (AMBCTL0.L)"
1041 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1042 used to control the Asynchronous Memory Bank 0 settings.
1045 hex "Bank 1 (AMBCTL0.H)"
1047 default 0x5558 if BF54x
1049 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1050 used to control the Asynchronous Memory Bank 1 settings.
1053 hex "Bank 2 (AMBCTL1.L)"
1056 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1057 used to control the Asynchronous Memory Bank 2 settings.
1060 hex "Bank 3 (AMBCTL1.H)"
1063 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1064 used to control the Asynchronous Memory Bank 3 settings.
1068 config EBIU_MBSCTLVAL
1069 hex "EBIU Bank Select Control Register"
1074 hex "Flash Memory Mode Control Register"
1079 hex "Flash Memory Bank Control Register"
1084 #############################################################################
1085 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1091 Support for PCI bus.
1093 source "drivers/pci/Kconfig"
1096 bool "Support for hot-pluggable device"
1098 Say Y here if you want to plug devices into your computer while
1099 the system is running, and be able to use them quickly. In many
1100 cases, the devices can likewise be unplugged at any time too.
1102 One well known example of this is PCMCIA- or PC-cards, credit-card
1103 size devices such as network cards, modems or hard drives which are
1104 plugged into slots found on all modern laptop computers. Another
1105 example, used on modern desktops as well as laptops, is USB.
1107 Enable HOTPLUG and build a modular kernel. Get agent software
1108 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1109 Then your kernel will automatically call out to a user mode "policy
1110 agent" (/sbin/hotplug) to load modules and set up software needed
1111 to use devices as you hotplug them.
1113 source "drivers/pcmcia/Kconfig"
1115 source "drivers/pci/hotplug/Kconfig"
1119 menu "Executable file formats"
1121 source "fs/Kconfig.binfmt"
1125 menu "Power management options"
1126 source "kernel/power/Kconfig"
1128 config ARCH_SUSPEND_POSSIBLE
1133 prompt "Standby Power Saving Mode"
1135 default PM_BFIN_SLEEP_DEEPER
1136 config PM_BFIN_SLEEP_DEEPER
1139 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1140 power dissipation by disabling the clock to the processor core (CCLK).
1141 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1142 to 0.85 V to provide the greatest power savings, while preserving the
1144 The PLL and system clock (SCLK) continue to operate at a very low
1145 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1146 the SDRAM is put into Self Refresh Mode. Typically an external event
1147 such as GPIO interrupt or RTC activity wakes up the processor.
1148 Various Peripherals such as UART, SPORT, PPI may not function as
1149 normal during Sleep Deeper, due to the reduced SCLK frequency.
1150 When in the sleep mode, system DMA access to L1 memory is not supported.
1152 If unsure, select "Sleep Deeper".
1154 config PM_BFIN_SLEEP
1157 Sleep Mode (High Power Savings) - The sleep mode reduces power
1158 dissipation by disabling the clock to the processor core (CCLK).
1159 The PLL and system clock (SCLK), however, continue to operate in
1160 this mode. Typically an external event or RTC activity will wake
1161 up the processor. When in the sleep mode, system DMA access to L1
1162 memory is not supported.
1164 If unsure, select "Sleep Deeper".
1167 config PM_WAKEUP_BY_GPIO
1168 bool "Allow Wakeup from Standby by GPIO"
1169 depends on PM && !BF54x
1171 config PM_WAKEUP_GPIO_NUMBER
1174 depends on PM_WAKEUP_BY_GPIO
1178 prompt "GPIO Polarity"
1179 depends on PM_WAKEUP_BY_GPIO
1180 default PM_WAKEUP_GPIO_POLAR_H
1181 config PM_WAKEUP_GPIO_POLAR_H
1183 config PM_WAKEUP_GPIO_POLAR_L
1185 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1187 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1189 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1193 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1196 config PM_BFIN_WAKE_PH6
1197 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1198 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1201 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1203 config PM_BFIN_WAKE_GP
1204 bool "Allow Wake-Up from GPIOs"
1205 depends on PM && BF54x
1208 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1209 (all processors, except ADSP-BF549). This option sets
1210 the general-purpose wake-up enable (GPWE) control bit to enable
1211 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1212 On ADSP-BF549 this option enables the the same functionality on the
1213 /MRXON pin also PH7.
1217 menu "CPU Frequency scaling"
1219 source "drivers/cpufreq/Kconfig"
1221 config BFIN_CPU_FREQ
1224 select CPU_FREQ_TABLE
1228 bool "CPU Voltage scaling"
1229 depends on EXPERIMENTAL
1233 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1234 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1235 manuals. There is a theoretical risk that during VDDINT transitions
1240 source "net/Kconfig"
1242 source "drivers/Kconfig"
1246 source "arch/blackfin/Kconfig.debug"
1248 source "security/Kconfig"
1250 source "crypto/Kconfig"
1252 source "lib/Kconfig"