2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
29 select ARCH_WANT_OPTIONAL_GPIOLIB
35 config GENERIC_FIND_NEXT_BIT
39 config GENERIC_HWEIGHT
43 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
55 config FORCE_MAX_ZONEORDER
59 config GENERIC_CALIBRATE_DELAY
69 source "kernel/Kconfig.preempt"
71 source "kernel/Kconfig.freezer"
73 menu "Blackfin Processor Options"
75 comment "Processor and Board Settings"
84 BF512 Processor Support.
89 BF514 Processor Support.
94 BF516 Processor Support.
99 BF518 Processor Support.
104 BF522 Processor Support.
109 BF523 Processor Support.
114 BF524 Processor Support.
119 BF525 Processor Support.
124 BF526 Processor Support.
129 BF527 Processor Support.
134 BF531 Processor Support.
139 BF532 Processor Support.
144 BF533 Processor Support.
149 BF534 Processor Support.
154 BF536 Processor Support.
159 BF537 Processor Support.
164 BF538 Processor Support.
169 BF539 Processor Support.
174 BF542 Processor Support.
179 BF544 Processor Support.
184 BF547 Processor Support.
189 BF548 Processor Support.
194 BF549 Processor Support.
199 BF561 Processor Support.
205 default 0 if (BF51x || BF52x || BF54x)
206 default 2 if (BF537 || BF536 || BF534)
207 default 3 if (BF561 ||BF533 || BF532 || BF531)
208 default 4 if (BF538 || BF539)
212 default 2 if (BF51x || BF52x || BF54x)
213 default 3 if (BF537 || BF536 || BF534)
214 default 5 if (BF561 || BF538 || BF539)
215 default 6 if (BF533 || BF532 || BF531)
219 default BF_REV_0_1 if (BF51x || BF52x || BF54x)
220 default BF_REV_0_2 if (BF534 || BF536 || BF537)
221 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
225 depends on (BF51x || BF52x || BF54x)
229 depends on (BF52x || BF54x)
233 depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
237 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
241 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
245 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
249 depends on (BF533 || BF532 || BF531)
261 depends on (BF512 || BF514 || BF516 || BF518)
266 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
271 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
276 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
279 config MEM_GENERIC_BOARD
281 depends on GENERIC_BOARD
284 config MEM_MT48LC64M4A2FB_7E
286 depends on (BFIN533_STAMP)
289 config MEM_MT48LC16M16A2TG_75
291 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
292 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
293 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
296 config MEM_MT48LC32M8A2_75
298 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
301 config MEM_MT48LC8M32B2B5_7
303 depends on (BFIN561_BLUETECHNIX_CM)
306 config MEM_MT48LC32M16A2TG_75
308 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
311 source "arch/blackfin/mach-bf518/Kconfig"
312 source "arch/blackfin/mach-bf527/Kconfig"
313 source "arch/blackfin/mach-bf533/Kconfig"
314 source "arch/blackfin/mach-bf561/Kconfig"
315 source "arch/blackfin/mach-bf537/Kconfig"
316 source "arch/blackfin/mach-bf538/Kconfig"
317 source "arch/blackfin/mach-bf548/Kconfig"
319 menu "Board customizations"
322 bool "Default bootloader kernel arguments"
325 string "Initial kernel command string"
326 depends on CMDLINE_BOOL
327 default "console=ttyBF0,57600"
329 If you don't have a boot loader capable of passing a command line string
330 to the kernel, you may specify one here. As a minimum, you should specify
331 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
334 hex "Kernel load address for booting"
336 range 0x1000 0x20000000
338 This option allows you to set the load address of the kernel.
339 This can be useful if you are on a board which has a small amount
340 of memory or you wish to reserve some memory at the beginning of
343 Note that you need to keep this value above 4k (0x1000) as this
344 memory region is used to capture NULL pointer references as well
345 as some core kernel functions.
348 hex "Kernel ROM Base"
350 range 0x20000000 0x20400000 if !(BF54x || BF561)
351 range 0x20000000 0x30000000 if (BF54x || BF561)
354 comment "Clock/PLL Setup"
357 int "Frequency of the crystal on the board in Hz"
358 default "11059200" if BFIN533_STAMP
359 default "27000000" if BFIN533_EZKIT
360 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
361 default "30000000" if BFIN561_EZKIT
362 default "24576000" if PNAV10
363 default "10000000" if BFIN532_IP0X
365 The frequency of CLKIN crystal oscillator on the board in Hz.
366 Warning: This value should match the crystal on the board. Otherwise,
367 peripherals won't work properly.
369 config BFIN_KERNEL_CLOCK
370 bool "Re-program Clocks while Kernel boots?"
373 This option decides if kernel clocks are re-programed from the
374 bootloader settings. If the clocks are not set, the SDRAM settings
375 are also not changed, and the Bootloader does 100% of the hardware
380 depends on BFIN_KERNEL_CLOCK
385 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
388 If this is set the clock will be divided by 2, before it goes to the PLL.
392 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
394 default "22" if BFIN533_EZKIT
395 default "45" if BFIN533_STAMP
396 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
397 default "22" if BFIN533_BLUETECHNIX_CM
398 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
399 default "20" if BFIN561_EZKIT
400 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
402 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
403 PLL Frequency = (Crystal Frequency) * (this setting)
406 prompt "Core Clock Divider"
407 depends on BFIN_KERNEL_CLOCK
410 This sets the frequency of the core. It can be 1, 2, 4 or 8
411 Core Frequency = (PLL frequency) / (this setting)
427 int "System Clock Divider"
428 depends on BFIN_KERNEL_CLOCK
432 This sets the frequency of the system clock (including SDRAM or DDR).
433 This can be between 1 and 15
434 System Clock = (PLL frequency) / (this setting)
437 prompt "DDR SDRAM Chip Type"
438 depends on BFIN_KERNEL_CLOCK
440 default MEM_MT46V32M16_5B
442 config MEM_MT46V32M16_6T
445 config MEM_MT46V32M16_5B
450 int "Max SDRAM Memory Size in MBytes"
454 This is the max memory size that the kernel will create CPLB
455 tables for. Your system will not be able to handle any more.
458 # Max & Min Speeds for various Chips
462 default 400000000 if BF512
463 default 400000000 if BF514
464 default 400000000 if BF516
465 default 400000000 if BF518
466 default 600000000 if BF522
467 default 400000000 if BF523
468 default 400000000 if BF524
469 default 600000000 if BF525
470 default 400000000 if BF526
471 default 600000000 if BF527
472 default 400000000 if BF531
473 default 400000000 if BF532
474 default 750000000 if BF533
475 default 500000000 if BF534
476 default 400000000 if BF536
477 default 600000000 if BF537
478 default 533333333 if BF538
479 default 533333333 if BF539
480 default 600000000 if BF542
481 default 533333333 if BF544
482 default 600000000 if BF547
483 default 600000000 if BF548
484 default 533333333 if BF549
485 default 600000000 if BF561
499 comment "Kernel Timer/Scheduler"
501 source kernel/Kconfig.hz
507 config GENERIC_CLOCKEVENTS
508 bool "Generic clock events"
509 depends on GENERIC_TIME
512 config CYCLES_CLOCKSOURCE
513 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
514 depends on EXPERIMENTAL
515 depends on GENERIC_CLOCKEVENTS
516 depends on !BFIN_SCRATCH_REG_CYCLES
519 If you say Y here, you will enable support for using the 'cycles'
520 registers as a clock source. Doing so means you will be unable to
521 safely write to the 'cycles' register during runtime. You will
522 still be able to read it (such as for performance monitoring), but
523 writing the registers will most likely crash the kernel.
525 source kernel/time/Kconfig
530 prompt "Blackfin Exception Scratch Register"
531 default BFIN_SCRATCH_REG_RETN
533 Select the resource to reserve for the Exception handler:
534 - RETN: Non-Maskable Interrupt (NMI)
535 - RETE: Exception Return (JTAG/ICE)
536 - CYCLES: Performance counter
538 If you are unsure, please select "RETN".
540 config BFIN_SCRATCH_REG_RETN
543 Use the RETN register in the Blackfin exception handler
544 as a stack scratch register. This means you cannot
545 safely use NMI on the Blackfin while running Linux, but
546 you can debug the system with a JTAG ICE and use the
547 CYCLES performance registers.
549 If you are unsure, please select "RETN".
551 config BFIN_SCRATCH_REG_RETE
554 Use the RETE register in the Blackfin exception handler
555 as a stack scratch register. This means you cannot
556 safely use a JTAG ICE while debugging a Blackfin board,
557 but you can safely use the CYCLES performance registers
560 If you are unsure, please select "RETN".
562 config BFIN_SCRATCH_REG_CYCLES
565 Use the CYCLES register in the Blackfin exception handler
566 as a stack scratch register. This means you cannot
567 safely use the CYCLES performance registers on a Blackfin
568 board at anytime, but you can debug the system with a JTAG
571 If you are unsure, please select "RETN".
578 menu "Blackfin Kernel Optimizations"
580 comment "Memory Optimizations"
583 bool "Locate interrupt entry code in L1 Memory"
586 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
587 into L1 instruction memory. (less latency)
589 config EXCPT_IRQ_SYSC_L1
590 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
593 If enabled, the entire ASM lowlevel exception and interrupt entry code
594 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
598 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
601 If enabled, the frequently called do_irq dispatcher function is linked
602 into L1 instruction memory. (less latency)
604 config CORE_TIMER_IRQ_L1
605 bool "Locate frequently called timer_interrupt() function in L1 Memory"
608 If enabled, the frequently called timer_interrupt() function is linked
609 into L1 instruction memory. (less latency)
612 bool "Locate frequently idle function in L1 Memory"
615 If enabled, the frequently called idle function is linked
616 into L1 instruction memory. (less latency)
619 bool "Locate kernel schedule function in L1 Memory"
622 If enabled, the frequently called kernel schedule is linked
623 into L1 instruction memory. (less latency)
625 config ARITHMETIC_OPS_L1
626 bool "Locate kernel owned arithmetic functions in L1 Memory"
629 If enabled, arithmetic functions are linked
630 into L1 instruction memory. (less latency)
633 bool "Locate access_ok function in L1 Memory"
636 If enabled, the access_ok function is linked
637 into L1 instruction memory. (less latency)
640 bool "Locate memset function in L1 Memory"
643 If enabled, the memset function is linked
644 into L1 instruction memory. (less latency)
647 bool "Locate memcpy function in L1 Memory"
650 If enabled, the memcpy function is linked
651 into L1 instruction memory. (less latency)
653 config SYS_BFIN_SPINLOCK_L1
654 bool "Locate sys_bfin_spinlock function in L1 Memory"
657 If enabled, sys_bfin_spinlock function is linked
658 into L1 instruction memory. (less latency)
660 config IP_CHECKSUM_L1
661 bool "Locate IP Checksum function in L1 Memory"
664 If enabled, the IP Checksum function is linked
665 into L1 instruction memory. (less latency)
667 config CACHELINE_ALIGNED_L1
668 bool "Locate cacheline_aligned data to L1 Data Memory"
673 If enabled, cacheline_anligned data is linked
674 into L1 data memory. (less latency)
676 config SYSCALL_TAB_L1
677 bool "Locate Syscall Table L1 Data Memory"
681 If enabled, the Syscall LUT is linked
682 into L1 data memory. (less latency)
684 config CPLB_SWITCH_TAB_L1
685 bool "Locate CPLB Switch Tables L1 Data Memory"
689 If enabled, the CPLB Switch Tables are linked
690 into L1 data memory. (less latency)
693 bool "Support locating application stack in L1 Scratch Memory"
696 If enabled the application stack can be located in L1
697 scratch memory (less latency).
699 Currently only works with FLAT binaries.
701 config EXCEPTION_L1_SCRATCH
702 bool "Locate exception stack in L1 Scratch Memory"
704 depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
706 Whenever an exception occurs, use the L1 Scratch memory for
707 stack storage. You cannot place the stacks of FLAT binaries
708 in L1 when using this option.
710 If you don't use L1 Scratch, then you should say Y here.
712 comment "Speed Optimizations"
713 config BFIN_INS_LOWOVERHEAD
714 bool "ins[bwl] low overhead, higher interrupt latency"
717 Reads on the Blackfin are speculative. In Blackfin terms, this means
718 they can be interrupted at any time (even after they have been issued
719 on to the external bus), and re-issued after the interrupt occurs.
720 For memory - this is not a big deal, since memory does not change if
723 If a FIFO is sitting on the end of the read, it will see two reads,
724 when the core only sees one since the FIFO receives both the read
725 which is cancelled (and not delivered to the core) and the one which
726 is re-issued (which is delivered to the core).
728 To solve this, interrupts are turned off before reads occur to
729 I/O space. This option controls which the overhead/latency of
730 controlling interrupts during this time
731 "n" turns interrupts off every read
732 (higher overhead, but lower interrupt latency)
733 "y" turns interrupts off every loop
734 (low overhead, but longer interrupt latency)
736 default behavior is to leave this set to on (type "Y"). If you are experiencing
737 interrupt latency issues, it is safe and OK to turn this off.
743 prompt "Kernel executes from"
745 Choose the memory type that the kernel will be running in.
750 The kernel will be resident in RAM when running.
755 The kernel will be resident in FLASH/ROM when running.
762 tristate "Enable Blackfin General Purpose Timers API"
765 Enable support for the General Purpose Timers API. If you
768 To compile this driver as a module, choose M here: the module
769 will be called gptimers.ko.
772 bool "Enable DMA Support"
775 DMA driver for Blackfin parts.
778 prompt "Uncached DMA region"
779 default DMA_UNCACHED_1M
780 depends on BFIN_DMA_5XX
781 config DMA_UNCACHED_4M
782 bool "Enable 4M DMA region"
783 config DMA_UNCACHED_2M
784 bool "Enable 2M DMA region"
785 config DMA_UNCACHED_1M
786 bool "Enable 1M DMA region"
787 config DMA_UNCACHED_NONE
788 bool "Disable DMA region"
792 comment "Cache Support"
797 config BFIN_DCACHE_BANKA
798 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
799 depends on BFIN_DCACHE && !BF531
801 config BFIN_ICACHE_LOCK
802 bool "Enable Instruction Cache Locking"
806 depends on BFIN_DCACHE
812 Cached data will be written back to SDRAM only when needed.
813 This can give a nice increase in performance, but beware of
814 broken drivers that do not properly invalidate/flush their
817 Write Through Policy:
818 Cached data will always be written back to SDRAM when the
819 cache is updated. This is a completely safe setting, but
820 performance is worse than Write Back.
822 If you are unsure of the options and you want to be safe,
823 then go with Write Through.
829 Cached data will be written back to SDRAM only when needed.
830 This can give a nice increase in performance, but beware of
831 broken drivers that do not properly invalidate/flush their
834 Write Through Policy:
835 Cached data will always be written back to SDRAM when the
836 cache is updated. This is a completely safe setting, but
837 performance is worse than Write Back.
839 If you are unsure of the options and you want to be safe,
840 then go with Write Through.
844 config BFIN_L2_CACHEABLE
846 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
849 Select to make L2 SRAM cacheable in L1 data and instruction cache.
852 bool "Enable the memory protection unit (EXPERIMENTAL)"
855 Use the processor's MPU to protect applications from accessing
856 memory they do not own. This comes at a performance penalty
857 and is recommended only for debugging.
859 comment "Asynchonous Memory Configuration"
861 menu "EBIU_AMGCTL Global Control"
867 bool "DMA has priority over core for ext. accesses"
872 bool "Bank 0 16 bit packing enable"
877 bool "Bank 1 16 bit packing enable"
882 bool "Bank 2 16 bit packing enable"
887 bool "Bank 3 16 bit packing enable"
891 prompt"Enable Asynchonous Memory Banks"
895 bool "Disable All Banks"
901 bool "Enable Bank 0 & 1"
903 config C_AMBEN_B0_B1_B2
904 bool "Enable Bank 0 & 1 & 2"
907 bool "Enable All Banks"
911 menu "EBIU_AMBCTL Control"
919 default 0x5558 if BF54x
930 config EBIU_MBSCTLVAL
931 hex "EBIU Bank Select Control Register"
936 hex "Flash Memory Mode Control Register"
941 hex "Flash Memory Bank Control Register"
946 #############################################################################
947 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
955 source "drivers/pci/Kconfig"
958 bool "Support for hot-pluggable device"
960 Say Y here if you want to plug devices into your computer while
961 the system is running, and be able to use them quickly. In many
962 cases, the devices can likewise be unplugged at any time too.
964 One well known example of this is PCMCIA- or PC-cards, credit-card
965 size devices such as network cards, modems or hard drives which are
966 plugged into slots found on all modern laptop computers. Another
967 example, used on modern desktops as well as laptops, is USB.
969 Enable HOTPLUG and build a modular kernel. Get agent software
970 (from <http://linux-hotplug.sourceforge.net/>) and install it.
971 Then your kernel will automatically call out to a user mode "policy
972 agent" (/sbin/hotplug) to load modules and set up software needed
973 to use devices as you hotplug them.
975 source "drivers/pcmcia/Kconfig"
977 source "drivers/pci/hotplug/Kconfig"
981 menu "Executable file formats"
983 source "fs/Kconfig.binfmt"
987 menu "Power management options"
988 source "kernel/power/Kconfig"
990 config ARCH_SUSPEND_POSSIBLE
995 prompt "Standby Power Saving Mode"
997 default PM_BFIN_SLEEP_DEEPER
998 config PM_BFIN_SLEEP_DEEPER
1001 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1002 power dissipation by disabling the clock to the processor core (CCLK).
1003 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1004 to 0.85 V to provide the greatest power savings, while preserving the
1006 The PLL and system clock (SCLK) continue to operate at a very low
1007 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1008 the SDRAM is put into Self Refresh Mode. Typically an external event
1009 such as GPIO interrupt or RTC activity wakes up the processor.
1010 Various Peripherals such as UART, SPORT, PPI may not function as
1011 normal during Sleep Deeper, due to the reduced SCLK frequency.
1012 When in the sleep mode, system DMA access to L1 memory is not supported.
1014 If unsure, select "Sleep Deeper".
1016 config PM_BFIN_SLEEP
1019 Sleep Mode (High Power Savings) - The sleep mode reduces power
1020 dissipation by disabling the clock to the processor core (CCLK).
1021 The PLL and system clock (SCLK), however, continue to operate in
1022 this mode. Typically an external event or RTC activity will wake
1023 up the processor. When in the sleep mode, system DMA access to L1
1024 memory is not supported.
1026 If unsure, select "Sleep Deeper".
1029 config PM_WAKEUP_BY_GPIO
1030 bool "Allow Wakeup from Standby by GPIO"
1032 config PM_WAKEUP_GPIO_NUMBER
1035 depends on PM_WAKEUP_BY_GPIO
1036 default 2 if BFIN537_STAMP
1039 prompt "GPIO Polarity"
1040 depends on PM_WAKEUP_BY_GPIO
1041 default PM_WAKEUP_GPIO_POLAR_H
1042 config PM_WAKEUP_GPIO_POLAR_H
1044 config PM_WAKEUP_GPIO_POLAR_L
1046 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1048 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1050 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1054 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1057 config PM_BFIN_WAKE_PH6
1058 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1059 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1062 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1064 config PM_BFIN_WAKE_GP
1065 bool "Allow Wake-Up from GPIOs"
1066 depends on PM && BF54x
1069 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1072 menu "CPU Frequency scaling"
1074 source "drivers/cpufreq/Kconfig"
1077 bool "CPU Voltage scaling"
1078 depends on EXPERIMENTAL
1082 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1083 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1084 manuals. There is a theoretical risk that during VDDINT transitions
1089 source "net/Kconfig"
1091 source "drivers/Kconfig"
1095 source "arch/blackfin/Kconfig.debug"
1097 source "security/Kconfig"
1099 source "crypto/Kconfig"
1101 source "lib/Kconfig"