2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
68 source "kernel/Kconfig.preempt"
70 source "kernel/Kconfig.freezer"
72 menu "Blackfin Processor Options"
74 comment "Processor and Board Settings"
83 BF522 Processor Support.
88 BF523 Processor Support.
93 BF524 Processor Support.
98 BF525 Processor Support.
103 BF526 Processor Support.
108 BF527 Processor Support.
113 BF531 Processor Support.
118 BF532 Processor Support.
123 BF533 Processor Support.
128 BF534 Processor Support.
133 BF536 Processor Support.
138 BF537 Processor Support.
143 BF542 Processor Support.
148 BF544 Processor Support.
153 BF547 Processor Support.
158 BF548 Processor Support.
163 BF549 Processor Support.
168 BF561 Processor Support.
174 default 0 if (BF52x || BF54x)
175 default 2 if (BF537 || BF536 || BF534)
176 default 3 if (BF561 ||BF533 || BF532 || BF531)
180 default 2 if (BF52x || BF54x)
181 default 3 if (BF537 || BF536 || BF534)
183 default 6 if (BF533 || BF532 || BF531)
187 default BF_REV_0_1 if (BF52x || BF54x)
188 default BF_REV_0_2 if (BF534 || BF536 || BF537)
189 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
193 depends on (BF52x || BF54x)
197 depends on (BF52x || BF54x)
201 depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
205 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
209 depends on (BF561 || BF533 || BF532 || BF531)
213 depends on (BF561 || BF533 || BF532 || BF531)
217 depends on (BF533 || BF532 || BF531)
229 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
234 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
239 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
242 config MEM_GENERIC_BOARD
244 depends on GENERIC_BOARD
247 config MEM_MT48LC64M4A2FB_7E
249 depends on (BFIN533_STAMP)
252 config MEM_MT48LC16M16A2TG_75
254 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
255 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
256 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
259 config MEM_MT48LC32M8A2_75
261 depends on (BFIN537_STAMP || PNAV10)
264 config MEM_MT48LC8M32B2B5_7
266 depends on (BFIN561_BLUETECHNIX_CM)
269 config MEM_MT48LC32M16A2TG_75
271 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
274 source "arch/blackfin/mach-bf527/Kconfig"
275 source "arch/blackfin/mach-bf533/Kconfig"
276 source "arch/blackfin/mach-bf561/Kconfig"
277 source "arch/blackfin/mach-bf537/Kconfig"
278 source "arch/blackfin/mach-bf548/Kconfig"
280 menu "Board customizations"
283 bool "Default bootloader kernel arguments"
286 string "Initial kernel command string"
287 depends on CMDLINE_BOOL
288 default "console=ttyBF0,57600"
290 If you don't have a boot loader capable of passing a command line string
291 to the kernel, you may specify one here. As a minimum, you should specify
292 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
295 hex "Kernel load address for booting"
297 range 0x1000 0x20000000
299 This option allows you to set the load address of the kernel.
300 This can be useful if you are on a board which has a small amount
301 of memory or you wish to reserve some memory at the beginning of
304 Note that you need to keep this value above 4k (0x1000) as this
305 memory region is used to capture NULL pointer references as well
306 as some core kernel functions.
309 hex "Kernel ROM Base"
311 range 0x20000000 0x20400000 if !(BF54x || BF561)
312 range 0x20000000 0x30000000 if (BF54x || BF561)
315 comment "Clock/PLL Setup"
318 int "Frequency of the crystal on the board in Hz"
319 default "11059200" if BFIN533_STAMP
320 default "27000000" if BFIN533_EZKIT
321 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
322 default "30000000" if BFIN561_EZKIT
323 default "24576000" if PNAV10
324 default "10000000" if BFIN532_IP0X
326 The frequency of CLKIN crystal oscillator on the board in Hz.
327 Warning: This value should match the crystal on the board. Otherwise,
328 peripherals won't work properly.
330 config BFIN_KERNEL_CLOCK
331 bool "Re-program Clocks while Kernel boots?"
334 This option decides if kernel clocks are re-programed from the
335 bootloader settings. If the clocks are not set, the SDRAM settings
336 are also not changed, and the Bootloader does 100% of the hardware
341 depends on BFIN_KERNEL_CLOCK
346 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
349 If this is set the clock will be divided by 2, before it goes to the PLL.
353 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
355 default "22" if BFIN533_EZKIT
356 default "45" if BFIN533_STAMP
357 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
358 default "22" if BFIN533_BLUETECHNIX_CM
359 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
360 default "20" if BFIN561_EZKIT
361 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
363 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
364 PLL Frequency = (Crystal Frequency) * (this setting)
367 prompt "Core Clock Divider"
368 depends on BFIN_KERNEL_CLOCK
371 This sets the frequency of the core. It can be 1, 2, 4 or 8
372 Core Frequency = (PLL frequency) / (this setting)
388 int "System Clock Divider"
389 depends on BFIN_KERNEL_CLOCK
393 This sets the frequency of the system clock (including SDRAM or DDR).
394 This can be between 1 and 15
395 System Clock = (PLL frequency) / (this setting)
398 prompt "DDR SDRAM Chip Type"
399 depends on BFIN_KERNEL_CLOCK
401 default MEM_MT46V32M16_5B
403 config MEM_MT46V32M16_6T
406 config MEM_MT46V32M16_5B
411 int "Max SDRAM Memory Size in MBytes"
415 This is the max memory size that the kernel will create CPLB
416 tables for. Your system will not be able to handle any more.
419 # Max & Min Speeds for various Chips
423 default 600000000 if BF522
424 default 400000000 if BF523
425 default 400000000 if BF524
426 default 600000000 if BF525
427 default 400000000 if BF526
428 default 600000000 if BF527
429 default 400000000 if BF531
430 default 400000000 if BF532
431 default 750000000 if BF533
432 default 500000000 if BF534
433 default 400000000 if BF536
434 default 600000000 if BF537
435 default 533333333 if BF538
436 default 533333333 if BF539
437 default 600000000 if BF542
438 default 533333333 if BF544
439 default 600000000 if BF547
440 default 600000000 if BF548
441 default 533333333 if BF549
442 default 600000000 if BF561
456 comment "Kernel Timer/Scheduler"
458 source kernel/Kconfig.hz
464 config GENERIC_CLOCKEVENTS
465 bool "Generic clock events"
466 depends on GENERIC_TIME
469 config CYCLES_CLOCKSOURCE
470 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
471 depends on EXPERIMENTAL
472 depends on GENERIC_CLOCKEVENTS
473 depends on !BFIN_SCRATCH_REG_CYCLES
476 If you say Y here, you will enable support for using the 'cycles'
477 registers as a clock source. Doing so means you will be unable to
478 safely write to the 'cycles' register during runtime. You will
479 still be able to read it (such as for performance monitoring), but
480 writing the registers will most likely crash the kernel.
482 source kernel/time/Kconfig
487 prompt "Blackfin Exception Scratch Register"
488 default BFIN_SCRATCH_REG_RETN
490 Select the resource to reserve for the Exception handler:
491 - RETN: Non-Maskable Interrupt (NMI)
492 - RETE: Exception Return (JTAG/ICE)
493 - CYCLES: Performance counter
495 If you are unsure, please select "RETN".
497 config BFIN_SCRATCH_REG_RETN
500 Use the RETN register in the Blackfin exception handler
501 as a stack scratch register. This means you cannot
502 safely use NMI on the Blackfin while running Linux, but
503 you can debug the system with a JTAG ICE and use the
504 CYCLES performance registers.
506 If you are unsure, please select "RETN".
508 config BFIN_SCRATCH_REG_RETE
511 Use the RETE register in the Blackfin exception handler
512 as a stack scratch register. This means you cannot
513 safely use a JTAG ICE while debugging a Blackfin board,
514 but you can safely use the CYCLES performance registers
517 If you are unsure, please select "RETN".
519 config BFIN_SCRATCH_REG_CYCLES
522 Use the CYCLES register in the Blackfin exception handler
523 as a stack scratch register. This means you cannot
524 safely use the CYCLES performance registers on a Blackfin
525 board at anytime, but you can debug the system with a JTAG
528 If you are unsure, please select "RETN".
535 menu "Blackfin Kernel Optimizations"
537 comment "Memory Optimizations"
540 bool "Locate interrupt entry code in L1 Memory"
543 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
544 into L1 instruction memory. (less latency)
546 config EXCPT_IRQ_SYSC_L1
547 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
550 If enabled, the entire ASM lowlevel exception and interrupt entry code
551 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
555 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
558 If enabled, the frequently called do_irq dispatcher function is linked
559 into L1 instruction memory. (less latency)
561 config CORE_TIMER_IRQ_L1
562 bool "Locate frequently called timer_interrupt() function in L1 Memory"
565 If enabled, the frequently called timer_interrupt() function is linked
566 into L1 instruction memory. (less latency)
569 bool "Locate frequently idle function in L1 Memory"
572 If enabled, the frequently called idle function is linked
573 into L1 instruction memory. (less latency)
576 bool "Locate kernel schedule function in L1 Memory"
579 If enabled, the frequently called kernel schedule is linked
580 into L1 instruction memory. (less latency)
582 config ARITHMETIC_OPS_L1
583 bool "Locate kernel owned arithmetic functions in L1 Memory"
586 If enabled, arithmetic functions are linked
587 into L1 instruction memory. (less latency)
590 bool "Locate access_ok function in L1 Memory"
593 If enabled, the access_ok function is linked
594 into L1 instruction memory. (less latency)
597 bool "Locate memset function in L1 Memory"
600 If enabled, the memset function is linked
601 into L1 instruction memory. (less latency)
604 bool "Locate memcpy function in L1 Memory"
607 If enabled, the memcpy function is linked
608 into L1 instruction memory. (less latency)
610 config SYS_BFIN_SPINLOCK_L1
611 bool "Locate sys_bfin_spinlock function in L1 Memory"
614 If enabled, sys_bfin_spinlock function is linked
615 into L1 instruction memory. (less latency)
617 config IP_CHECKSUM_L1
618 bool "Locate IP Checksum function in L1 Memory"
621 If enabled, the IP Checksum function is linked
622 into L1 instruction memory. (less latency)
624 config CACHELINE_ALIGNED_L1
625 bool "Locate cacheline_aligned data to L1 Data Memory"
630 If enabled, cacheline_anligned data is linked
631 into L1 data memory. (less latency)
633 config SYSCALL_TAB_L1
634 bool "Locate Syscall Table L1 Data Memory"
638 If enabled, the Syscall LUT is linked
639 into L1 data memory. (less latency)
641 config CPLB_SWITCH_TAB_L1
642 bool "Locate CPLB Switch Tables L1 Data Memory"
646 If enabled, the CPLB Switch Tables are linked
647 into L1 data memory. (less latency)
650 bool "Support locating application stack in L1 Scratch Memory"
653 If enabled the application stack can be located in L1
654 scratch memory (less latency).
656 Currently only works with FLAT binaries.
658 comment "Speed Optimizations"
659 config BFIN_INS_LOWOVERHEAD
660 bool "ins[bwl] low overhead, higher interrupt latency"
663 Reads on the Blackfin are speculative. In Blackfin terms, this means
664 they can be interrupted at any time (even after they have been issued
665 on to the external bus), and re-issued after the interrupt occurs.
666 For memory - this is not a big deal, since memory does not change if
669 If a FIFO is sitting on the end of the read, it will see two reads,
670 when the core only sees one since the FIFO receives both the read
671 which is cancelled (and not delivered to the core) and the one which
672 is re-issued (which is delivered to the core).
674 To solve this, interrupts are turned off before reads occur to
675 I/O space. This option controls which the overhead/latency of
676 controlling interrupts during this time
677 "n" turns interrupts off every read
678 (higher overhead, but lower interrupt latency)
679 "y" turns interrupts off every loop
680 (low overhead, but longer interrupt latency)
682 default behavior is to leave this set to on (type "Y"). If you are experiencing
683 interrupt latency issues, it is safe and OK to turn this off.
689 prompt "Kernel executes from"
691 Choose the memory type that the kernel will be running in.
696 The kernel will be resident in RAM when running.
701 The kernel will be resident in FLASH/ROM when running.
708 tristate "Enable Blackfin General Purpose Timers API"
711 Enable support for the General Purpose Timers API. If you
714 To compile this driver as a module, choose M here: the module
715 will be called gptimers.ko.
718 bool "Enable DMA Support"
719 depends on (BF52x || BF53x || BF561 || BF54x)
722 DMA driver for BF5xx.
725 prompt "Uncached SDRAM region"
726 default DMA_UNCACHED_1M
727 depends on BFIN_DMA_5XX
728 config DMA_UNCACHED_4M
729 bool "Enable 4M DMA region"
730 config DMA_UNCACHED_2M
731 bool "Enable 2M DMA region"
732 config DMA_UNCACHED_1M
733 bool "Enable 1M DMA region"
734 config DMA_UNCACHED_NONE
735 bool "Disable DMA region"
739 comment "Cache Support"
744 config BFIN_DCACHE_BANKA
745 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
746 depends on BFIN_DCACHE && !BF531
748 config BFIN_ICACHE_LOCK
749 bool "Enable Instruction Cache Locking"
753 depends on BFIN_DCACHE
759 Cached data will be written back to SDRAM only when needed.
760 This can give a nice increase in performance, but beware of
761 broken drivers that do not properly invalidate/flush their
764 Write Through Policy:
765 Cached data will always be written back to SDRAM when the
766 cache is updated. This is a completely safe setting, but
767 performance is worse than Write Back.
769 If you are unsure of the options and you want to be safe,
770 then go with Write Through.
776 Cached data will be written back to SDRAM only when needed.
777 This can give a nice increase in performance, but beware of
778 broken drivers that do not properly invalidate/flush their
781 Write Through Policy:
782 Cached data will always be written back to SDRAM when the
783 cache is updated. This is a completely safe setting, but
784 performance is worse than Write Back.
786 If you are unsure of the options and you want to be safe,
787 then go with Write Through.
791 config BFIN_L2_CACHEABLE
793 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
796 Select to make L2 SRAM cacheable in L1 data and instruction cache.
799 bool "Enable the memory protection unit (EXPERIMENTAL)"
802 Use the processor's MPU to protect applications from accessing
803 memory they do not own. This comes at a performance penalty
804 and is recommended only for debugging.
806 comment "Asynchonous Memory Configuration"
808 menu "EBIU_AMGCTL Global Control"
814 bool "DMA has priority over core for ext. accesses"
819 bool "Bank 0 16 bit packing enable"
824 bool "Bank 1 16 bit packing enable"
829 bool "Bank 2 16 bit packing enable"
834 bool "Bank 3 16 bit packing enable"
838 prompt"Enable Asynchonous Memory Banks"
842 bool "Disable All Banks"
848 bool "Enable Bank 0 & 1"
850 config C_AMBEN_B0_B1_B2
851 bool "Enable Bank 0 & 1 & 2"
854 bool "Enable All Banks"
858 menu "EBIU_AMBCTL Control"
866 default 0x5558 if BF54x
877 config EBIU_MBSCTLVAL
878 hex "EBIU Bank Select Control Register"
883 hex "Flash Memory Mode Control Register"
888 hex "Flash Memory Bank Control Register"
893 #############################################################################
894 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
902 source "drivers/pci/Kconfig"
905 bool "Support for hot-pluggable device"
907 Say Y here if you want to plug devices into your computer while
908 the system is running, and be able to use them quickly. In many
909 cases, the devices can likewise be unplugged at any time too.
911 One well known example of this is PCMCIA- or PC-cards, credit-card
912 size devices such as network cards, modems or hard drives which are
913 plugged into slots found on all modern laptop computers. Another
914 example, used on modern desktops as well as laptops, is USB.
916 Enable HOTPLUG and build a modular kernel. Get agent software
917 (from <http://linux-hotplug.sourceforge.net/>) and install it.
918 Then your kernel will automatically call out to a user mode "policy
919 agent" (/sbin/hotplug) to load modules and set up software needed
920 to use devices as you hotplug them.
922 source "drivers/pcmcia/Kconfig"
924 source "drivers/pci/hotplug/Kconfig"
928 menu "Executable file formats"
930 source "fs/Kconfig.binfmt"
934 menu "Power management options"
935 source "kernel/power/Kconfig"
937 config ARCH_SUSPEND_POSSIBLE
942 prompt "Standby Power Saving Mode"
944 default PM_BFIN_SLEEP_DEEPER
945 config PM_BFIN_SLEEP_DEEPER
948 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
949 power dissipation by disabling the clock to the processor core (CCLK).
950 Furthermore, Standby sets the internal power supply voltage (VDDINT)
951 to 0.85 V to provide the greatest power savings, while preserving the
953 The PLL and system clock (SCLK) continue to operate at a very low
954 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
955 the SDRAM is put into Self Refresh Mode. Typically an external event
956 such as GPIO interrupt or RTC activity wakes up the processor.
957 Various Peripherals such as UART, SPORT, PPI may not function as
958 normal during Sleep Deeper, due to the reduced SCLK frequency.
959 When in the sleep mode, system DMA access to L1 memory is not supported.
961 If unsure, select "Sleep Deeper".
966 Sleep Mode (High Power Savings) - The sleep mode reduces power
967 dissipation by disabling the clock to the processor core (CCLK).
968 The PLL and system clock (SCLK), however, continue to operate in
969 this mode. Typically an external event or RTC activity will wake
970 up the processor. When in the sleep mode, system DMA access to L1
971 memory is not supported.
973 If unsure, select "Sleep Deeper".
976 config PM_WAKEUP_BY_GPIO
977 bool "Allow Wakeup from Standby by GPIO"
979 config PM_WAKEUP_GPIO_NUMBER
982 depends on PM_WAKEUP_BY_GPIO
983 default 2 if BFIN537_STAMP
986 prompt "GPIO Polarity"
987 depends on PM_WAKEUP_BY_GPIO
988 default PM_WAKEUP_GPIO_POLAR_H
989 config PM_WAKEUP_GPIO_POLAR_H
991 config PM_WAKEUP_GPIO_POLAR_L
993 config PM_WAKEUP_GPIO_POLAR_EDGE_F
995 config PM_WAKEUP_GPIO_POLAR_EDGE_R
997 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1001 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1004 config PM_BFIN_WAKE_PH6
1005 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1006 depends on PM && (BF52x || BF534 || BF536 || BF537)
1009 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1011 config PM_BFIN_WAKE_GP
1012 bool "Allow Wake-Up from GPIOs"
1013 depends on PM && BF54x
1016 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1019 menu "CPU Frequency scaling"
1021 source "drivers/cpufreq/Kconfig"
1024 bool "CPU Voltage scaling"
1025 depends on EXPERIMENTAL
1029 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1030 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1031 manuals. There is a theoretical risk that during VDDINT transitions
1036 source "net/Kconfig"
1038 source "drivers/Kconfig"
1042 source "arch/blackfin/Kconfig.debug"
1044 source "security/Kconfig"
1046 source "crypto/Kconfig"
1048 source "lib/Kconfig"