2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
29 select ARCH_WANT_OPTIONAL_GPIOLIB
35 config GENERIC_FIND_NEXT_BIT
39 config GENERIC_HWEIGHT
43 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
55 config FORCE_MAX_ZONEORDER
59 config GENERIC_CALIBRATE_DELAY
65 source "kernel/Kconfig.preempt"
67 source "kernel/Kconfig.freezer"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF512 Processor Support.
85 BF514 Processor Support.
90 BF516 Processor Support.
95 BF518 Processor Support.
100 BF522 Processor Support.
105 BF523 Processor Support.
110 BF524 Processor Support.
115 BF525 Processor Support.
120 BF526 Processor Support.
125 BF527 Processor Support.
130 BF531 Processor Support.
135 BF532 Processor Support.
140 BF533 Processor Support.
145 BF534 Processor Support.
150 BF536 Processor Support.
155 BF537 Processor Support.
160 BF538 Processor Support.
165 BF539 Processor Support.
170 BF542 Processor Support.
175 BF544 Processor Support.
180 BF547 Processor Support.
185 BF548 Processor Support.
190 BF549 Processor Support.
195 BF561 Processor Support.
201 bool "Symmetric multi-processing support"
203 This enables support for systems with more than one CPU,
204 like the dual core BF561. If you have a system with only one
205 CPU, say N. If you have a system with more than one CPU, say Y.
207 If you don't know what to do here, say N.
219 config TICK_SOURCE_SYSTMR0
227 default 0 if (BF51x || BF52x || BF54x)
228 default 2 if (BF537 || BF536 || BF534)
229 default 3 if (BF561 ||BF533 || BF532 || BF531)
230 default 4 if (BF538 || BF539)
234 default 2 if (BF51x || BF52x || BF54x)
235 default 3 if (BF537 || BF536 || BF534)
236 default 5 if (BF561 || BF538 || BF539)
237 default 6 if (BF533 || BF532 || BF531)
241 default BF_REV_0_1 if (BF51x || BF52x || BF54x)
242 default BF_REV_0_2 if (BF534 || BF536 || BF537)
243 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
247 depends on (BF51x || BF52x || BF54x)
251 depends on (BF52x || BF54x)
255 depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
259 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
263 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
267 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
271 depends on (BF533 || BF532 || BF531)
283 depends on (BF512 || BF514 || BF516 || BF518)
288 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
293 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
298 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
301 config MEM_GENERIC_BOARD
303 depends on GENERIC_BOARD
306 config MEM_MT48LC64M4A2FB_7E
308 depends on (BFIN533_STAMP)
311 config MEM_MT48LC16M16A2TG_75
313 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
314 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
315 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
318 config MEM_MT48LC32M8A2_75
320 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
323 config MEM_MT48LC8M32B2B5_7
325 depends on (BFIN561_BLUETECHNIX_CM)
328 config MEM_MT48LC32M16A2TG_75
330 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
333 config MEM_MT48LC32M8A2_75
335 depends on (BFIN518F_EZBRD)
338 source "arch/blackfin/mach-bf518/Kconfig"
339 source "arch/blackfin/mach-bf527/Kconfig"
340 source "arch/blackfin/mach-bf533/Kconfig"
341 source "arch/blackfin/mach-bf561/Kconfig"
342 source "arch/blackfin/mach-bf537/Kconfig"
343 source "arch/blackfin/mach-bf538/Kconfig"
344 source "arch/blackfin/mach-bf548/Kconfig"
346 menu "Board customizations"
349 bool "Default bootloader kernel arguments"
352 string "Initial kernel command string"
353 depends on CMDLINE_BOOL
354 default "console=ttyBF0,57600"
356 If you don't have a boot loader capable of passing a command line string
357 to the kernel, you may specify one here. As a minimum, you should specify
358 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
361 hex "Kernel load address for booting"
363 range 0x1000 0x20000000
365 This option allows you to set the load address of the kernel.
366 This can be useful if you are on a board which has a small amount
367 of memory or you wish to reserve some memory at the beginning of
370 Note that you need to keep this value above 4k (0x1000) as this
371 memory region is used to capture NULL pointer references as well
372 as some core kernel functions.
375 hex "Kernel ROM Base"
378 range 0x20000000 0x20400000 if !(BF54x || BF561)
379 range 0x20000000 0x30000000 if (BF54x || BF561)
382 comment "Clock/PLL Setup"
385 int "Frequency of the crystal on the board in Hz"
386 default "11059200" if BFIN533_STAMP
387 default "27000000" if BFIN533_EZKIT
388 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
389 default "30000000" if BFIN561_EZKIT
390 default "24576000" if PNAV10
391 default "10000000" if BFIN532_IP0X
393 The frequency of CLKIN crystal oscillator on the board in Hz.
394 Warning: This value should match the crystal on the board. Otherwise,
395 peripherals won't work properly.
397 config BFIN_KERNEL_CLOCK
398 bool "Re-program Clocks while Kernel boots?"
401 This option decides if kernel clocks are re-programed from the
402 bootloader settings. If the clocks are not set, the SDRAM settings
403 are also not changed, and the Bootloader does 100% of the hardware
408 depends on BFIN_KERNEL_CLOCK
413 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
416 If this is set the clock will be divided by 2, before it goes to the PLL.
420 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
422 default "22" if BFIN533_EZKIT
423 default "45" if BFIN533_STAMP
424 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
425 default "22" if BFIN533_BLUETECHNIX_CM
426 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
427 default "20" if BFIN561_EZKIT
428 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
430 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
431 PLL Frequency = (Crystal Frequency) * (this setting)
434 prompt "Core Clock Divider"
435 depends on BFIN_KERNEL_CLOCK
438 This sets the frequency of the core. It can be 1, 2, 4 or 8
439 Core Frequency = (PLL frequency) / (this setting)
455 int "System Clock Divider"
456 depends on BFIN_KERNEL_CLOCK
460 This sets the frequency of the system clock (including SDRAM or DDR).
461 This can be between 1 and 15
462 System Clock = (PLL frequency) / (this setting)
465 prompt "DDR SDRAM Chip Type"
466 depends on BFIN_KERNEL_CLOCK
468 default MEM_MT46V32M16_5B
470 config MEM_MT46V32M16_6T
473 config MEM_MT46V32M16_5B
478 prompt "DDR/SDRAM Timing"
479 depends on BFIN_KERNEL_CLOCK
480 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
482 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
483 The calculated SDRAM timing parameters may not be 100%
484 accurate - This option is therefore marked experimental.
486 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
487 bool "Calculate Timings (EXPERIMENTAL)"
488 depends on EXPERIMENTAL
490 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
491 bool "Provide accurate Timings based on target SCLK"
493 Please consult the Blackfin Hardware Reference Manuals as well
494 as the memory device datasheet.
495 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
498 menu "Memory Init Control"
499 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
516 config MEM_EBIU_DDRQUE
533 # Max & Min Speeds for various Chips
537 default 400000000 if BF512
538 default 400000000 if BF514
539 default 400000000 if BF516
540 default 400000000 if BF518
541 default 600000000 if BF522
542 default 400000000 if BF523
543 default 400000000 if BF524
544 default 600000000 if BF525
545 default 400000000 if BF526
546 default 600000000 if BF527
547 default 400000000 if BF531
548 default 400000000 if BF532
549 default 750000000 if BF533
550 default 500000000 if BF534
551 default 400000000 if BF536
552 default 600000000 if BF537
553 default 533333333 if BF538
554 default 533333333 if BF539
555 default 600000000 if BF542
556 default 533333333 if BF544
557 default 600000000 if BF547
558 default 600000000 if BF548
559 default 533333333 if BF549
560 default 600000000 if BF561
574 comment "Kernel Timer/Scheduler"
576 source kernel/Kconfig.hz
583 config GENERIC_CLOCKEVENTS
584 bool "Generic clock events"
585 depends on GENERIC_TIME
588 config CYCLES_CLOCKSOURCE
589 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
590 depends on EXPERIMENTAL
591 depends on GENERIC_CLOCKEVENTS
592 depends on !BFIN_SCRATCH_REG_CYCLES
595 If you say Y here, you will enable support for using the 'cycles'
596 registers as a clock source. Doing so means you will be unable to
597 safely write to the 'cycles' register during runtime. You will
598 still be able to read it (such as for performance monitoring), but
599 writing the registers will most likely crash the kernel.
601 source kernel/time/Kconfig
606 prompt "Blackfin Exception Scratch Register"
607 default BFIN_SCRATCH_REG_RETN
609 Select the resource to reserve for the Exception handler:
610 - RETN: Non-Maskable Interrupt (NMI)
611 - RETE: Exception Return (JTAG/ICE)
612 - CYCLES: Performance counter
614 If you are unsure, please select "RETN".
616 config BFIN_SCRATCH_REG_RETN
619 Use the RETN register in the Blackfin exception handler
620 as a stack scratch register. This means you cannot
621 safely use NMI on the Blackfin while running Linux, but
622 you can debug the system with a JTAG ICE and use the
623 CYCLES performance registers.
625 If you are unsure, please select "RETN".
627 config BFIN_SCRATCH_REG_RETE
630 Use the RETE register in the Blackfin exception handler
631 as a stack scratch register. This means you cannot
632 safely use a JTAG ICE while debugging a Blackfin board,
633 but you can safely use the CYCLES performance registers
636 If you are unsure, please select "RETN".
638 config BFIN_SCRATCH_REG_CYCLES
641 Use the CYCLES register in the Blackfin exception handler
642 as a stack scratch register. This means you cannot
643 safely use the CYCLES performance registers on a Blackfin
644 board at anytime, but you can debug the system with a JTAG
647 If you are unsure, please select "RETN".
654 menu "Blackfin Kernel Optimizations"
657 comment "Memory Optimizations"
660 bool "Locate interrupt entry code in L1 Memory"
663 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
664 into L1 instruction memory. (less latency)
666 config EXCPT_IRQ_SYSC_L1
667 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
670 If enabled, the entire ASM lowlevel exception and interrupt entry code
671 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
675 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
678 If enabled, the frequently called do_irq dispatcher function is linked
679 into L1 instruction memory. (less latency)
681 config CORE_TIMER_IRQ_L1
682 bool "Locate frequently called timer_interrupt() function in L1 Memory"
685 If enabled, the frequently called timer_interrupt() function is linked
686 into L1 instruction memory. (less latency)
689 bool "Locate frequently idle function in L1 Memory"
692 If enabled, the frequently called idle function is linked
693 into L1 instruction memory. (less latency)
696 bool "Locate kernel schedule function in L1 Memory"
699 If enabled, the frequently called kernel schedule is linked
700 into L1 instruction memory. (less latency)
702 config ARITHMETIC_OPS_L1
703 bool "Locate kernel owned arithmetic functions in L1 Memory"
706 If enabled, arithmetic functions are linked
707 into L1 instruction memory. (less latency)
710 bool "Locate access_ok function in L1 Memory"
713 If enabled, the access_ok function is linked
714 into L1 instruction memory. (less latency)
717 bool "Locate memset function in L1 Memory"
720 If enabled, the memset function is linked
721 into L1 instruction memory. (less latency)
724 bool "Locate memcpy function in L1 Memory"
727 If enabled, the memcpy function is linked
728 into L1 instruction memory. (less latency)
730 config SYS_BFIN_SPINLOCK_L1
731 bool "Locate sys_bfin_spinlock function in L1 Memory"
734 If enabled, sys_bfin_spinlock function is linked
735 into L1 instruction memory. (less latency)
737 config IP_CHECKSUM_L1
738 bool "Locate IP Checksum function in L1 Memory"
741 If enabled, the IP Checksum function is linked
742 into L1 instruction memory. (less latency)
744 config CACHELINE_ALIGNED_L1
745 bool "Locate cacheline_aligned data to L1 Data Memory"
750 If enabled, cacheline_anligned data is linked
751 into L1 data memory. (less latency)
753 config SYSCALL_TAB_L1
754 bool "Locate Syscall Table L1 Data Memory"
758 If enabled, the Syscall LUT is linked
759 into L1 data memory. (less latency)
761 config CPLB_SWITCH_TAB_L1
762 bool "Locate CPLB Switch Tables L1 Data Memory"
766 If enabled, the CPLB Switch Tables are linked
767 into L1 data memory. (less latency)
770 bool "Support locating application stack in L1 Scratch Memory"
773 If enabled the application stack can be located in L1
774 scratch memory (less latency).
776 Currently only works with FLAT binaries.
778 config EXCEPTION_L1_SCRATCH
779 bool "Locate exception stack in L1 Scratch Memory"
781 depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
783 Whenever an exception occurs, use the L1 Scratch memory for
784 stack storage. You cannot place the stacks of FLAT binaries
785 in L1 when using this option.
787 If you don't use L1 Scratch, then you should say Y here.
789 comment "Speed Optimizations"
790 config BFIN_INS_LOWOVERHEAD
791 bool "ins[bwl] low overhead, higher interrupt latency"
794 Reads on the Blackfin are speculative. In Blackfin terms, this means
795 they can be interrupted at any time (even after they have been issued
796 on to the external bus), and re-issued after the interrupt occurs.
797 For memory - this is not a big deal, since memory does not change if
800 If a FIFO is sitting on the end of the read, it will see two reads,
801 when the core only sees one since the FIFO receives both the read
802 which is cancelled (and not delivered to the core) and the one which
803 is re-issued (which is delivered to the core).
805 To solve this, interrupts are turned off before reads occur to
806 I/O space. This option controls which the overhead/latency of
807 controlling interrupts during this time
808 "n" turns interrupts off every read
809 (higher overhead, but lower interrupt latency)
810 "y" turns interrupts off every loop
811 (low overhead, but longer interrupt latency)
813 default behavior is to leave this set to on (type "Y"). If you are experiencing
814 interrupt latency issues, it is safe and OK to turn this off.
819 prompt "Kernel executes from"
821 Choose the memory type that the kernel will be running in.
826 The kernel will be resident in RAM when running.
831 The kernel will be resident in FLASH/ROM when running.
838 tristate "Enable Blackfin General Purpose Timers API"
841 Enable support for the General Purpose Timers API. If you
844 To compile this driver as a module, choose M here: the module
845 will be called gptimers.ko.
848 prompt "Uncached DMA region"
849 default DMA_UNCACHED_1M
850 config DMA_UNCACHED_4M
851 bool "Enable 4M DMA region"
852 config DMA_UNCACHED_2M
853 bool "Enable 2M DMA region"
854 config DMA_UNCACHED_1M
855 bool "Enable 1M DMA region"
856 config DMA_UNCACHED_NONE
857 bool "Disable DMA region"
861 comment "Cache Support"
866 config BFIN_DCACHE_BANKA
867 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
868 depends on BFIN_DCACHE && !BF531
870 config BFIN_ICACHE_LOCK
871 bool "Enable Instruction Cache Locking"
875 depends on BFIN_DCACHE
876 default BFIN_WB if !SMP
877 default BFIN_WT if SMP
883 Cached data will be written back to SDRAM only when needed.
884 This can give a nice increase in performance, but beware of
885 broken drivers that do not properly invalidate/flush their
888 Write Through Policy:
889 Cached data will always be written back to SDRAM when the
890 cache is updated. This is a completely safe setting, but
891 performance is worse than Write Back.
893 If you are unsure of the options and you want to be safe,
894 then go with Write Through.
900 Cached data will be written back to SDRAM only when needed.
901 This can give a nice increase in performance, but beware of
902 broken drivers that do not properly invalidate/flush their
905 Write Through Policy:
906 Cached data will always be written back to SDRAM when the
907 cache is updated. This is a completely safe setting, but
908 performance is worse than Write Back.
910 If you are unsure of the options and you want to be safe,
911 then go with Write Through.
915 config BFIN_L2_CACHEABLE
917 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
920 Select to make L2 SRAM cacheable in L1 data and instruction cache.
923 bool "Enable the memory protection unit (EXPERIMENTAL)"
926 Use the processor's MPU to protect applications from accessing
927 memory they do not own. This comes at a performance penalty
928 and is recommended only for debugging.
930 comment "Asynchonous Memory Configuration"
932 menu "EBIU_AMGCTL Global Control"
938 bool "DMA has priority over core for ext. accesses"
943 bool "Bank 0 16 bit packing enable"
948 bool "Bank 1 16 bit packing enable"
953 bool "Bank 2 16 bit packing enable"
958 bool "Bank 3 16 bit packing enable"
962 prompt"Enable Asynchonous Memory Banks"
966 bool "Disable All Banks"
972 bool "Enable Bank 0 & 1"
974 config C_AMBEN_B0_B1_B2
975 bool "Enable Bank 0 & 1 & 2"
978 bool "Enable All Banks"
982 menu "EBIU_AMBCTL Control"
990 default 0x5558 if BF54x
1001 config EBIU_MBSCTLVAL
1002 hex "EBIU Bank Select Control Register"
1007 hex "Flash Memory Mode Control Register"
1012 hex "Flash Memory Bank Control Register"
1017 #############################################################################
1018 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1024 Support for PCI bus.
1026 source "drivers/pci/Kconfig"
1029 bool "Support for hot-pluggable device"
1031 Say Y here if you want to plug devices into your computer while
1032 the system is running, and be able to use them quickly. In many
1033 cases, the devices can likewise be unplugged at any time too.
1035 One well known example of this is PCMCIA- or PC-cards, credit-card
1036 size devices such as network cards, modems or hard drives which are
1037 plugged into slots found on all modern laptop computers. Another
1038 example, used on modern desktops as well as laptops, is USB.
1040 Enable HOTPLUG and build a modular kernel. Get agent software
1041 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1042 Then your kernel will automatically call out to a user mode "policy
1043 agent" (/sbin/hotplug) to load modules and set up software needed
1044 to use devices as you hotplug them.
1046 source "drivers/pcmcia/Kconfig"
1048 source "drivers/pci/hotplug/Kconfig"
1052 menu "Executable file formats"
1054 source "fs/Kconfig.binfmt"
1058 menu "Power management options"
1059 source "kernel/power/Kconfig"
1061 config ARCH_SUSPEND_POSSIBLE
1066 prompt "Standby Power Saving Mode"
1068 default PM_BFIN_SLEEP_DEEPER
1069 config PM_BFIN_SLEEP_DEEPER
1072 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1073 power dissipation by disabling the clock to the processor core (CCLK).
1074 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1075 to 0.85 V to provide the greatest power savings, while preserving the
1077 The PLL and system clock (SCLK) continue to operate at a very low
1078 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1079 the SDRAM is put into Self Refresh Mode. Typically an external event
1080 such as GPIO interrupt or RTC activity wakes up the processor.
1081 Various Peripherals such as UART, SPORT, PPI may not function as
1082 normal during Sleep Deeper, due to the reduced SCLK frequency.
1083 When in the sleep mode, system DMA access to L1 memory is not supported.
1085 If unsure, select "Sleep Deeper".
1087 config PM_BFIN_SLEEP
1090 Sleep Mode (High Power Savings) - The sleep mode reduces power
1091 dissipation by disabling the clock to the processor core (CCLK).
1092 The PLL and system clock (SCLK), however, continue to operate in
1093 this mode. Typically an external event or RTC activity will wake
1094 up the processor. When in the sleep mode, system DMA access to L1
1095 memory is not supported.
1097 If unsure, select "Sleep Deeper".
1100 config PM_WAKEUP_BY_GPIO
1101 bool "Allow Wakeup from Standby by GPIO"
1103 config PM_WAKEUP_GPIO_NUMBER
1106 depends on PM_WAKEUP_BY_GPIO
1110 prompt "GPIO Polarity"
1111 depends on PM_WAKEUP_BY_GPIO
1112 default PM_WAKEUP_GPIO_POLAR_H
1113 config PM_WAKEUP_GPIO_POLAR_H
1115 config PM_WAKEUP_GPIO_POLAR_L
1117 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1119 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1121 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1125 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1128 config PM_BFIN_WAKE_PH6
1129 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1130 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1133 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1135 config PM_BFIN_WAKE_GP
1136 bool "Allow Wake-Up from GPIOs"
1137 depends on PM && BF54x
1140 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1143 menu "CPU Frequency scaling"
1145 source "drivers/cpufreq/Kconfig"
1147 config BFIN_CPU_FREQ
1150 select CPU_FREQ_TABLE
1154 bool "CPU Voltage scaling"
1155 depends on EXPERIMENTAL
1159 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1160 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1161 manuals. There is a theoretical risk that during VDDINT transitions
1166 source "net/Kconfig"
1168 source "drivers/Kconfig"
1172 source "arch/blackfin/Kconfig.debug"
1174 source "security/Kconfig"
1176 source "crypto/Kconfig"
1178 source "lib/Kconfig"