2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
29 select ARCH_WANT_OPTIONAL_GPIOLIB
35 config GENERIC_FIND_NEXT_BIT
39 config GENERIC_HWEIGHT
43 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
55 config FORCE_MAX_ZONEORDER
59 config GENERIC_CALIBRATE_DELAY
69 source "kernel/Kconfig.preempt"
71 source "kernel/Kconfig.freezer"
73 menu "Blackfin Processor Options"
75 comment "Processor and Board Settings"
84 BF512 Processor Support.
89 BF514 Processor Support.
94 BF516 Processor Support.
99 BF518 Processor Support.
104 BF522 Processor Support.
109 BF523 Processor Support.
114 BF524 Processor Support.
119 BF525 Processor Support.
124 BF526 Processor Support.
129 BF527 Processor Support.
134 BF531 Processor Support.
139 BF532 Processor Support.
144 BF533 Processor Support.
149 BF534 Processor Support.
154 BF536 Processor Support.
159 BF537 Processor Support.
164 BF538 Processor Support.
169 BF539 Processor Support.
174 BF542 Processor Support.
179 BF544 Processor Support.
184 BF547 Processor Support.
189 BF548 Processor Support.
194 BF549 Processor Support.
199 BF561 Processor Support.
205 bool "Symmetric multi-processing support"
207 This enables support for systems with more than one CPU,
208 like the dual core BF561. If you have a system with only one
209 CPU, say N. If you have a system with more than one CPU, say Y.
211 If you don't know what to do here, say N.
223 config TICK_SOURCE_SYSTMR0
231 default 0 if (BF51x || BF52x || BF54x)
232 default 2 if (BF537 || BF536 || BF534)
233 default 3 if (BF561 ||BF533 || BF532 || BF531)
234 default 4 if (BF538 || BF539)
238 default 2 if (BF51x || BF52x || BF54x)
239 default 3 if (BF537 || BF536 || BF534)
240 default 5 if (BF561 || BF538 || BF539)
241 default 6 if (BF533 || BF532 || BF531)
245 default BF_REV_0_1 if (BF51x || BF52x || BF54x)
246 default BF_REV_0_2 if (BF534 || BF536 || BF537)
247 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
251 depends on (BF51x || BF52x || BF54x)
255 depends on (BF52x || BF54x)
259 depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
263 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
267 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
271 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
275 depends on (BF533 || BF532 || BF531)
287 depends on (BF512 || BF514 || BF516 || BF518)
292 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
297 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
302 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
305 config MEM_GENERIC_BOARD
307 depends on GENERIC_BOARD
310 config MEM_MT48LC64M4A2FB_7E
312 depends on (BFIN533_STAMP)
315 config MEM_MT48LC16M16A2TG_75
317 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
318 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
319 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
322 config MEM_MT48LC32M8A2_75
324 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
327 config MEM_MT48LC8M32B2B5_7
329 depends on (BFIN561_BLUETECHNIX_CM)
332 config MEM_MT48LC32M16A2TG_75
334 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
337 source "arch/blackfin/mach-bf518/Kconfig"
338 source "arch/blackfin/mach-bf527/Kconfig"
339 source "arch/blackfin/mach-bf533/Kconfig"
340 source "arch/blackfin/mach-bf561/Kconfig"
341 source "arch/blackfin/mach-bf537/Kconfig"
342 source "arch/blackfin/mach-bf538/Kconfig"
343 source "arch/blackfin/mach-bf548/Kconfig"
345 menu "Board customizations"
348 bool "Default bootloader kernel arguments"
351 string "Initial kernel command string"
352 depends on CMDLINE_BOOL
353 default "console=ttyBF0,57600"
355 If you don't have a boot loader capable of passing a command line string
356 to the kernel, you may specify one here. As a minimum, you should specify
357 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
360 hex "Kernel load address for booting"
362 range 0x1000 0x20000000
364 This option allows you to set the load address of the kernel.
365 This can be useful if you are on a board which has a small amount
366 of memory or you wish to reserve some memory at the beginning of
369 Note that you need to keep this value above 4k (0x1000) as this
370 memory region is used to capture NULL pointer references as well
371 as some core kernel functions.
374 hex "Kernel ROM Base"
377 range 0x20000000 0x20400000 if !(BF54x || BF561)
378 range 0x20000000 0x30000000 if (BF54x || BF561)
381 comment "Clock/PLL Setup"
384 int "Frequency of the crystal on the board in Hz"
385 default "11059200" if BFIN533_STAMP
386 default "27000000" if BFIN533_EZKIT
387 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
388 default "30000000" if BFIN561_EZKIT
389 default "24576000" if PNAV10
390 default "10000000" if BFIN532_IP0X
392 The frequency of CLKIN crystal oscillator on the board in Hz.
393 Warning: This value should match the crystal on the board. Otherwise,
394 peripherals won't work properly.
396 config BFIN_KERNEL_CLOCK
397 bool "Re-program Clocks while Kernel boots?"
400 This option decides if kernel clocks are re-programed from the
401 bootloader settings. If the clocks are not set, the SDRAM settings
402 are also not changed, and the Bootloader does 100% of the hardware
407 depends on BFIN_KERNEL_CLOCK
412 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
415 If this is set the clock will be divided by 2, before it goes to the PLL.
419 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
421 default "22" if BFIN533_EZKIT
422 default "45" if BFIN533_STAMP
423 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
424 default "22" if BFIN533_BLUETECHNIX_CM
425 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
426 default "20" if BFIN561_EZKIT
427 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
429 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
430 PLL Frequency = (Crystal Frequency) * (this setting)
433 prompt "Core Clock Divider"
434 depends on BFIN_KERNEL_CLOCK
437 This sets the frequency of the core. It can be 1, 2, 4 or 8
438 Core Frequency = (PLL frequency) / (this setting)
454 int "System Clock Divider"
455 depends on BFIN_KERNEL_CLOCK
459 This sets the frequency of the system clock (including SDRAM or DDR).
460 This can be between 1 and 15
461 System Clock = (PLL frequency) / (this setting)
464 prompt "DDR SDRAM Chip Type"
465 depends on BFIN_KERNEL_CLOCK
467 default MEM_MT46V32M16_5B
469 config MEM_MT46V32M16_6T
472 config MEM_MT46V32M16_5B
477 prompt "DDR/SDRAM Timing"
478 depends on BFIN_KERNEL_CLOCK
479 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
481 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
482 The calculated SDRAM timing parameters may not be 100%
483 accurate - This option is therefore marked experimental.
485 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
486 bool "Calculate Timings (EXPERIMENTAL)"
487 depends on EXPERIMENTAL
489 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
490 bool "Provide accurate Timings based on target SCLK"
492 Please consult the Blackfin Hardware Reference Manuals as well
493 as the memory device datasheet.
494 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
497 menu "Memory Init Control"
498 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
515 config MEM_EBIU_DDRQUE
532 int "Max SDRAM Memory Size in MBytes"
536 This is the max memory size that the kernel will create CPLB
537 tables for. Your system will not be able to handle any more.
540 # Max & Min Speeds for various Chips
544 default 400000000 if BF512
545 default 400000000 if BF514
546 default 400000000 if BF516
547 default 400000000 if BF518
548 default 600000000 if BF522
549 default 400000000 if BF523
550 default 400000000 if BF524
551 default 600000000 if BF525
552 default 400000000 if BF526
553 default 600000000 if BF527
554 default 400000000 if BF531
555 default 400000000 if BF532
556 default 750000000 if BF533
557 default 500000000 if BF534
558 default 400000000 if BF536
559 default 600000000 if BF537
560 default 533333333 if BF538
561 default 533333333 if BF539
562 default 600000000 if BF542
563 default 533333333 if BF544
564 default 600000000 if BF547
565 default 600000000 if BF548
566 default 533333333 if BF549
567 default 600000000 if BF561
581 comment "Kernel Timer/Scheduler"
583 source kernel/Kconfig.hz
590 config GENERIC_CLOCKEVENTS
591 bool "Generic clock events"
592 depends on GENERIC_TIME
595 config CYCLES_CLOCKSOURCE
596 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
597 depends on EXPERIMENTAL
598 depends on GENERIC_CLOCKEVENTS
599 depends on !BFIN_SCRATCH_REG_CYCLES
602 If you say Y here, you will enable support for using the 'cycles'
603 registers as a clock source. Doing so means you will be unable to
604 safely write to the 'cycles' register during runtime. You will
605 still be able to read it (such as for performance monitoring), but
606 writing the registers will most likely crash the kernel.
608 source kernel/time/Kconfig
613 prompt "Blackfin Exception Scratch Register"
614 default BFIN_SCRATCH_REG_RETN
616 Select the resource to reserve for the Exception handler:
617 - RETN: Non-Maskable Interrupt (NMI)
618 - RETE: Exception Return (JTAG/ICE)
619 - CYCLES: Performance counter
621 If you are unsure, please select "RETN".
623 config BFIN_SCRATCH_REG_RETN
626 Use the RETN register in the Blackfin exception handler
627 as a stack scratch register. This means you cannot
628 safely use NMI on the Blackfin while running Linux, but
629 you can debug the system with a JTAG ICE and use the
630 CYCLES performance registers.
632 If you are unsure, please select "RETN".
634 config BFIN_SCRATCH_REG_RETE
637 Use the RETE register in the Blackfin exception handler
638 as a stack scratch register. This means you cannot
639 safely use a JTAG ICE while debugging a Blackfin board,
640 but you can safely use the CYCLES performance registers
643 If you are unsure, please select "RETN".
645 config BFIN_SCRATCH_REG_CYCLES
648 Use the CYCLES register in the Blackfin exception handler
649 as a stack scratch register. This means you cannot
650 safely use the CYCLES performance registers on a Blackfin
651 board at anytime, but you can debug the system with a JTAG
654 If you are unsure, please select "RETN".
661 menu "Blackfin Kernel Optimizations"
664 comment "Memory Optimizations"
667 bool "Locate interrupt entry code in L1 Memory"
670 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
671 into L1 instruction memory. (less latency)
673 config EXCPT_IRQ_SYSC_L1
674 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
677 If enabled, the entire ASM lowlevel exception and interrupt entry code
678 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
682 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
685 If enabled, the frequently called do_irq dispatcher function is linked
686 into L1 instruction memory. (less latency)
688 config CORE_TIMER_IRQ_L1
689 bool "Locate frequently called timer_interrupt() function in L1 Memory"
692 If enabled, the frequently called timer_interrupt() function is linked
693 into L1 instruction memory. (less latency)
696 bool "Locate frequently idle function in L1 Memory"
699 If enabled, the frequently called idle function is linked
700 into L1 instruction memory. (less latency)
703 bool "Locate kernel schedule function in L1 Memory"
706 If enabled, the frequently called kernel schedule is linked
707 into L1 instruction memory. (less latency)
709 config ARITHMETIC_OPS_L1
710 bool "Locate kernel owned arithmetic functions in L1 Memory"
713 If enabled, arithmetic functions are linked
714 into L1 instruction memory. (less latency)
717 bool "Locate access_ok function in L1 Memory"
720 If enabled, the access_ok function is linked
721 into L1 instruction memory. (less latency)
724 bool "Locate memset function in L1 Memory"
727 If enabled, the memset function is linked
728 into L1 instruction memory. (less latency)
731 bool "Locate memcpy function in L1 Memory"
734 If enabled, the memcpy function is linked
735 into L1 instruction memory. (less latency)
737 config SYS_BFIN_SPINLOCK_L1
738 bool "Locate sys_bfin_spinlock function in L1 Memory"
741 If enabled, sys_bfin_spinlock function is linked
742 into L1 instruction memory. (less latency)
744 config IP_CHECKSUM_L1
745 bool "Locate IP Checksum function in L1 Memory"
748 If enabled, the IP Checksum function is linked
749 into L1 instruction memory. (less latency)
751 config CACHELINE_ALIGNED_L1
752 bool "Locate cacheline_aligned data to L1 Data Memory"
757 If enabled, cacheline_anligned data is linked
758 into L1 data memory. (less latency)
760 config SYSCALL_TAB_L1
761 bool "Locate Syscall Table L1 Data Memory"
765 If enabled, the Syscall LUT is linked
766 into L1 data memory. (less latency)
768 config CPLB_SWITCH_TAB_L1
769 bool "Locate CPLB Switch Tables L1 Data Memory"
773 If enabled, the CPLB Switch Tables are linked
774 into L1 data memory. (less latency)
777 bool "Support locating application stack in L1 Scratch Memory"
780 If enabled the application stack can be located in L1
781 scratch memory (less latency).
783 Currently only works with FLAT binaries.
785 config EXCEPTION_L1_SCRATCH
786 bool "Locate exception stack in L1 Scratch Memory"
788 depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
790 Whenever an exception occurs, use the L1 Scratch memory for
791 stack storage. You cannot place the stacks of FLAT binaries
792 in L1 when using this option.
794 If you don't use L1 Scratch, then you should say Y here.
796 comment "Speed Optimizations"
797 config BFIN_INS_LOWOVERHEAD
798 bool "ins[bwl] low overhead, higher interrupt latency"
801 Reads on the Blackfin are speculative. In Blackfin terms, this means
802 they can be interrupted at any time (even after they have been issued
803 on to the external bus), and re-issued after the interrupt occurs.
804 For memory - this is not a big deal, since memory does not change if
807 If a FIFO is sitting on the end of the read, it will see two reads,
808 when the core only sees one since the FIFO receives both the read
809 which is cancelled (and not delivered to the core) and the one which
810 is re-issued (which is delivered to the core).
812 To solve this, interrupts are turned off before reads occur to
813 I/O space. This option controls which the overhead/latency of
814 controlling interrupts during this time
815 "n" turns interrupts off every read
816 (higher overhead, but lower interrupt latency)
817 "y" turns interrupts off every loop
818 (low overhead, but longer interrupt latency)
820 default behavior is to leave this set to on (type "Y"). If you are experiencing
821 interrupt latency issues, it is safe and OK to turn this off.
826 prompt "Kernel executes from"
828 Choose the memory type that the kernel will be running in.
833 The kernel will be resident in RAM when running.
838 The kernel will be resident in FLASH/ROM when running.
845 tristate "Enable Blackfin General Purpose Timers API"
848 Enable support for the General Purpose Timers API. If you
851 To compile this driver as a module, choose M here: the module
852 will be called gptimers.ko.
855 prompt "Uncached DMA region"
856 default DMA_UNCACHED_1M
857 config DMA_UNCACHED_4M
858 bool "Enable 4M DMA region"
859 config DMA_UNCACHED_2M
860 bool "Enable 2M DMA region"
861 config DMA_UNCACHED_1M
862 bool "Enable 1M DMA region"
863 config DMA_UNCACHED_NONE
864 bool "Disable DMA region"
868 comment "Cache Support"
873 config BFIN_DCACHE_BANKA
874 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
875 depends on BFIN_DCACHE && !BF531
877 config BFIN_ICACHE_LOCK
878 bool "Enable Instruction Cache Locking"
882 depends on BFIN_DCACHE
883 default BFIN_WB if !SMP
884 default BFIN_WT if SMP
890 Cached data will be written back to SDRAM only when needed.
891 This can give a nice increase in performance, but beware of
892 broken drivers that do not properly invalidate/flush their
895 Write Through Policy:
896 Cached data will always be written back to SDRAM when the
897 cache is updated. This is a completely safe setting, but
898 performance is worse than Write Back.
900 If you are unsure of the options and you want to be safe,
901 then go with Write Through.
907 Cached data will be written back to SDRAM only when needed.
908 This can give a nice increase in performance, but beware of
909 broken drivers that do not properly invalidate/flush their
912 Write Through Policy:
913 Cached data will always be written back to SDRAM when the
914 cache is updated. This is a completely safe setting, but
915 performance is worse than Write Back.
917 If you are unsure of the options and you want to be safe,
918 then go with Write Through.
922 config BFIN_L2_CACHEABLE
924 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
927 Select to make L2 SRAM cacheable in L1 data and instruction cache.
930 bool "Enable the memory protection unit (EXPERIMENTAL)"
933 Use the processor's MPU to protect applications from accessing
934 memory they do not own. This comes at a performance penalty
935 and is recommended only for debugging.
937 comment "Asynchonous Memory Configuration"
939 menu "EBIU_AMGCTL Global Control"
945 bool "DMA has priority over core for ext. accesses"
950 bool "Bank 0 16 bit packing enable"
955 bool "Bank 1 16 bit packing enable"
960 bool "Bank 2 16 bit packing enable"
965 bool "Bank 3 16 bit packing enable"
969 prompt"Enable Asynchonous Memory Banks"
973 bool "Disable All Banks"
979 bool "Enable Bank 0 & 1"
981 config C_AMBEN_B0_B1_B2
982 bool "Enable Bank 0 & 1 & 2"
985 bool "Enable All Banks"
989 menu "EBIU_AMBCTL Control"
997 default 0x5558 if BF54x
1008 config EBIU_MBSCTLVAL
1009 hex "EBIU Bank Select Control Register"
1014 hex "Flash Memory Mode Control Register"
1019 hex "Flash Memory Bank Control Register"
1024 #############################################################################
1025 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1031 Support for PCI bus.
1033 source "drivers/pci/Kconfig"
1036 bool "Support for hot-pluggable device"
1038 Say Y here if you want to plug devices into your computer while
1039 the system is running, and be able to use them quickly. In many
1040 cases, the devices can likewise be unplugged at any time too.
1042 One well known example of this is PCMCIA- or PC-cards, credit-card
1043 size devices such as network cards, modems or hard drives which are
1044 plugged into slots found on all modern laptop computers. Another
1045 example, used on modern desktops as well as laptops, is USB.
1047 Enable HOTPLUG and build a modular kernel. Get agent software
1048 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1049 Then your kernel will automatically call out to a user mode "policy
1050 agent" (/sbin/hotplug) to load modules and set up software needed
1051 to use devices as you hotplug them.
1053 source "drivers/pcmcia/Kconfig"
1055 source "drivers/pci/hotplug/Kconfig"
1059 menu "Executable file formats"
1061 source "fs/Kconfig.binfmt"
1065 menu "Power management options"
1066 source "kernel/power/Kconfig"
1068 config ARCH_SUSPEND_POSSIBLE
1073 prompt "Standby Power Saving Mode"
1075 default PM_BFIN_SLEEP_DEEPER
1076 config PM_BFIN_SLEEP_DEEPER
1079 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1080 power dissipation by disabling the clock to the processor core (CCLK).
1081 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1082 to 0.85 V to provide the greatest power savings, while preserving the
1084 The PLL and system clock (SCLK) continue to operate at a very low
1085 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1086 the SDRAM is put into Self Refresh Mode. Typically an external event
1087 such as GPIO interrupt or RTC activity wakes up the processor.
1088 Various Peripherals such as UART, SPORT, PPI may not function as
1089 normal during Sleep Deeper, due to the reduced SCLK frequency.
1090 When in the sleep mode, system DMA access to L1 memory is not supported.
1092 If unsure, select "Sleep Deeper".
1094 config PM_BFIN_SLEEP
1097 Sleep Mode (High Power Savings) - The sleep mode reduces power
1098 dissipation by disabling the clock to the processor core (CCLK).
1099 The PLL and system clock (SCLK), however, continue to operate in
1100 this mode. Typically an external event or RTC activity will wake
1101 up the processor. When in the sleep mode, system DMA access to L1
1102 memory is not supported.
1104 If unsure, select "Sleep Deeper".
1107 config PM_WAKEUP_BY_GPIO
1108 bool "Allow Wakeup from Standby by GPIO"
1110 config PM_WAKEUP_GPIO_NUMBER
1113 depends on PM_WAKEUP_BY_GPIO
1117 prompt "GPIO Polarity"
1118 depends on PM_WAKEUP_BY_GPIO
1119 default PM_WAKEUP_GPIO_POLAR_H
1120 config PM_WAKEUP_GPIO_POLAR_H
1122 config PM_WAKEUP_GPIO_POLAR_L
1124 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1126 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1128 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1132 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1135 config PM_BFIN_WAKE_PH6
1136 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1137 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1140 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1142 config PM_BFIN_WAKE_GP
1143 bool "Allow Wake-Up from GPIOs"
1144 depends on PM && BF54x
1147 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1150 menu "CPU Frequency scaling"
1152 source "drivers/cpufreq/Kconfig"
1154 config BFIN_CPU_FREQ
1157 select CPU_FREQ_TABLE
1161 bool "CPU Voltage scaling"
1162 depends on EXPERIMENTAL
1166 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1167 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1168 manuals. There is a theoretical risk that during VDDINT transitions
1173 source "net/Kconfig"
1175 source "drivers/Kconfig"
1179 source "arch/blackfin/Kconfig.debug"
1181 source "security/Kconfig"
1183 source "crypto/Kconfig"
1185 source "lib/Kconfig"