2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
29 select ARCH_WANT_OPTIONAL_GPIOLIB
35 config GENERIC_FIND_NEXT_BIT
39 config GENERIC_HWEIGHT
43 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
55 config FORCE_MAX_ZONEORDER
59 config GENERIC_CALIBRATE_DELAY
65 source "kernel/Kconfig.preempt"
67 source "kernel/Kconfig.freezer"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF512 Processor Support.
85 BF514 Processor Support.
90 BF516 Processor Support.
95 BF518 Processor Support.
100 BF522 Processor Support.
105 BF523 Processor Support.
110 BF524 Processor Support.
115 BF525 Processor Support.
120 BF526 Processor Support.
125 BF527 Processor Support.
130 BF531 Processor Support.
135 BF532 Processor Support.
140 BF533 Processor Support.
145 BF534 Processor Support.
150 BF536 Processor Support.
155 BF537 Processor Support.
160 BF538 Processor Support.
165 BF539 Processor Support.
170 BF542 Processor Support.
175 BF542 Processor Support.
180 BF544 Processor Support.
185 BF544 Processor Support.
190 BF547 Processor Support.
195 BF547 Processor Support.
200 BF548 Processor Support.
205 BF548 Processor Support.
210 BF549 Processor Support.
215 BF549 Processor Support.
220 BF561 Processor Support.
226 bool "Symmetric multi-processing support"
228 This enables support for systems with more than one CPU,
229 like the dual core BF561. If you have a system with only one
230 CPU, say N. If you have a system with more than one CPU, say Y.
232 If you don't know what to do here, say N.
246 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
247 default 2 if (BF537 || BF536 || BF534)
248 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
249 default 4 if (BF538 || BF539)
253 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
254 default 3 if (BF537 || BF536 || BF534 || BF54xM)
255 default 5 if (BF561 || BF538 || BF539)
256 default 6 if (BF533 || BF532 || BF531)
260 default BF_REV_0_0 if (BF51x || BF52x)
261 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
262 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
266 depends on (BF51x || BF52x || (BF54x && !BF54xM))
270 depends on (BF52x || (BF54x && !BF54xM))
274 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
278 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
282 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
286 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
290 depends on (BF533 || BF532 || BF531)
302 depends on (BF512 || BF514 || BF516 || BF518)
307 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
312 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
317 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
322 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
325 config MEM_GENERIC_BOARD
327 depends on GENERIC_BOARD
330 config MEM_MT48LC64M4A2FB_7E
332 depends on (BFIN533_STAMP)
335 config MEM_MT48LC16M16A2TG_75
337 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
338 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
339 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
342 config MEM_MT48LC32M8A2_75
344 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
347 config MEM_MT48LC8M32B2B5_7
349 depends on (BFIN561_BLUETECHNIX_CM)
352 config MEM_MT48LC32M16A2TG_75
354 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
357 config MEM_MT48LC32M8A2_75
359 depends on (BFIN518F_EZBRD)
362 source "arch/blackfin/mach-bf518/Kconfig"
363 source "arch/blackfin/mach-bf527/Kconfig"
364 source "arch/blackfin/mach-bf533/Kconfig"
365 source "arch/blackfin/mach-bf561/Kconfig"
366 source "arch/blackfin/mach-bf537/Kconfig"
367 source "arch/blackfin/mach-bf538/Kconfig"
368 source "arch/blackfin/mach-bf548/Kconfig"
370 menu "Board customizations"
373 bool "Default bootloader kernel arguments"
376 string "Initial kernel command string"
377 depends on CMDLINE_BOOL
378 default "console=ttyBF0,57600"
380 If you don't have a boot loader capable of passing a command line string
381 to the kernel, you may specify one here. As a minimum, you should specify
382 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
385 hex "Kernel load address for booting"
387 range 0x1000 0x20000000
389 This option allows you to set the load address of the kernel.
390 This can be useful if you are on a board which has a small amount
391 of memory or you wish to reserve some memory at the beginning of
394 Note that you need to keep this value above 4k (0x1000) as this
395 memory region is used to capture NULL pointer references as well
396 as some core kernel functions.
399 hex "Kernel ROM Base"
402 range 0x20000000 0x20400000 if !(BF54x || BF561)
403 range 0x20000000 0x30000000 if (BF54x || BF561)
406 comment "Clock/PLL Setup"
409 int "Frequency of the crystal on the board in Hz"
410 default "11059200" if BFIN533_STAMP
411 default "27000000" if BFIN533_EZKIT
412 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
413 default "30000000" if BFIN561_EZKIT
414 default "24576000" if PNAV10
415 default "10000000" if BFIN532_IP0X
417 The frequency of CLKIN crystal oscillator on the board in Hz.
418 Warning: This value should match the crystal on the board. Otherwise,
419 peripherals won't work properly.
421 config BFIN_KERNEL_CLOCK
422 bool "Re-program Clocks while Kernel boots?"
425 This option decides if kernel clocks are re-programed from the
426 bootloader settings. If the clocks are not set, the SDRAM settings
427 are also not changed, and the Bootloader does 100% of the hardware
432 depends on BFIN_KERNEL_CLOCK
437 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
440 If this is set the clock will be divided by 2, before it goes to the PLL.
444 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
446 default "22" if BFIN533_EZKIT
447 default "45" if BFIN533_STAMP
448 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
449 default "22" if BFIN533_BLUETECHNIX_CM
450 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
451 default "20" if BFIN561_EZKIT
452 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
454 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
455 PLL Frequency = (Crystal Frequency) * (this setting)
458 prompt "Core Clock Divider"
459 depends on BFIN_KERNEL_CLOCK
462 This sets the frequency of the core. It can be 1, 2, 4 or 8
463 Core Frequency = (PLL frequency) / (this setting)
479 int "System Clock Divider"
480 depends on BFIN_KERNEL_CLOCK
484 This sets the frequency of the system clock (including SDRAM or DDR).
485 This can be between 1 and 15
486 System Clock = (PLL frequency) / (this setting)
489 prompt "DDR SDRAM Chip Type"
490 depends on BFIN_KERNEL_CLOCK
492 default MEM_MT46V32M16_5B
494 config MEM_MT46V32M16_6T
497 config MEM_MT46V32M16_5B
502 prompt "DDR/SDRAM Timing"
503 depends on BFIN_KERNEL_CLOCK
504 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
506 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
507 The calculated SDRAM timing parameters may not be 100%
508 accurate - This option is therefore marked experimental.
510 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
511 bool "Calculate Timings (EXPERIMENTAL)"
512 depends on EXPERIMENTAL
514 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
515 bool "Provide accurate Timings based on target SCLK"
517 Please consult the Blackfin Hardware Reference Manuals as well
518 as the memory device datasheet.
519 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
522 menu "Memory Init Control"
523 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
540 config MEM_EBIU_DDRQUE
557 # Max & Min Speeds for various Chips
561 default 400000000 if BF512
562 default 400000000 if BF514
563 default 400000000 if BF516
564 default 400000000 if BF518
565 default 600000000 if BF522
566 default 400000000 if BF523
567 default 400000000 if BF524
568 default 600000000 if BF525
569 default 400000000 if BF526
570 default 600000000 if BF527
571 default 400000000 if BF531
572 default 400000000 if BF532
573 default 750000000 if BF533
574 default 500000000 if BF534
575 default 400000000 if BF536
576 default 600000000 if BF537
577 default 533333333 if BF538
578 default 533333333 if BF539
579 default 600000000 if BF542
580 default 533333333 if BF544
581 default 600000000 if BF547
582 default 600000000 if BF548
583 default 533333333 if BF549
584 default 600000000 if BF561
598 comment "Kernel Timer/Scheduler"
600 source kernel/Kconfig.hz
606 config GENERIC_CLOCKEVENTS
607 bool "Generic clock events"
608 depends on GENERIC_TIME
612 prompt "Kernel Tick Source"
613 depends on GENERIC_CLOCKEVENTS
614 default TICKSOURCE_CORETMR
616 config TICKSOURCE_GPTMR0
617 bool "Gptimer0 (SCLK domain)"
621 config TICKSOURCE_CORETMR
622 bool "Core timer (CCLK domain)"
626 config CYCLES_CLOCKSOURCE
627 bool "Use 'CYCLES' as a clocksource"
628 depends on GENERIC_CLOCKEVENTS
629 depends on !BFIN_SCRATCH_REG_CYCLES
632 If you say Y here, you will enable support for using the 'cycles'
633 registers as a clock source. Doing so means you will be unable to
634 safely write to the 'cycles' register during runtime. You will
635 still be able to read it (such as for performance monitoring), but
636 writing the registers will most likely crash the kernel.
638 config GPTMR0_CLOCKSOURCE
639 bool "Use GPTimer0 as a clocksource (higher rating)"
640 depends on GENERIC_CLOCKEVENTS
641 depends on !TICKSOURCE_GPTMR0
643 source kernel/time/Kconfig
648 prompt "Blackfin Exception Scratch Register"
649 default BFIN_SCRATCH_REG_RETN
651 Select the resource to reserve for the Exception handler:
652 - RETN: Non-Maskable Interrupt (NMI)
653 - RETE: Exception Return (JTAG/ICE)
654 - CYCLES: Performance counter
656 If you are unsure, please select "RETN".
658 config BFIN_SCRATCH_REG_RETN
661 Use the RETN register in the Blackfin exception handler
662 as a stack scratch register. This means you cannot
663 safely use NMI on the Blackfin while running Linux, but
664 you can debug the system with a JTAG ICE and use the
665 CYCLES performance registers.
667 If you are unsure, please select "RETN".
669 config BFIN_SCRATCH_REG_RETE
672 Use the RETE register in the Blackfin exception handler
673 as a stack scratch register. This means you cannot
674 safely use a JTAG ICE while debugging a Blackfin board,
675 but you can safely use the CYCLES performance registers
678 If you are unsure, please select "RETN".
680 config BFIN_SCRATCH_REG_CYCLES
683 Use the CYCLES register in the Blackfin exception handler
684 as a stack scratch register. This means you cannot
685 safely use the CYCLES performance registers on a Blackfin
686 board at anytime, but you can debug the system with a JTAG
689 If you are unsure, please select "RETN".
696 menu "Blackfin Kernel Optimizations"
699 comment "Memory Optimizations"
702 bool "Locate interrupt entry code in L1 Memory"
705 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
706 into L1 instruction memory. (less latency)
708 config EXCPT_IRQ_SYSC_L1
709 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
712 If enabled, the entire ASM lowlevel exception and interrupt entry code
713 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
717 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
720 If enabled, the frequently called do_irq dispatcher function is linked
721 into L1 instruction memory. (less latency)
723 config CORE_TIMER_IRQ_L1
724 bool "Locate frequently called timer_interrupt() function in L1 Memory"
727 If enabled, the frequently called timer_interrupt() function is linked
728 into L1 instruction memory. (less latency)
731 bool "Locate frequently idle function in L1 Memory"
734 If enabled, the frequently called idle function is linked
735 into L1 instruction memory. (less latency)
738 bool "Locate kernel schedule function in L1 Memory"
741 If enabled, the frequently called kernel schedule is linked
742 into L1 instruction memory. (less latency)
744 config ARITHMETIC_OPS_L1
745 bool "Locate kernel owned arithmetic functions in L1 Memory"
748 If enabled, arithmetic functions are linked
749 into L1 instruction memory. (less latency)
752 bool "Locate access_ok function in L1 Memory"
755 If enabled, the access_ok function is linked
756 into L1 instruction memory. (less latency)
759 bool "Locate memset function in L1 Memory"
762 If enabled, the memset function is linked
763 into L1 instruction memory. (less latency)
766 bool "Locate memcpy function in L1 Memory"
769 If enabled, the memcpy function is linked
770 into L1 instruction memory. (less latency)
772 config SYS_BFIN_SPINLOCK_L1
773 bool "Locate sys_bfin_spinlock function in L1 Memory"
776 If enabled, sys_bfin_spinlock function is linked
777 into L1 instruction memory. (less latency)
779 config IP_CHECKSUM_L1
780 bool "Locate IP Checksum function in L1 Memory"
783 If enabled, the IP Checksum function is linked
784 into L1 instruction memory. (less latency)
786 config CACHELINE_ALIGNED_L1
787 bool "Locate cacheline_aligned data to L1 Data Memory"
792 If enabled, cacheline_aligned data is linked
793 into L1 data memory. (less latency)
795 config SYSCALL_TAB_L1
796 bool "Locate Syscall Table L1 Data Memory"
800 If enabled, the Syscall LUT is linked
801 into L1 data memory. (less latency)
803 config CPLB_SWITCH_TAB_L1
804 bool "Locate CPLB Switch Tables L1 Data Memory"
808 If enabled, the CPLB Switch Tables are linked
809 into L1 data memory. (less latency)
812 bool "Support locating application stack in L1 Scratch Memory"
815 If enabled the application stack can be located in L1
816 scratch memory (less latency).
818 Currently only works with FLAT binaries.
820 config EXCEPTION_L1_SCRATCH
821 bool "Locate exception stack in L1 Scratch Memory"
823 depends on !APP_STACK_L1
825 Whenever an exception occurs, use the L1 Scratch memory for
826 stack storage. You cannot place the stacks of FLAT binaries
827 in L1 when using this option.
829 If you don't use L1 Scratch, then you should say Y here.
831 comment "Speed Optimizations"
832 config BFIN_INS_LOWOVERHEAD
833 bool "ins[bwl] low overhead, higher interrupt latency"
836 Reads on the Blackfin are speculative. In Blackfin terms, this means
837 they can be interrupted at any time (even after they have been issued
838 on to the external bus), and re-issued after the interrupt occurs.
839 For memory - this is not a big deal, since memory does not change if
842 If a FIFO is sitting on the end of the read, it will see two reads,
843 when the core only sees one since the FIFO receives both the read
844 which is cancelled (and not delivered to the core) and the one which
845 is re-issued (which is delivered to the core).
847 To solve this, interrupts are turned off before reads occur to
848 I/O space. This option controls which the overhead/latency of
849 controlling interrupts during this time
850 "n" turns interrupts off every read
851 (higher overhead, but lower interrupt latency)
852 "y" turns interrupts off every loop
853 (low overhead, but longer interrupt latency)
855 default behavior is to leave this set to on (type "Y"). If you are experiencing
856 interrupt latency issues, it is safe and OK to turn this off.
861 prompt "Kernel executes from"
863 Choose the memory type that the kernel will be running in.
868 The kernel will be resident in RAM when running.
873 The kernel will be resident in FLASH/ROM when running.
880 tristate "Enable Blackfin General Purpose Timers API"
883 Enable support for the General Purpose Timers API. If you
886 To compile this driver as a module, choose M here: the module
887 will be called gptimers.ko.
890 prompt "Uncached DMA region"
891 default DMA_UNCACHED_1M
892 config DMA_UNCACHED_4M
893 bool "Enable 4M DMA region"
894 config DMA_UNCACHED_2M
895 bool "Enable 2M DMA region"
896 config DMA_UNCACHED_1M
897 bool "Enable 1M DMA region"
898 config DMA_UNCACHED_NONE
899 bool "Disable DMA region"
903 comment "Cache Support"
908 config BFIN_DCACHE_BANKA
909 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
910 depends on BFIN_DCACHE && !BF531
912 config BFIN_ICACHE_LOCK
913 bool "Enable Instruction Cache Locking"
917 depends on BFIN_DCACHE
918 default BFIN_WB if !SMP
919 default BFIN_WT if SMP
925 Cached data will be written back to SDRAM only when needed.
926 This can give a nice increase in performance, but beware of
927 broken drivers that do not properly invalidate/flush their
930 Write Through Policy:
931 Cached data will always be written back to SDRAM when the
932 cache is updated. This is a completely safe setting, but
933 performance is worse than Write Back.
935 If you are unsure of the options and you want to be safe,
936 then go with Write Through.
942 Cached data will be written back to SDRAM only when needed.
943 This can give a nice increase in performance, but beware of
944 broken drivers that do not properly invalidate/flush their
947 Write Through Policy:
948 Cached data will always be written back to SDRAM when the
949 cache is updated. This is a completely safe setting, but
950 performance is worse than Write Back.
952 If you are unsure of the options and you want to be safe,
953 then go with Write Through.
957 config BFIN_L2_CACHEABLE
959 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
962 Select to make L2 SRAM cacheable in L1 data and instruction cache.
965 bool "Enable the memory protection unit (EXPERIMENTAL)"
968 Use the processor's MPU to protect applications from accessing
969 memory they do not own. This comes at a performance penalty
970 and is recommended only for debugging.
972 comment "Asynchronous Memory Configuration"
974 menu "EBIU_AMGCTL Global Control"
980 bool "DMA has priority over core for ext. accesses"
985 bool "Bank 0 16 bit packing enable"
990 bool "Bank 1 16 bit packing enable"
995 bool "Bank 2 16 bit packing enable"
1000 bool "Bank 3 16 bit packing enable"
1004 prompt "Enable Asynchronous Memory Banks"
1008 bool "Disable All Banks"
1011 bool "Enable Bank 0"
1013 config C_AMBEN_B0_B1
1014 bool "Enable Bank 0 & 1"
1016 config C_AMBEN_B0_B1_B2
1017 bool "Enable Bank 0 & 1 & 2"
1020 bool "Enable All Banks"
1024 menu "EBIU_AMBCTL Control"
1026 hex "Bank 0 (AMBCTL0.L)"
1029 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1030 used to control the Asynchronous Memory Bank 0 settings.
1033 hex "Bank 1 (AMBCTL0.H)"
1035 default 0x5558 if BF54x
1037 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1038 used to control the Asynchronous Memory Bank 1 settings.
1041 hex "Bank 2 (AMBCTL1.L)"
1044 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1045 used to control the Asynchronous Memory Bank 2 settings.
1048 hex "Bank 3 (AMBCTL1.H)"
1051 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1052 used to control the Asynchronous Memory Bank 3 settings.
1056 config EBIU_MBSCTLVAL
1057 hex "EBIU Bank Select Control Register"
1062 hex "Flash Memory Mode Control Register"
1067 hex "Flash Memory Bank Control Register"
1072 #############################################################################
1073 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1079 Support for PCI bus.
1081 source "drivers/pci/Kconfig"
1084 bool "Support for hot-pluggable device"
1086 Say Y here if you want to plug devices into your computer while
1087 the system is running, and be able to use them quickly. In many
1088 cases, the devices can likewise be unplugged at any time too.
1090 One well known example of this is PCMCIA- or PC-cards, credit-card
1091 size devices such as network cards, modems or hard drives which are
1092 plugged into slots found on all modern laptop computers. Another
1093 example, used on modern desktops as well as laptops, is USB.
1095 Enable HOTPLUG and build a modular kernel. Get agent software
1096 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1097 Then your kernel will automatically call out to a user mode "policy
1098 agent" (/sbin/hotplug) to load modules and set up software needed
1099 to use devices as you hotplug them.
1101 source "drivers/pcmcia/Kconfig"
1103 source "drivers/pci/hotplug/Kconfig"
1107 menu "Executable file formats"
1109 source "fs/Kconfig.binfmt"
1113 menu "Power management options"
1114 source "kernel/power/Kconfig"
1116 config ARCH_SUSPEND_POSSIBLE
1121 prompt "Standby Power Saving Mode"
1123 default PM_BFIN_SLEEP_DEEPER
1124 config PM_BFIN_SLEEP_DEEPER
1127 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1128 power dissipation by disabling the clock to the processor core (CCLK).
1129 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1130 to 0.85 V to provide the greatest power savings, while preserving the
1132 The PLL and system clock (SCLK) continue to operate at a very low
1133 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1134 the SDRAM is put into Self Refresh Mode. Typically an external event
1135 such as GPIO interrupt or RTC activity wakes up the processor.
1136 Various Peripherals such as UART, SPORT, PPI may not function as
1137 normal during Sleep Deeper, due to the reduced SCLK frequency.
1138 When in the sleep mode, system DMA access to L1 memory is not supported.
1140 If unsure, select "Sleep Deeper".
1142 config PM_BFIN_SLEEP
1145 Sleep Mode (High Power Savings) - The sleep mode reduces power
1146 dissipation by disabling the clock to the processor core (CCLK).
1147 The PLL and system clock (SCLK), however, continue to operate in
1148 this mode. Typically an external event or RTC activity will wake
1149 up the processor. When in the sleep mode, system DMA access to L1
1150 memory is not supported.
1152 If unsure, select "Sleep Deeper".
1155 config PM_WAKEUP_BY_GPIO
1156 bool "Allow Wakeup from Standby by GPIO"
1157 depends on PM && !BF54x
1159 config PM_WAKEUP_GPIO_NUMBER
1162 depends on PM_WAKEUP_BY_GPIO
1166 prompt "GPIO Polarity"
1167 depends on PM_WAKEUP_BY_GPIO
1168 default PM_WAKEUP_GPIO_POLAR_H
1169 config PM_WAKEUP_GPIO_POLAR_H
1171 config PM_WAKEUP_GPIO_POLAR_L
1173 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1175 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1177 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1181 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1184 config PM_BFIN_WAKE_PH6
1185 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1186 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1189 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1191 config PM_BFIN_WAKE_GP
1192 bool "Allow Wake-Up from GPIOs"
1193 depends on PM && BF54x
1196 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1197 (all processors, except ADSP-BF549). This option sets
1198 the general-purpose wake-up enable (GPWE) control bit to enable
1199 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1200 On ADSP-BF549 this option enables the the same functionality on the
1201 /MRXON pin also PH7.
1205 menu "CPU Frequency scaling"
1207 source "drivers/cpufreq/Kconfig"
1209 config BFIN_CPU_FREQ
1212 select CPU_FREQ_TABLE
1216 bool "CPU Voltage scaling"
1217 depends on EXPERIMENTAL
1221 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1222 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1223 manuals. There is a theoretical risk that during VDDINT transitions
1228 source "net/Kconfig"
1230 source "drivers/Kconfig"
1234 source "arch/blackfin/Kconfig.debug"
1236 source "security/Kconfig"
1238 source "crypto/Kconfig"
1240 source "lib/Kconfig"