2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
18 config RWSEM_GENERIC_SPINLOCK
21 config RWSEM_XCHGADD_ALGORITHM
27 select HAVE_ARCH_TRACEHOOK
28 select HAVE_FUNCTION_GRAPH_TRACER
29 select HAVE_FUNCTION_TRACER
30 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
32 select HAVE_KERNEL_GZIP if RAMKERNEL
33 select HAVE_KERNEL_BZIP2 if RAMKERNEL
34 select HAVE_KERNEL_LZMA if RAMKERNEL
36 select ARCH_WANT_OPTIONAL_GPIOLIB
48 config GENERIC_FIND_NEXT_BIT
51 config GENERIC_HARDIRQS
54 config GENERIC_IRQ_PROBE
57 config GENERIC_HARDIRQS_NO__DO_IRQ
63 config FORCE_MAX_ZONEORDER
67 config GENERIC_CALIBRATE_DELAY
70 config LOCKDEP_SUPPORT
73 config STACKTRACE_SUPPORT
76 config TRACE_IRQFLAGS_SUPPORT
81 source "kernel/Kconfig.preempt"
83 source "kernel/Kconfig.freezer"
85 menu "Blackfin Processor Options"
87 comment "Processor and Board Settings"
96 BF512 Processor Support.
101 BF514 Processor Support.
106 BF516 Processor Support.
111 BF518 Processor Support.
116 BF522 Processor Support.
121 BF523 Processor Support.
126 BF524 Processor Support.
131 BF525 Processor Support.
136 BF526 Processor Support.
141 BF527 Processor Support.
146 BF531 Processor Support.
151 BF532 Processor Support.
156 BF533 Processor Support.
161 BF534 Processor Support.
166 BF536 Processor Support.
171 BF537 Processor Support.
176 BF538 Processor Support.
181 BF539 Processor Support.
186 BF542 Processor Support.
191 BF542 Processor Support.
196 BF544 Processor Support.
201 BF544 Processor Support.
206 BF547 Processor Support.
211 BF547 Processor Support.
216 BF548 Processor Support.
221 BF548 Processor Support.
226 BF549 Processor Support.
231 BF549 Processor Support.
236 BF561 Processor Support.
242 select TICKSOURCE_CORETMR
243 bool "Symmetric multi-processing support"
245 This enables support for systems with more than one CPU,
246 like the dual core BF561. If you have a system with only one
247 CPU, say N. If you have a system with more than one CPU, say Y.
249 If you don't know what to do here, say N.
257 bool "Support for hot-pluggable CPUs"
258 depends on SMP && HOTPLUG
266 config HAVE_LEGACY_PER_CPU_AREA
272 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
273 default 2 if (BF537 || BF536 || BF534)
274 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
275 default 4 if (BF538 || BF539)
279 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
280 default 3 if (BF537 || BF536 || BF534 || BF54xM)
281 default 5 if (BF561 || BF538 || BF539)
282 default 6 if (BF533 || BF532 || BF531)
286 default BF_REV_0_0 if (BF51x || BF52x)
287 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
288 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
292 depends on (BF51x || BF52x || (BF54x && !BF54xM))
296 depends on (BF51x || BF52x || (BF54x && !BF54xM))
300 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
304 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
308 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
312 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
316 depends on (BF533 || BF532 || BF531)
328 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
331 config MEM_GENERIC_BOARD
333 depends on GENERIC_BOARD
336 config MEM_MT48LC64M4A2FB_7E
338 depends on (BFIN533_STAMP)
341 config MEM_MT48LC16M16A2TG_75
343 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
344 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
345 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
346 || BFIN527_BLUETECHNIX_CM)
349 config MEM_MT48LC32M8A2_75
351 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
354 config MEM_MT48LC8M32B2B5_7
356 depends on (BFIN561_BLUETECHNIX_CM)
359 config MEM_MT48LC32M16A2TG_75
361 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
364 config MEM_MT48LC32M8A2_75
366 depends on (BFIN518F_EZBRD)
369 config MEM_MT48H32M16LFCJ_75
371 depends on (BFIN526_EZBRD)
374 source "arch/blackfin/mach-bf518/Kconfig"
375 source "arch/blackfin/mach-bf527/Kconfig"
376 source "arch/blackfin/mach-bf533/Kconfig"
377 source "arch/blackfin/mach-bf561/Kconfig"
378 source "arch/blackfin/mach-bf537/Kconfig"
379 source "arch/blackfin/mach-bf538/Kconfig"
380 source "arch/blackfin/mach-bf548/Kconfig"
382 menu "Board customizations"
385 bool "Default bootloader kernel arguments"
388 string "Initial kernel command string"
389 depends on CMDLINE_BOOL
390 default "console=ttyBF0,57600"
392 If you don't have a boot loader capable of passing a command line string
393 to the kernel, you may specify one here. As a minimum, you should specify
394 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
397 hex "Kernel load address for booting"
399 range 0x1000 0x20000000
401 This option allows you to set the load address of the kernel.
402 This can be useful if you are on a board which has a small amount
403 of memory or you wish to reserve some memory at the beginning of
406 Note that you need to keep this value above 4k (0x1000) as this
407 memory region is used to capture NULL pointer references as well
408 as some core kernel functions.
411 hex "Kernel ROM Base"
414 range 0x20000000 0x20400000 if !(BF54x || BF561)
415 range 0x20000000 0x30000000 if (BF54x || BF561)
417 Make sure your ROM base does not include any file-header
418 information that is prepended to the kernel.
420 For example, the bootable U-Boot format (created with
421 mkimage) has a 64 byte header (0x40). So while the image
422 you write to flash might start at say 0x20080000, you have
423 to add 0x40 to get the kernel's ROM base as it will come
426 comment "Clock/PLL Setup"
429 int "Frequency of the crystal on the board in Hz"
430 default "10000000" if BFIN532_IP0X
431 default "11059200" if BFIN533_STAMP
432 default "24576000" if PNAV10
433 default "25000000" # most people use this
434 default "27000000" if BFIN533_EZKIT
435 default "30000000" if BFIN561_EZKIT
437 The frequency of CLKIN crystal oscillator on the board in Hz.
438 Warning: This value should match the crystal on the board. Otherwise,
439 peripherals won't work properly.
441 config BFIN_KERNEL_CLOCK
442 bool "Re-program Clocks while Kernel boots?"
445 This option decides if kernel clocks are re-programed from the
446 bootloader settings. If the clocks are not set, the SDRAM settings
447 are also not changed, and the Bootloader does 100% of the hardware
452 depends on BFIN_KERNEL_CLOCK
457 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
460 If this is set the clock will be divided by 2, before it goes to the PLL.
464 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
466 default "22" if BFIN533_EZKIT
467 default "45" if BFIN533_STAMP
468 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
469 default "22" if BFIN533_BLUETECHNIX_CM
470 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
471 default "20" if BFIN561_EZKIT
472 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
474 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
475 PLL Frequency = (Crystal Frequency) * (this setting)
478 prompt "Core Clock Divider"
479 depends on BFIN_KERNEL_CLOCK
482 This sets the frequency of the core. It can be 1, 2, 4 or 8
483 Core Frequency = (PLL frequency) / (this setting)
499 int "System Clock Divider"
500 depends on BFIN_KERNEL_CLOCK
504 This sets the frequency of the system clock (including SDRAM or DDR).
505 This can be between 1 and 15
506 System Clock = (PLL frequency) / (this setting)
509 prompt "DDR SDRAM Chip Type"
510 depends on BFIN_KERNEL_CLOCK
512 default MEM_MT46V32M16_5B
514 config MEM_MT46V32M16_6T
517 config MEM_MT46V32M16_5B
522 prompt "DDR/SDRAM Timing"
523 depends on BFIN_KERNEL_CLOCK
524 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
526 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
527 The calculated SDRAM timing parameters may not be 100%
528 accurate - This option is therefore marked experimental.
530 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
531 bool "Calculate Timings (EXPERIMENTAL)"
532 depends on EXPERIMENTAL
534 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
535 bool "Provide accurate Timings based on target SCLK"
537 Please consult the Blackfin Hardware Reference Manuals as well
538 as the memory device datasheet.
539 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
542 menu "Memory Init Control"
543 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
560 config MEM_EBIU_DDRQUE
577 # Max & Min Speeds for various Chips
581 default 400000000 if BF512
582 default 400000000 if BF514
583 default 400000000 if BF516
584 default 400000000 if BF518
585 default 400000000 if BF522
586 default 600000000 if BF523
587 default 400000000 if BF524
588 default 600000000 if BF525
589 default 400000000 if BF526
590 default 600000000 if BF527
591 default 400000000 if BF531
592 default 400000000 if BF532
593 default 750000000 if BF533
594 default 500000000 if BF534
595 default 400000000 if BF536
596 default 600000000 if BF537
597 default 533333333 if BF538
598 default 533333333 if BF539
599 default 600000000 if BF542
600 default 533333333 if BF544
601 default 600000000 if BF547
602 default 600000000 if BF548
603 default 533333333 if BF549
604 default 600000000 if BF561
618 comment "Kernel Timer/Scheduler"
620 source kernel/Kconfig.hz
625 config GENERIC_CLOCKEVENTS
626 bool "Generic clock events"
629 menu "Clock event device"
630 depends on GENERIC_CLOCKEVENTS
631 config TICKSOURCE_GPTMR0
636 config TICKSOURCE_CORETMR
642 depends on GENERIC_CLOCKEVENTS
643 config CYCLES_CLOCKSOURCE
646 depends on !BFIN_SCRATCH_REG_CYCLES
649 If you say Y here, you will enable support for using the 'cycles'
650 registers as a clock source. Doing so means you will be unable to
651 safely write to the 'cycles' register during runtime. You will
652 still be able to read it (such as for performance monitoring), but
653 writing the registers will most likely crash the kernel.
655 config GPTMR0_CLOCKSOURCE
658 depends on !TICKSOURCE_GPTMR0
661 config ARCH_USES_GETTIMEOFFSET
662 depends on !GENERIC_CLOCKEVENTS
665 source kernel/time/Kconfig
670 prompt "Blackfin Exception Scratch Register"
671 default BFIN_SCRATCH_REG_RETN
673 Select the resource to reserve for the Exception handler:
674 - RETN: Non-Maskable Interrupt (NMI)
675 - RETE: Exception Return (JTAG/ICE)
676 - CYCLES: Performance counter
678 If you are unsure, please select "RETN".
680 config BFIN_SCRATCH_REG_RETN
683 Use the RETN register in the Blackfin exception handler
684 as a stack scratch register. This means you cannot
685 safely use NMI on the Blackfin while running Linux, but
686 you can debug the system with a JTAG ICE and use the
687 CYCLES performance registers.
689 If you are unsure, please select "RETN".
691 config BFIN_SCRATCH_REG_RETE
694 Use the RETE register in the Blackfin exception handler
695 as a stack scratch register. This means you cannot
696 safely use a JTAG ICE while debugging a Blackfin board,
697 but you can safely use the CYCLES performance registers
700 If you are unsure, please select "RETN".
702 config BFIN_SCRATCH_REG_CYCLES
705 Use the CYCLES register in the Blackfin exception handler
706 as a stack scratch register. This means you cannot
707 safely use the CYCLES performance registers on a Blackfin
708 board at anytime, but you can debug the system with a JTAG
711 If you are unsure, please select "RETN".
718 menu "Blackfin Kernel Optimizations"
721 comment "Memory Optimizations"
724 bool "Locate interrupt entry code in L1 Memory"
727 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
728 into L1 instruction memory. (less latency)
730 config EXCPT_IRQ_SYSC_L1
731 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
734 If enabled, the entire ASM lowlevel exception and interrupt entry code
735 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
739 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
742 If enabled, the frequently called do_irq dispatcher function is linked
743 into L1 instruction memory. (less latency)
745 config CORE_TIMER_IRQ_L1
746 bool "Locate frequently called timer_interrupt() function in L1 Memory"
749 If enabled, the frequently called timer_interrupt() function is linked
750 into L1 instruction memory. (less latency)
753 bool "Locate frequently idle function in L1 Memory"
756 If enabled, the frequently called idle function is linked
757 into L1 instruction memory. (less latency)
760 bool "Locate kernel schedule function in L1 Memory"
763 If enabled, the frequently called kernel schedule is linked
764 into L1 instruction memory. (less latency)
766 config ARITHMETIC_OPS_L1
767 bool "Locate kernel owned arithmetic functions in L1 Memory"
770 If enabled, arithmetic functions are linked
771 into L1 instruction memory. (less latency)
774 bool "Locate access_ok function in L1 Memory"
777 If enabled, the access_ok function is linked
778 into L1 instruction memory. (less latency)
781 bool "Locate memset function in L1 Memory"
784 If enabled, the memset function is linked
785 into L1 instruction memory. (less latency)
788 bool "Locate memcpy function in L1 Memory"
791 If enabled, the memcpy function is linked
792 into L1 instruction memory. (less latency)
795 bool "locate strcmp function in L1 Memory"
798 If enabled, the strcmp function is linked
799 into L1 instruction memory (less latency).
802 bool "locate strncmp function in L1 Memory"
805 If enabled, the strncmp function is linked
806 into L1 instruction memory (less latency).
809 bool "locate strcpy function in L1 Memory"
812 If enabled, the strcpy function is linked
813 into L1 instruction memory (less latency).
816 bool "locate strncpy function in L1 Memory"
819 If enabled, the strncpy function is linked
820 into L1 instruction memory (less latency).
822 config SYS_BFIN_SPINLOCK_L1
823 bool "Locate sys_bfin_spinlock function in L1 Memory"
826 If enabled, sys_bfin_spinlock function is linked
827 into L1 instruction memory. (less latency)
829 config IP_CHECKSUM_L1
830 bool "Locate IP Checksum function in L1 Memory"
833 If enabled, the IP Checksum function is linked
834 into L1 instruction memory. (less latency)
836 config CACHELINE_ALIGNED_L1
837 bool "Locate cacheline_aligned data to L1 Data Memory"
842 If enabled, cacheline_aligned data is linked
843 into L1 data memory. (less latency)
845 config SYSCALL_TAB_L1
846 bool "Locate Syscall Table L1 Data Memory"
850 If enabled, the Syscall LUT is linked
851 into L1 data memory. (less latency)
853 config CPLB_SWITCH_TAB_L1
854 bool "Locate CPLB Switch Tables L1 Data Memory"
858 If enabled, the CPLB Switch Tables are linked
859 into L1 data memory. (less latency)
862 bool "Support locating application stack in L1 Scratch Memory"
865 If enabled the application stack can be located in L1
866 scratch memory (less latency).
868 Currently only works with FLAT binaries.
870 config EXCEPTION_L1_SCRATCH
871 bool "Locate exception stack in L1 Scratch Memory"
873 depends on !APP_STACK_L1
875 Whenever an exception occurs, use the L1 Scratch memory for
876 stack storage. You cannot place the stacks of FLAT binaries
877 in L1 when using this option.
879 If you don't use L1 Scratch, then you should say Y here.
881 comment "Speed Optimizations"
882 config BFIN_INS_LOWOVERHEAD
883 bool "ins[bwl] low overhead, higher interrupt latency"
886 Reads on the Blackfin are speculative. In Blackfin terms, this means
887 they can be interrupted at any time (even after they have been issued
888 on to the external bus), and re-issued after the interrupt occurs.
889 For memory - this is not a big deal, since memory does not change if
892 If a FIFO is sitting on the end of the read, it will see two reads,
893 when the core only sees one since the FIFO receives both the read
894 which is cancelled (and not delivered to the core) and the one which
895 is re-issued (which is delivered to the core).
897 To solve this, interrupts are turned off before reads occur to
898 I/O space. This option controls which the overhead/latency of
899 controlling interrupts during this time
900 "n" turns interrupts off every read
901 (higher overhead, but lower interrupt latency)
902 "y" turns interrupts off every loop
903 (low overhead, but longer interrupt latency)
905 default behavior is to leave this set to on (type "Y"). If you are experiencing
906 interrupt latency issues, it is safe and OK to turn this off.
911 prompt "Kernel executes from"
913 Choose the memory type that the kernel will be running in.
918 The kernel will be resident in RAM when running.
923 The kernel will be resident in FLASH/ROM when running.
930 tristate "Enable Blackfin General Purpose Timers API"
933 Enable support for the General Purpose Timers API. If you
936 To compile this driver as a module, choose M here: the module
937 will be called gptimers.
940 prompt "Uncached DMA region"
941 default DMA_UNCACHED_1M
942 config DMA_UNCACHED_4M
943 bool "Enable 4M DMA region"
944 config DMA_UNCACHED_2M
945 bool "Enable 2M DMA region"
946 config DMA_UNCACHED_1M
947 bool "Enable 1M DMA region"
948 config DMA_UNCACHED_512K
949 bool "Enable 512K DMA region"
950 config DMA_UNCACHED_256K
951 bool "Enable 256K DMA region"
952 config DMA_UNCACHED_128K
953 bool "Enable 128K DMA region"
954 config DMA_UNCACHED_NONE
955 bool "Disable DMA region"
959 comment "Cache Support"
964 config BFIN_EXTMEM_ICACHEABLE
965 bool "Enable ICACHE for external memory"
966 depends on BFIN_ICACHE
968 config BFIN_L2_ICACHEABLE
969 bool "Enable ICACHE for L2 SRAM"
970 depends on BFIN_ICACHE
971 depends on BF54x || BF561
977 config BFIN_DCACHE_BANKA
978 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
979 depends on BFIN_DCACHE && !BF531
981 config BFIN_EXTMEM_DCACHEABLE
982 bool "Enable DCACHE for external memory"
983 depends on BFIN_DCACHE
986 prompt "External memory DCACHE policy"
987 depends on BFIN_EXTMEM_DCACHEABLE
988 default BFIN_EXTMEM_WRITEBACK if !SMP
989 default BFIN_EXTMEM_WRITETHROUGH if SMP
990 config BFIN_EXTMEM_WRITEBACK
995 Cached data will be written back to SDRAM only when needed.
996 This can give a nice increase in performance, but beware of
997 broken drivers that do not properly invalidate/flush their
1000 Write Through Policy:
1001 Cached data will always be written back to SDRAM when the
1002 cache is updated. This is a completely safe setting, but
1003 performance is worse than Write Back.
1005 If you are unsure of the options and you want to be safe,
1006 then go with Write Through.
1008 config BFIN_EXTMEM_WRITETHROUGH
1009 bool "Write through"
1012 Cached data will be written back to SDRAM only when needed.
1013 This can give a nice increase in performance, but beware of
1014 broken drivers that do not properly invalidate/flush their
1017 Write Through Policy:
1018 Cached data will always be written back to SDRAM when the
1019 cache is updated. This is a completely safe setting, but
1020 performance is worse than Write Back.
1022 If you are unsure of the options and you want to be safe,
1023 then go with Write Through.
1027 config BFIN_L2_DCACHEABLE
1028 bool "Enable DCACHE for L2 SRAM"
1029 depends on BFIN_DCACHE
1030 depends on (BF54x || BF561) && !SMP
1033 prompt "L2 SRAM DCACHE policy"
1034 depends on BFIN_L2_DCACHEABLE
1035 default BFIN_L2_WRITEBACK
1036 config BFIN_L2_WRITEBACK
1039 config BFIN_L2_WRITETHROUGH
1040 bool "Write through"
1044 comment "Memory Protection Unit"
1046 bool "Enable the memory protection unit (EXPERIMENTAL)"
1049 Use the processor's MPU to protect applications from accessing
1050 memory they do not own. This comes at a performance penalty
1051 and is recommended only for debugging.
1053 comment "Asynchronous Memory Configuration"
1055 menu "EBIU_AMGCTL Global Control"
1057 bool "Enable CLKOUT"
1061 bool "DMA has priority over core for ext. accesses"
1066 bool "Bank 0 16 bit packing enable"
1071 bool "Bank 1 16 bit packing enable"
1076 bool "Bank 2 16 bit packing enable"
1081 bool "Bank 3 16 bit packing enable"
1085 prompt "Enable Asynchronous Memory Banks"
1089 bool "Disable All Banks"
1092 bool "Enable Bank 0"
1094 config C_AMBEN_B0_B1
1095 bool "Enable Bank 0 & 1"
1097 config C_AMBEN_B0_B1_B2
1098 bool "Enable Bank 0 & 1 & 2"
1101 bool "Enable All Banks"
1105 menu "EBIU_AMBCTL Control"
1107 hex "Bank 0 (AMBCTL0.L)"
1110 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1111 used to control the Asynchronous Memory Bank 0 settings.
1114 hex "Bank 1 (AMBCTL0.H)"
1116 default 0x5558 if BF54x
1118 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1119 used to control the Asynchronous Memory Bank 1 settings.
1122 hex "Bank 2 (AMBCTL1.L)"
1125 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1126 used to control the Asynchronous Memory Bank 2 settings.
1129 hex "Bank 3 (AMBCTL1.H)"
1132 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1133 used to control the Asynchronous Memory Bank 3 settings.
1137 config EBIU_MBSCTLVAL
1138 hex "EBIU Bank Select Control Register"
1143 hex "Flash Memory Mode Control Register"
1148 hex "Flash Memory Bank Control Register"
1153 #############################################################################
1154 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1160 Support for PCI bus.
1162 source "drivers/pci/Kconfig"
1164 source "drivers/pcmcia/Kconfig"
1166 source "drivers/pci/hotplug/Kconfig"
1170 menu "Executable file formats"
1172 source "fs/Kconfig.binfmt"
1176 menu "Power management options"
1178 source "kernel/power/Kconfig"
1180 config ARCH_SUSPEND_POSSIBLE
1184 prompt "Standby Power Saving Mode"
1186 default PM_BFIN_SLEEP_DEEPER
1187 config PM_BFIN_SLEEP_DEEPER
1190 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1191 power dissipation by disabling the clock to the processor core (CCLK).
1192 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1193 to 0.85 V to provide the greatest power savings, while preserving the
1195 The PLL and system clock (SCLK) continue to operate at a very low
1196 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1197 the SDRAM is put into Self Refresh Mode. Typically an external event
1198 such as GPIO interrupt or RTC activity wakes up the processor.
1199 Various Peripherals such as UART, SPORT, PPI may not function as
1200 normal during Sleep Deeper, due to the reduced SCLK frequency.
1201 When in the sleep mode, system DMA access to L1 memory is not supported.
1203 If unsure, select "Sleep Deeper".
1205 config PM_BFIN_SLEEP
1208 Sleep Mode (High Power Savings) - The sleep mode reduces power
1209 dissipation by disabling the clock to the processor core (CCLK).
1210 The PLL and system clock (SCLK), however, continue to operate in
1211 this mode. Typically an external event or RTC activity will wake
1212 up the processor. When in the sleep mode, system DMA access to L1
1213 memory is not supported.
1215 If unsure, select "Sleep Deeper".
1218 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1221 config PM_BFIN_WAKE_PH6
1222 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1223 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1226 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1228 config PM_BFIN_WAKE_GP
1229 bool "Allow Wake-Up from GPIOs"
1230 depends on PM && BF54x
1233 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1234 (all processors, except ADSP-BF549). This option sets
1235 the general-purpose wake-up enable (GPWE) control bit to enable
1236 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1237 On ADSP-BF549 this option enables the the same functionality on the
1238 /MRXON pin also PH7.
1242 menu "CPU Frequency scaling"
1244 source "drivers/cpufreq/Kconfig"
1246 config BFIN_CPU_FREQ
1249 select CPU_FREQ_TABLE
1253 bool "CPU Voltage scaling"
1254 depends on EXPERIMENTAL
1258 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1259 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1260 manuals. There is a theoretical risk that during VDDINT transitions
1265 source "net/Kconfig"
1267 source "drivers/Kconfig"
1269 source "drivers/firmware/Kconfig"
1273 source "arch/blackfin/Kconfig.debug"
1275 source "security/Kconfig"
1277 source "crypto/Kconfig"
1279 source "lib/Kconfig"