2 * Support for Versatile FPGA-based IRQ controllers
6 #include <linux/irqdomain.h>
7 #include <linux/module.h>
9 #include <asm/exception.h>
10 #include <asm/mach/irq.h>
11 #include <plat/fpga-irq.h>
13 #define IRQ_STATUS 0x00
14 #define IRQ_RAW_STATUS 0x04
15 #define IRQ_ENABLE_SET 0x08
16 #define IRQ_ENABLE_CLEAR 0x0c
19 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
20 * @base: memory offset in virtual memory
21 * @irq_start: first IRQ number handled by this instance
22 * @chip: chip container for this instance
23 * @domain: IRQ domain for this instance
24 * @valid: mask for valid IRQs on this controller
25 * @used_irqs: number of active IRQs on this controller
27 struct fpga_irq_data {
29 unsigned int irq_start;
32 struct irq_domain *domain;
36 /* we cannot allocate memory when the controllers are initially registered */
37 static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
38 static int fpga_irq_id;
40 static void fpga_irq_mask(struct irq_data *d)
42 struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
43 u32 mask = 1 << d->hwirq;
45 writel(mask, f->base + IRQ_ENABLE_CLEAR);
48 static void fpga_irq_unmask(struct irq_data *d)
50 struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
51 u32 mask = 1 << d->hwirq;
53 writel(mask, f->base + IRQ_ENABLE_SET);
56 static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
58 struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
59 u32 status = readl(f->base + IRQ_STATUS);
62 do_bad_IRQ(irq, desc);
67 irq = ffs(status) - 1;
68 status &= ~(1 << irq);
69 generic_handle_irq(irq_find_mapping(f->domain, irq));
74 * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
75 * if we've handled at least one interrupt. This does a single read of the
76 * status register and handles all interrupts in order from LSB first.
78 static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
84 while ((status = readl(f->base + IRQ_STATUS))) {
85 irq = ffs(status) - 1;
86 handle_IRQ(irq_find_mapping(f->domain, irq), regs);
94 * Keep iterating over all registered FPGA IRQ controllers until there are
95 * no pending interrupts.
97 asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
102 for (i = 0, handled = 0; i < fpga_irq_id; ++i)
103 handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
107 static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
108 irq_hw_number_t hwirq)
110 struct fpga_irq_data *f = d->host_data;
112 /* Skip invalid IRQs, only register handlers for the real ones */
113 if (!(f->valid & (1 << hwirq)))
115 irq_set_chip_data(irq, f);
116 irq_set_chip_and_handler(irq, &f->chip,
118 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
123 static struct irq_domain_ops fpga_irqdomain_ops = {
124 .map = fpga_irqdomain_map,
125 .xlate = irq_domain_xlate_onetwocell,
128 void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
129 int parent_irq, u32 valid, struct device_node *node)
131 struct fpga_irq_data *f;
133 if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
134 printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
138 f = &fpga_irq_devices[fpga_irq_id];
140 f->irq_start = irq_start;
142 f->chip.irq_ack = fpga_irq_mask;
143 f->chip.irq_mask = fpga_irq_mask;
144 f->chip.irq_unmask = fpga_irq_unmask;
147 if (parent_irq != -1) {
148 irq_set_handler_data(parent_irq, f);
149 irq_set_chained_handler(parent_irq, fpga_irq_handle);
152 f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0,
153 &fpga_irqdomain_ops, f);
154 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
155 fpga_irq_id, name, base, f->used_irqs);