arch/arm/plat-s3c24xx/irq.c

   1 /* linux/arch/arm/plat-s3c24xx/irq.c
   2  *
   3  * Copyright (c) 2003,2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  * Changelog:
  21  *
  22  *   22-Jul-2004  Ben Dooks <ben@simtec.co.uk>
  23  *                Fixed compile warnings
  24  *
  25  *   22-Jul-2004  Roc Wu <cooloney@yahoo.com.cn>
  26  *                Fixed s3c_extirq_type
  27  *
  28  *   21-Jul-2004  Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
  29  *                Addition of ADC/TC demux
  30  *
  31  *   04-Oct-2004  Klaus Fetscher <k.fetscher@fetron.de>
  32  *                Fix for set_irq_type() on low EINT numbers
  33  *
  34  *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
  35  *                Tidy up KF's patch and sort out new release
  36  *
  37  *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
  38  *                Add support for power management controls
  39  *
  40  *   04-Nov-2004  Ben Dooks
  41  *                Fix standard IRQ wake for EINT0..4 and RTC
  42  *
  43  *   22-Feb-2005  Ben Dooks
  44  *                Fixed edge-triggering on ADC IRQ
  45  *
  46  *   28-Jun-2005  Ben Dooks
  47  *                Mark IRQ_LCD valid
  48  *
  49  *   25-Jul-2005  Ben Dooks
  50  *                Split the S3C2440 IRQ code to separate file
  51 */
  52
  53 #include <linux/init.h>
  54 #include <linux/module.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/ioport.h>
  57 #include <linux/sysdev.h>
  58
  59 #include <asm/irq.h>
  60 #include <asm/mach/irq.h>
  61
  62 #include <plat/regs-irqtype.h>
  63
  64 #include <plat/cpu.h>
  65 #include <plat/pm.h>
  66 #include <plat/irq.h>
  67
  68 static void
  69 s3c_irq_mask(unsigned int irqno)
  70 {
  71         unsigned long mask;
  72
  73         irqno -= IRQ_EINT0;
  74
  75         mask = __raw_readl(S3C2410_INTMSK);
  76         mask |= 1UL << irqno;
  77         __raw_writel(mask, S3C2410_INTMSK);
  78 }
  79
  80 static inline void
  81 s3c_irq_ack(unsigned int irqno)
  82 {
  83         unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
  84
  85         __raw_writel(bitval, S3C2410_SRCPND);
  86         __raw_writel(bitval, S3C2410_INTPND);
  87 }
  88
  89 static inline void
  90 s3c_irq_maskack(unsigned int irqno)
  91 {
  92         unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
  93         unsigned long mask;
  94
  95         mask = __raw_readl(S3C2410_INTMSK);
  96         __raw_writel(mask|bitval, S3C2410_INTMSK);
  97
  98         __raw_writel(bitval, S3C2410_SRCPND);
  99         __raw_writel(bitval, S3C2410_INTPND);
 100 }
 101
 102
 103 static void
 104 s3c_irq_unmask(unsigned int irqno)
 105 {
 106         unsigned long mask;
 107
 108         if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
 109                 irqdbf2("s3c_irq_unmask %d\n", irqno);
 110
 111         irqno -= IRQ_EINT0;
 112
 113         mask = __raw_readl(S3C2410_INTMSK);
 114         mask &= ~(1UL << irqno);
 115         __raw_writel(mask, S3C2410_INTMSK);
 116 }
 117
 118 struct irq_chip s3c_irq_level_chip = {
 119         .name           = "s3c-level",
 120         .ack            = s3c_irq_maskack,
 121         .mask           = s3c_irq_mask,
 122         .unmask         = s3c_irq_unmask,
 123         .set_wake       = s3c_irq_wake
 124 };
 125
 126 struct irq_chip s3c_irq_chip = {
 127         .name           = "s3c",
 128         .ack            = s3c_irq_ack,
 129         .mask           = s3c_irq_mask,
 130         .unmask         = s3c_irq_unmask,
 131         .set_wake       = s3c_irq_wake
 132 };
 133
 134 static void
 135 s3c_irqext_mask(unsigned int irqno)
 136 {
 137         unsigned long mask;
 138
 139         irqno -= EXTINT_OFF;
 140
 141         mask = __raw_readl(S3C24XX_EINTMASK);
 142         mask |= ( 1UL << irqno);
 143         __raw_writel(mask, S3C24XX_EINTMASK);
 144 }
 145
 146 static void
 147 s3c_irqext_ack(unsigned int irqno)
 148 {
 149         unsigned long req;
 150         unsigned long bit;
 151         unsigned long mask;
 152
 153         bit = 1UL << (irqno - EXTINT_OFF);
 154
 155         mask = __raw_readl(S3C24XX_EINTMASK);
 156
 157         __raw_writel(bit, S3C24XX_EINTPEND);
 158
 159         req = __raw_readl(S3C24XX_EINTPEND);
 160         req &= ~mask;
 161
 162         /* not sure if we should be acking the parent irq... */
 163
 164         if (irqno <= IRQ_EINT7 ) {
 165                 if ((req & 0xf0) == 0)
 166                         s3c_irq_ack(IRQ_EINT4t7);
 167         } else {
 168                 if ((req >> 8) == 0)
 169                         s3c_irq_ack(IRQ_EINT8t23);
 170         }
 171 }
 172
 173 static void
 174 s3c_irqext_unmask(unsigned int irqno)
 175 {
 176         unsigned long mask;
 177
 178         irqno -= EXTINT_OFF;
 179
 180         mask = __raw_readl(S3C24XX_EINTMASK);
 181         mask &= ~( 1UL << irqno);
 182         __raw_writel(mask, S3C24XX_EINTMASK);
 183 }
 184
 185 int
 186 s3c_irqext_type(unsigned int irq, unsigned int type)
 187 {
 188         void __iomem *extint_reg;
 189         void __iomem *gpcon_reg;
 190         unsigned long gpcon_offset, extint_offset;
 191         unsigned long newvalue = 0, value;
 192
 193         if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
 194         {
 195                 gpcon_reg = S3C2410_GPFCON;
 196                 extint_reg = S3C24XX_EXTINT0;
 197                 gpcon_offset = (irq - IRQ_EINT0) * 2;
 198                 extint_offset = (irq - IRQ_EINT0) * 4;
 199         }
 200         else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
 201         {
 202                 gpcon_reg = S3C2410_GPFCON;
 203                 extint_reg = S3C24XX_EXTINT0;
 204                 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
 205                 extint_offset = (irq - (EXTINT_OFF)) * 4;
 206         }
 207         else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
 208         {
 209                 gpcon_reg = S3C2410_GPGCON;
 210                 extint_reg = S3C24XX_EXTINT1;
 211                 gpcon_offset = (irq - IRQ_EINT8) * 2;
 212                 extint_offset = (irq - IRQ_EINT8) * 4;
 213         }
 214         else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
 215         {
 216                 gpcon_reg = S3C2410_GPGCON;
 217                 extint_reg = S3C24XX_EXTINT2;
 218                 gpcon_offset = (irq - IRQ_EINT8) * 2;
 219                 extint_offset = (irq - IRQ_EINT16) * 4;
 220         } else
 221                 return -1;
 222
 223         /* Set the GPIO to external interrupt mode */
 224         value = __raw_readl(gpcon_reg);
 225         value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
 226         __raw_writel(value, gpcon_reg);
 227
 228         /* Set the external interrupt to pointed trigger type */
 229         switch (type)
 230         {
 231                 case IRQ_TYPE_NONE:
 232                         printk(KERN_WARNING "No edge setting!\n");
 233                         break;
 234
 235                 case IRQ_TYPE_EDGE_RISING:
 236                         newvalue = S3C2410_EXTINT_RISEEDGE;
 237                         break;
 238
 239                 case IRQ_TYPE_EDGE_FALLING:
 240                         newvalue = S3C2410_EXTINT_FALLEDGE;
 241                         break;
 242
 243                 case IRQ_TYPE_EDGE_BOTH:
 244                         newvalue = S3C2410_EXTINT_BOTHEDGE;
 245                         break;
 246
 247                 case IRQ_TYPE_LEVEL_LOW:
 248                         newvalue = S3C2410_EXTINT_LOWLEV;
 249                         break;
 250
 251                 case IRQ_TYPE_LEVEL_HIGH:
 252                         newvalue = S3C2410_EXTINT_HILEV;
 253                         break;
 254
 255                 default:
 256                         printk(KERN_ERR "No such irq type %d", type);
 257                         return -1;
 258         }
 259
 260         value = __raw_readl(extint_reg);
 261         value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
 262         __raw_writel(value, extint_reg);
 263
 264         return 0;
 265 }
 266
 267 static struct irq_chip s3c_irqext_chip = {
 268         .name           = "s3c-ext",
 269         .mask           = s3c_irqext_mask,
 270         .unmask         = s3c_irqext_unmask,
 271         .ack            = s3c_irqext_ack,
 272         .set_type       = s3c_irqext_type,
 273         .set_wake       = s3c_irqext_wake
 274 };
 275
 276 static struct irq_chip s3c_irq_eint0t4 = {
 277         .name           = "s3c-ext0",
 278         .ack            = s3c_irq_ack,
 279         .mask           = s3c_irq_mask,
 280         .unmask         = s3c_irq_unmask,
 281         .set_wake       = s3c_irq_wake,
 282         .set_type       = s3c_irqext_type,
 283 };
 284
 285 /* mask values for the parent registers for each of the interrupt types */
 286
 287 #define INTMSK_UART0     (1UL << (IRQ_UART0 - IRQ_EINT0))
 288 #define INTMSK_UART1     (1UL << (IRQ_UART1 - IRQ_EINT0))
 289 #define INTMSK_UART2     (1UL << (IRQ_UART2 - IRQ_EINT0))
 290 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
 291
 292
 293 /* UART0 */
 294
 295 static void
 296 s3c_irq_uart0_mask(unsigned int irqno)
 297 {
 298         s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
 299 }
 300
 301 static void
 302 s3c_irq_uart0_unmask(unsigned int irqno)
 303 {
 304         s3c_irqsub_unmask(irqno, INTMSK_UART0);
 305 }
 306
 307 static void
 308 s3c_irq_uart0_ack(unsigned int irqno)
 309 {
 310         s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
 311 }
 312
 313 static struct irq_chip s3c_irq_uart0 = {
 314         .name           = "s3c-uart0",
 315         .mask           = s3c_irq_uart0_mask,
 316         .unmask         = s3c_irq_uart0_unmask,
 317         .ack            = s3c_irq_uart0_ack,
 318 };
 319
 320 /* UART1 */
 321
 322 static void
 323 s3c_irq_uart1_mask(unsigned int irqno)
 324 {
 325         s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
 326 }
 327
 328 static void
 329 s3c_irq_uart1_unmask(unsigned int irqno)
 330 {
 331         s3c_irqsub_unmask(irqno, INTMSK_UART1);
 332 }
 333
 334 static void
 335 s3c_irq_uart1_ack(unsigned int irqno)
 336 {
 337         s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
 338 }
 339
 340 static struct irq_chip s3c_irq_uart1 = {
 341         .name           = "s3c-uart1",
 342         .mask           = s3c_irq_uart1_mask,
 343         .unmask         = s3c_irq_uart1_unmask,
 344         .ack            = s3c_irq_uart1_ack,
 345 };
 346
 347 /* UART2 */
 348
 349 static void
 350 s3c_irq_uart2_mask(unsigned int irqno)
 351 {
 352         s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
 353 }
 354
 355 static void
 356 s3c_irq_uart2_unmask(unsigned int irqno)
 357 {
 358         s3c_irqsub_unmask(irqno, INTMSK_UART2);
 359 }
 360
 361 static void
 362 s3c_irq_uart2_ack(unsigned int irqno)
 363 {
 364         s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
 365 }
 366
 367 static struct irq_chip s3c_irq_uart2 = {
 368         .name           = "s3c-uart2",
 369         .mask           = s3c_irq_uart2_mask,
 370         .unmask         = s3c_irq_uart2_unmask,
 371         .ack            = s3c_irq_uart2_ack,
 372 };
 373
 374 /* ADC and Touchscreen */
 375
 376 static void
 377 s3c_irq_adc_mask(unsigned int irqno)
 378 {
 379         s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
 380 }
 381
 382 static void
 383 s3c_irq_adc_unmask(unsigned int irqno)
 384 {
 385         s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
 386 }
 387
 388 static void
 389 s3c_irq_adc_ack(unsigned int irqno)
 390 {
 391         s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
 392 }
 393
 394 static struct irq_chip s3c_irq_adc = {
 395         .name           = "s3c-adc",
 396         .mask           = s3c_irq_adc_mask,
 397         .unmask         = s3c_irq_adc_unmask,
 398         .ack            = s3c_irq_adc_ack,
 399 };
 400
 401 /* irq demux for adc */
 402 static void s3c_irq_demux_adc(unsigned int irq,
 403                               struct irq_desc *desc)
 404 {
 405         unsigned int subsrc, submsk;
 406         unsigned int offset = 9;
 407
 408         /* read the current pending interrupts, and the mask
 409          * for what it is available */
 410
 411         subsrc = __raw_readl(S3C2410_SUBSRCPND);
 412         submsk = __raw_readl(S3C2410_INTSUBMSK);
 413
 414         subsrc &= ~submsk;
 415         subsrc >>= offset;
 416         subsrc &= 3;
 417
 418         if (subsrc != 0) {
 419                 if (subsrc & 1) {
 420                         generic_handle_irq(IRQ_TC);
 421                 }
 422                 if (subsrc & 2) {
 423                         generic_handle_irq(IRQ_ADC);
 424                 }
 425         }
 426 }
 427
 428 static void s3c_irq_demux_uart(unsigned int start)
 429 {
 430         unsigned int subsrc, submsk;
 431         unsigned int offset = start - IRQ_S3CUART_RX0;
 432
 433         /* read the current pending interrupts, and the mask
 434          * for what it is available */
 435
 436         subsrc = __raw_readl(S3C2410_SUBSRCPND);
 437         submsk = __raw_readl(S3C2410_INTSUBMSK);
 438
 439         irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
 440                 start, offset, subsrc, submsk);
 441
 442         subsrc &= ~submsk;
 443         subsrc >>= offset;
 444         subsrc &= 7;
 445
 446         if (subsrc != 0) {
 447                 if (subsrc & 1)
 448                         generic_handle_irq(start);
 449
 450                 if (subsrc & 2)
 451                         generic_handle_irq(start+1);
 452
 453                 if (subsrc & 4)
 454                         generic_handle_irq(start+2);
 455         }
 456 }
 457
 458 /* uart demux entry points */
 459
 460 static void
 461 s3c_irq_demux_uart0(unsigned int irq,
 462                     struct irq_desc *desc)
 463 {
 464         irq = irq;
 465         s3c_irq_demux_uart(IRQ_S3CUART_RX0);
 466 }
 467
 468 static void
 469 s3c_irq_demux_uart1(unsigned int irq,
 470                     struct irq_desc *desc)
 471 {
 472         irq = irq;
 473         s3c_irq_demux_uart(IRQ_S3CUART_RX1);
 474 }
 475
 476 static void
 477 s3c_irq_demux_uart2(unsigned int irq,
 478                     struct irq_desc *desc)
 479 {
 480         irq = irq;
 481         s3c_irq_demux_uart(IRQ_S3CUART_RX2);
 482 }
 483
 484 static void
 485 s3c_irq_demux_extint8(unsigned int irq,
 486                       struct irq_desc *desc)
 487 {
 488         unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
 489         unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
 490
 491         eintpnd &= ~eintmsk;
 492         eintpnd &= ~0xff;       /* ignore lower irqs */
 493
 494         /* we may as well handle all the pending IRQs here */
 495
 496         while (eintpnd) {
 497                 irq = __ffs(eintpnd);
 498                 eintpnd &= ~(1<<irq);
 499
 500                 irq += (IRQ_EINT4 - 4);
 501                 generic_handle_irq(irq);
 502         }
 503
 504 }
 505
 506 static void
 507 s3c_irq_demux_extint4t7(unsigned int irq,
 508                         struct irq_desc *desc)
 509 {
 510         unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
 511         unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
 512
 513         eintpnd &= ~eintmsk;
 514         eintpnd &= 0xff;        /* only lower irqs */
 515
 516         /* we may as well handle all the pending IRQs here */
 517
 518         while (eintpnd) {
 519                 irq = __ffs(eintpnd);
 520                 eintpnd &= ~(1<<irq);
 521
 522                 irq += (IRQ_EINT4 - 4);
 523
 524                 generic_handle_irq(irq);
 525         }
 526 }
 527
 528 /* s3c24xx_init_irq
 529  *
 530  * Initialise S3C2410 IRQ system
 531 */
 532
 533 void __init s3c24xx_init_irq(void)
 534 {
 535         unsigned long pend;
 536         unsigned long last;
 537         int irqno;
 538         int i;
 539
 540         irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
 541
 542         /* first, clear all interrupts pending... */
 543
 544         last = 0;
 545         for (i = 0; i < 4; i++) {
 546                 pend = __raw_readl(S3C24XX_EINTPEND);
 547
 548                 if (pend == 0 || pend == last)
 549                         break;
 550
 551                 __raw_writel(pend, S3C24XX_EINTPEND);
 552                 printk("irq: clearing pending ext status %08x\n", (int)pend);
 553                 last = pend;
 554         }
 555
 556         last = 0;
 557         for (i = 0; i < 4; i++) {
 558                 pend = __raw_readl(S3C2410_INTPND);
 559
 560                 if (pend == 0 || pend == last)
 561                         break;
 562
 563                 __raw_writel(pend, S3C2410_SRCPND);
 564                 __raw_writel(pend, S3C2410_INTPND);
 565                 printk("irq: clearing pending status %08x\n", (int)pend);
 566                 last = pend;
 567         }
 568
 569         last = 0;
 570         for (i = 0; i < 4; i++) {
 571                 pend = __raw_readl(S3C2410_SUBSRCPND);
 572
 573                 if (pend == 0 || pend == last)
 574                         break;
 575
 576                 printk("irq: clearing subpending status %08x\n", (int)pend);
 577                 __raw_writel(pend, S3C2410_SUBSRCPND);
 578                 last = pend;
 579         }
 580
 581         /* register the main interrupts */
 582
 583         irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
 584
 585         for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
 586                 /* set all the s3c2410 internal irqs */
 587
 588                 switch (irqno) {
 589                         /* deal with the special IRQs (cascaded) */
 590
 591                 case IRQ_EINT4t7:
 592                 case IRQ_EINT8t23:
 593                 case IRQ_UART0:
 594                 case IRQ_UART1:
 595                 case IRQ_UART2:
 596                 case IRQ_ADCPARENT:
 597                         set_irq_chip(irqno, &s3c_irq_level_chip);
 598                         set_irq_handler(irqno, handle_level_irq);
 599                         break;
 600
 601                 case IRQ_RESERVED6:
 602                 case IRQ_RESERVED24:
 603                         /* no IRQ here */
 604                         break;
 605
 606                 default:
 607                         //irqdbf("registering irq %d (s3c irq)\n", irqno);
 608                         set_irq_chip(irqno, &s3c_irq_chip);
 609                         set_irq_handler(irqno, handle_edge_irq);
 610                         set_irq_flags(irqno, IRQF_VALID);
 611                 }
 612         }
 613
 614         /* setup the cascade irq handlers */
 615
 616         set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
 617         set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
 618
 619         set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
 620         set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
 621         set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
 622         set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
 623
 624         /* external interrupts */
 625
 626         for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
 627                 irqdbf("registering irq %d (ext int)\n", irqno);
 628                 set_irq_chip(irqno, &s3c_irq_eint0t4);
 629                 set_irq_handler(irqno, handle_edge_irq);
 630                 set_irq_flags(irqno, IRQF_VALID);
 631         }
 632
 633         for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
 634                 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
 635                 set_irq_chip(irqno, &s3c_irqext_chip);
 636                 set_irq_handler(irqno, handle_edge_irq);
 637                 set_irq_flags(irqno, IRQF_VALID);
 638         }
 639
 640         /* register the uart interrupts */
 641
 642         irqdbf("s3c2410: registering external interrupts\n");
 643
 644         for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
 645                 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
 646                 set_irq_chip(irqno, &s3c_irq_uart0);
 647                 set_irq_handler(irqno, handle_level_irq);
 648                 set_irq_flags(irqno, IRQF_VALID);
 649         }
 650
 651         for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
 652                 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
 653                 set_irq_chip(irqno, &s3c_irq_uart1);
 654                 set_irq_handler(irqno, handle_level_irq);
 655                 set_irq_flags(irqno, IRQF_VALID);
 656         }
 657
 658         for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
 659                 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
 660                 set_irq_chip(irqno, &s3c_irq_uart2);
 661                 set_irq_handler(irqno, handle_level_irq);
 662                 set_irq_flags(irqno, IRQF_VALID);
 663         }
 664
 665         for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
 666                 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
 667                 set_irq_chip(irqno, &s3c_irq_adc);
 668                 set_irq_handler(irqno, handle_edge_irq);
 669                 set_irq_flags(irqno, IRQF_VALID);
 670         }
 671
 672         irqdbf("s3c2410: registered interrupt handlers\n");
 673 }