2 * arch/arm/plat-orion/time.c
4 * Marvell Orion SoC timer handling.
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
10 * Timer 0 is used as free-running clocksource, while timer 1 is
11 * used as clock_event_device.
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/timer.h>
17 #include <linux/clockchips.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <asm/sched_clock.h>
23 * MBus bridge block registers.
25 #define BRIDGE_CAUSE_OFF 0x0110
26 #define BRIDGE_MASK_OFF 0x0114
27 #define BRIDGE_INT_TIMER0 0x0002
28 #define BRIDGE_INT_TIMER1 0x0004
32 * Timer block registers.
34 #define TIMER_CTRL_OFF 0x0000
35 #define TIMER0_EN 0x0001
36 #define TIMER0_RELOAD_EN 0x0002
37 #define TIMER1_EN 0x0004
38 #define TIMER1_RELOAD_EN 0x0008
39 #define TIMER0_RELOAD_OFF 0x0010
40 #define TIMER0_VAL_OFF 0x0014
41 #define TIMER1_RELOAD_OFF 0x0018
42 #define TIMER1_VAL_OFF 0x001c
48 static void __iomem *bridge_base;
49 static u32 bridge_timer1_clr_mask;
50 static void __iomem *timer_base;
54 * Number of timer ticks per jiffy.
56 static u32 ticks_per_jiffy;
60 * Orion's sched_clock implementation. It has a resolution of
61 * at least 7.5ns (133MHz TCLK).
63 static DEFINE_CLOCK_DATA(cd);
65 unsigned long long notrace sched_clock(void)
67 u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
68 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
72 static void notrace orion_update_sched_clock(void)
74 u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
75 update_sched_clock(&cd, cyc, (u32)~0);
78 static void __init setup_sched_clock(unsigned long tclk)
80 init_sched_clock(&cd, orion_update_sched_clock, 32, tclk);
84 * Clocksource handling.
86 static cycle_t orion_clksrc_read(struct clocksource *cs)
88 return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
91 static struct clocksource orion_clksrc = {
92 .name = "orion_clocksource",
94 .read = orion_clksrc_read,
95 .mask = CLOCKSOURCE_MASK(32),
96 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
102 * Clockevent handling.
105 orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
113 local_irq_save(flags);
116 * Clear and enable clockevent timer interrupt.
118 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
120 u = readl(bridge_base + BRIDGE_MASK_OFF);
121 u |= BRIDGE_INT_TIMER1;
122 writel(u, bridge_base + BRIDGE_MASK_OFF);
125 * Setup new clockevent timer value.
127 writel(delta, timer_base + TIMER1_VAL_OFF);
132 u = readl(timer_base + TIMER_CTRL_OFF);
133 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
134 writel(u, timer_base + TIMER_CTRL_OFF);
136 local_irq_restore(flags);
142 orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
147 local_irq_save(flags);
148 if (mode == CLOCK_EVT_MODE_PERIODIC) {
150 * Setup timer to fire at 1/HZ intervals.
152 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
153 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
156 * Enable timer interrupt.
158 u = readl(bridge_base + BRIDGE_MASK_OFF);
159 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
164 u = readl(timer_base + TIMER_CTRL_OFF);
165 writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
166 timer_base + TIMER_CTRL_OFF);
171 u = readl(timer_base + TIMER_CTRL_OFF);
172 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
175 * Disable timer interrupt.
177 u = readl(bridge_base + BRIDGE_MASK_OFF);
178 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
181 * ACK pending timer interrupt.
183 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
186 local_irq_restore(flags);
189 static struct clock_event_device orion_clkevt = {
190 .name = "orion_tick",
191 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
194 .set_next_event = orion_clkevt_next_event,
195 .set_mode = orion_clkevt_mode,
198 static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
201 * ACK timer interrupt and call event handler.
203 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
204 orion_clkevt.event_handler(&orion_clkevt);
209 static struct irqaction orion_timer_irq = {
210 .name = "orion_tick",
211 .flags = IRQF_DISABLED | IRQF_TIMER,
212 .handler = orion_timer_interrupt
216 orion_time_set_base(u32 _timer_base)
218 timer_base = (void __iomem *)_timer_base;
222 orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
223 unsigned int irq, unsigned int tclk)
228 * Set SoC-specific data.
230 bridge_base = (void __iomem *)_bridge_base;
231 bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
233 ticks_per_jiffy = (tclk + HZ/2) / HZ;
236 * Set scale and timer for sched_clock.
238 setup_sched_clock(tclk);
241 * Setup free-running clocksource timer (interrupts
244 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
245 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
246 u = readl(bridge_base + BRIDGE_MASK_OFF);
247 writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
248 u = readl(timer_base + TIMER_CTRL_OFF);
249 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
250 clocksource_register_hz(&orion_clksrc, tclk);
253 * Setup clockevent timer (interrupt-driven).
255 setup_irq(irq, &orion_timer_irq);
256 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
257 orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
258 orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
259 orion_clkevt.cpumask = cpumask_of(0);
260 clockevents_register_device(&orion_clkevt);