fix mismerge in ll_rw_blk.c
[pandora-kernel.git] / arch / arm / plat-omap / mux.c
1 /*
2  * linux/arch/arm/plat-omap/mux.c
3  *
4  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
5  *
6  * Copyright (C) 2003 Nokia Corporation
7  *
8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23  *
24  */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <asm/system.h>
29 #include <asm/io.h>
30 #include <linux/spinlock.h>
31
32 #define __MUX_C__
33 #include <asm/arch/mux.h>
34
35 #ifdef CONFIG_OMAP_MUX
36
37 /*
38  * Sets the Omap MUX and PULL_DWN registers based on the table
39  */
40 int __init_or_module
41 omap_cfg_reg(const reg_cfg_t reg_cfg)
42 {
43         static DEFINE_SPINLOCK(mux_spin_lock);
44
45         unsigned long flags;
46         reg_cfg_set *cfg;
47         unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
48                 pull_orig = 0, pull = 0;
49         unsigned int mask, warn = 0;
50
51         if (reg_cfg > ARRAY_SIZE(reg_cfg_table)) {
52                 printk(KERN_ERR "MUX: reg_cfg %d\n", reg_cfg);
53                 return -EINVAL;
54         }
55
56         cfg = (reg_cfg_set *)&reg_cfg_table[reg_cfg];
57
58         /* Check the mux register in question */
59         if (cfg->mux_reg) {
60                 unsigned        tmp1, tmp2;
61
62                 spin_lock_irqsave(&mux_spin_lock, flags);
63                 reg_orig = omap_readl(cfg->mux_reg);
64
65                 /* The mux registers always seem to be 3 bits long */
66                 mask = (0x7 << cfg->mask_offset);
67                 tmp1 = reg_orig & mask;
68                 reg = reg_orig & ~mask;
69
70                 tmp2 = (cfg->mask << cfg->mask_offset);
71                 reg |= tmp2;
72
73                 if (tmp1 != tmp2)
74                         warn = 1;
75
76                 omap_writel(reg, cfg->mux_reg);
77                 spin_unlock_irqrestore(&mux_spin_lock, flags);
78         }
79
80         /* Check for pull up or pull down selection on 1610 */
81         if (!cpu_is_omap1510()) {
82                 if (cfg->pu_pd_reg && cfg->pull_val) {
83                         spin_lock_irqsave(&mux_spin_lock, flags);
84                         pu_pd_orig = omap_readl(cfg->pu_pd_reg);
85                         mask = 1 << cfg->pull_bit;
86
87                         if (cfg->pu_pd_val) {
88                                 if (!(pu_pd_orig & mask))
89                                         warn = 1;
90                                 /* Use pull up */
91                                 pu_pd = pu_pd_orig | mask;
92                         } else {
93                                 if (pu_pd_orig & mask)
94                                         warn = 1;
95                                 /* Use pull down */
96                                 pu_pd = pu_pd_orig & ~mask;
97                         }
98                         omap_writel(pu_pd, cfg->pu_pd_reg);
99                         spin_unlock_irqrestore(&mux_spin_lock, flags);
100                 }
101         }
102
103         /* Check for an associated pull down register */
104         if (cfg->pull_reg) {
105                 spin_lock_irqsave(&mux_spin_lock, flags);
106                 pull_orig = omap_readl(cfg->pull_reg);
107                 mask = 1 << cfg->pull_bit;
108
109                 if (cfg->pull_val) {
110                         if (pull_orig & mask)
111                                 warn = 1;
112                         /* Low bit = pull enabled */
113                         pull = pull_orig & ~mask;
114                 } else {
115                         if (!(pull_orig & mask))
116                                 warn = 1;
117                         /* High bit = pull disabled */
118                         pull = pull_orig | mask;
119                 }
120
121                 omap_writel(pull, cfg->pull_reg);
122                 spin_unlock_irqrestore(&mux_spin_lock, flags);
123         }
124
125         if (warn) {
126 #ifdef CONFIG_OMAP_MUX_WARNINGS
127                 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
128 #endif
129         }
130
131 #ifdef CONFIG_OMAP_MUX_DEBUG
132         if (cfg->debug || warn) {
133                 printk("MUX: Setting register %s\n", cfg->name);
134                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
135                        cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
136
137                 if (!cpu_is_omap1510()) {
138                         if (cfg->pu_pd_reg && cfg->pull_val) {
139                                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
140                                        cfg->pu_pd_name, cfg->pu_pd_reg,
141                                        pu_pd_orig, pu_pd);
142                         }
143                 }
144
145                 if (cfg->pull_reg)
146                         printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
147                                cfg->pull_name, cfg->pull_reg, pull_orig, pull);
148         }
149 #endif
150
151 #ifdef CONFIG_OMAP_MUX_ERRORS
152         return warn ? -ETXTBSY : 0;
153 #else
154         return 0;
155 #endif
156 }
157
158 EXPORT_SYMBOL(omap_cfg_reg);
159
160 #endif  /* CONFIG_OMAP_MUX */