arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27
  28 #include <plat/dma.h>
  29 #include <plat/mcbsp.h>
  30
  31 #include "../mach-omap2/cm-regbits-34xx.h"
  32
  33 struct omap_mcbsp **mcbsp_ptr;
  34 int omap_mcbsp_count, omap_mcbsp_cache_size;
  35
  36 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  37 {
  38         if (cpu_class_is_omap1()) {
  39                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
  40                 __raw_writew((u16)val, mcbsp->io_base + reg);
  41         } else if (cpu_is_omap2420()) {
  42                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
  43                 __raw_writew((u16)val, mcbsp->io_base + reg);
  44         } else {
  45                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
  46                 __raw_writel(val, mcbsp->io_base + reg);
  47         }
  48 }
  49
  50 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  51 {
  52         if (cpu_class_is_omap1()) {
  53                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  54                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
  55         } else if (cpu_is_omap2420()) {
  56                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  57                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  58         } else {
  59                 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
  60                                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  61         }
  62 }
  63
  64 #ifdef CONFIG_ARCH_OMAP3
  65 void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  66 {
  67         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  68 }
  69
  70 int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  71 {
  72         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  73 }
  74 #endif
  75
  76 #define MCBSP_READ(mcbsp, reg) \
  77                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  78 #define MCBSP_WRITE(mcbsp, reg, val) \
  79                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  80 #define MCBSP_READ_CACHE(mcbsp, reg) \
  81                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  82
  83 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  84 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  85
  86 #define MCBSP_ST_READ(mcbsp, reg) \
  87                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  88 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  89                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  90
  91 static void omap_mcbsp_dump_reg(u8 id)
  92 {
  93         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  94
  95         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  96         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  97                         MCBSP_READ(mcbsp, DRR2));
  98         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  99                         MCBSP_READ(mcbsp, DRR1));
 100         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
 101                         MCBSP_READ(mcbsp, DXR2));
 102         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
 103                         MCBSP_READ(mcbsp, DXR1));
 104         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
 105                         MCBSP_READ(mcbsp, SPCR2));
 106         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
 107                         MCBSP_READ(mcbsp, SPCR1));
 108         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
 109                         MCBSP_READ(mcbsp, RCR2));
 110         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 111                         MCBSP_READ(mcbsp, RCR1));
 112         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 113                         MCBSP_READ(mcbsp, XCR2));
 114         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 115                         MCBSP_READ(mcbsp, XCR1));
 116         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 117                         MCBSP_READ(mcbsp, SRGR2));
 118         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 119                         MCBSP_READ(mcbsp, SRGR1));
 120         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 121                         MCBSP_READ(mcbsp, PCR0));
 122         dev_dbg(mcbsp->dev, "***********************\n");
 123 }
 124
 125 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 126 {
 127         struct omap_mcbsp *mcbsp_tx = dev_id;
 128         u16 irqst_spcr2;
 129
 130         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 131         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 132
 133         if (irqst_spcr2 & XSYNC_ERR) {
 134                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 135                         irqst_spcr2);
 136                 /* Writing zero to XSYNC_ERR clears the IRQ */
 137                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 138         } else {
 139                 complete(&mcbsp_tx->tx_irq_completion);
 140         }
 141
 142         return IRQ_HANDLED;
 143 }
 144
 145 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 146 {
 147         struct omap_mcbsp *mcbsp_rx = dev_id;
 148         u16 irqst_spcr1;
 149
 150         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 151         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 152
 153         if (irqst_spcr1 & RSYNC_ERR) {
 154                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 155                         irqst_spcr1);
 156                 /* Writing zero to RSYNC_ERR clears the IRQ */
 157                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 158         } else {
 159                 complete(&mcbsp_rx->tx_irq_completion);
 160         }
 161
 162         return IRQ_HANDLED;
 163 }
 164
 165 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 166 {
 167         struct omap_mcbsp *mcbsp_dma_tx = data;
 168
 169         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 170                 MCBSP_READ(mcbsp_dma_tx, SPCR2));
 171
 172         /* We can free the channels */
 173         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 174         mcbsp_dma_tx->dma_tx_lch = -1;
 175
 176         complete(&mcbsp_dma_tx->tx_dma_completion);
 177 }
 178
 179 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 180 {
 181         struct omap_mcbsp *mcbsp_dma_rx = data;
 182
 183         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 184                 MCBSP_READ(mcbsp_dma_rx, SPCR2));
 185
 186         /* We can free the channels */
 187         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 188         mcbsp_dma_rx->dma_rx_lch = -1;
 189
 190         complete(&mcbsp_dma_rx->rx_dma_completion);
 191 }
 192
 193 /*
 194  * omap_mcbsp_config simply write a config to the
 195  * appropriate McBSP.
 196  * You either call this function or set the McBSP registers
 197  * by yourself before calling omap_mcbsp_start().
 198  */
 199 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 200 {
 201         struct omap_mcbsp *mcbsp;
 202
 203         if (!omap_mcbsp_check_valid_id(id)) {
 204                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 205                 return;
 206         }
 207         mcbsp = id_to_mcbsp_ptr(id);
 208
 209         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 210                         mcbsp->id, mcbsp->phys_base);
 211
 212         /* We write the given config */
 213         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 214         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 215         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 216         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 217         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 218         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 219         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 220         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 221         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 222         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 223         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 224         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 225                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 226                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 227         }
 228 }
 229 EXPORT_SYMBOL(omap_mcbsp_config);
 230
 231 #ifdef CONFIG_ARCH_OMAP3
 232 static void omap_st_on(struct omap_mcbsp *mcbsp)
 233 {
 234         unsigned int w;
 235
 236         /*
 237          * Sidetone uses McBSP ICLK - which must not idle when sidetones
 238          * are enabled or sidetones start sounding ugly.
 239          */
 240         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 241         w &= ~(1 << (mcbsp->id - 2));
 242         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 243
 244         /* Enable McBSP Sidetone */
 245         w = MCBSP_READ(mcbsp, SSELCR);
 246         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 247
 248         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 249         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 250
 251         /* Enable Sidetone from Sidetone Core */
 252         w = MCBSP_ST_READ(mcbsp, SSELCR);
 253         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 254 }
 255
 256 static void omap_st_off(struct omap_mcbsp *mcbsp)
 257 {
 258         unsigned int w;
 259
 260         w = MCBSP_ST_READ(mcbsp, SSELCR);
 261         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 262
 263         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 264         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
 265
 266         w = MCBSP_READ(mcbsp, SSELCR);
 267         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 268
 269         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 270         w |= 1 << (mcbsp->id - 2);
 271         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 272 }
 273
 274 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 275 {
 276         u16 val, i;
 277
 278         val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 279         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
 280
 281         val = MCBSP_ST_READ(mcbsp, SSELCR);
 282
 283         if (val & ST_COEFFWREN)
 284                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 285
 286         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 287
 288         for (i = 0; i < 128; i++)
 289                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 290
 291         i = 0;
 292
 293         val = MCBSP_ST_READ(mcbsp, SSELCR);
 294         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 295                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 296
 297         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 298
 299         if (i == 1000)
 300                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 301 }
 302
 303 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 304 {
 305         u16 w;
 306         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 307
 308         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 309         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 310
 311         w = MCBSP_ST_READ(mcbsp, SSELCR);
 312
 313         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 314                       ST_CH1GAIN(st_data->ch1gain));
 315 }
 316
 317 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
 318 {
 319         struct omap_mcbsp *mcbsp;
 320         struct omap_mcbsp_st_data *st_data;
 321         int ret = 0;
 322
 323         if (!omap_mcbsp_check_valid_id(id)) {
 324                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 325                 return -ENODEV;
 326         }
 327
 328         mcbsp = id_to_mcbsp_ptr(id);
 329         st_data = mcbsp->st_data;
 330
 331         if (!st_data)
 332                 return -ENOENT;
 333
 334         spin_lock_irq(&mcbsp->lock);
 335         if (channel == 0)
 336                 st_data->ch0gain = chgain;
 337         else if (channel == 1)
 338                 st_data->ch1gain = chgain;
 339         else
 340                 ret = -EINVAL;
 341
 342         if (st_data->enabled)
 343                 omap_st_chgain(mcbsp);
 344         spin_unlock_irq(&mcbsp->lock);
 345
 346         return ret;
 347 }
 348 EXPORT_SYMBOL(omap_st_set_chgain);
 349
 350 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
 351 {
 352         struct omap_mcbsp *mcbsp;
 353         struct omap_mcbsp_st_data *st_data;
 354         int ret = 0;
 355
 356         if (!omap_mcbsp_check_valid_id(id)) {
 357                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 358                 return -ENODEV;
 359         }
 360
 361         mcbsp = id_to_mcbsp_ptr(id);
 362         st_data = mcbsp->st_data;
 363
 364         if (!st_data)
 365                 return -ENOENT;
 366
 367         spin_lock_irq(&mcbsp->lock);
 368         if (channel == 0)
 369                 *chgain = st_data->ch0gain;
 370         else if (channel == 1)
 371                 *chgain = st_data->ch1gain;
 372         else
 373                 ret = -EINVAL;
 374         spin_unlock_irq(&mcbsp->lock);
 375
 376         return ret;
 377 }
 378 EXPORT_SYMBOL(omap_st_get_chgain);
 379
 380 static int omap_st_start(struct omap_mcbsp *mcbsp)
 381 {
 382         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 383
 384         if (st_data && st_data->enabled && !st_data->running) {
 385                 omap_st_fir_write(mcbsp, st_data->taps);
 386                 omap_st_chgain(mcbsp);
 387
 388                 if (!mcbsp->free) {
 389                         omap_st_on(mcbsp);
 390                         st_data->running = 1;
 391                 }
 392         }
 393
 394         return 0;
 395 }
 396
 397 int omap_st_enable(unsigned int id)
 398 {
 399         struct omap_mcbsp *mcbsp;
 400         struct omap_mcbsp_st_data *st_data;
 401
 402         if (!omap_mcbsp_check_valid_id(id)) {
 403                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 404                 return -ENODEV;
 405         }
 406
 407         mcbsp = id_to_mcbsp_ptr(id);
 408         st_data = mcbsp->st_data;
 409
 410         if (!st_data)
 411                 return -ENODEV;
 412
 413         spin_lock_irq(&mcbsp->lock);
 414         st_data->enabled = 1;
 415         omap_st_start(mcbsp);
 416         spin_unlock_irq(&mcbsp->lock);
 417
 418         return 0;
 419 }
 420 EXPORT_SYMBOL(omap_st_enable);
 421
 422 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 423 {
 424         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 425
 426         if (st_data && st_data->running) {
 427                 if (!mcbsp->free) {
 428                         omap_st_off(mcbsp);
 429                         st_data->running = 0;
 430                 }
 431         }
 432
 433         return 0;
 434 }
 435
 436 int omap_st_disable(unsigned int id)
 437 {
 438         struct omap_mcbsp *mcbsp;
 439         struct omap_mcbsp_st_data *st_data;
 440         int ret = 0;
 441
 442         if (!omap_mcbsp_check_valid_id(id)) {
 443                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 444                 return -ENODEV;
 445         }
 446
 447         mcbsp = id_to_mcbsp_ptr(id);
 448         st_data = mcbsp->st_data;
 449
 450         if (!st_data)
 451                 return -ENODEV;
 452
 453         spin_lock_irq(&mcbsp->lock);
 454         omap_st_stop(mcbsp);
 455         st_data->enabled = 0;
 456         spin_unlock_irq(&mcbsp->lock);
 457
 458         return ret;
 459 }
 460 EXPORT_SYMBOL(omap_st_disable);
 461
 462 int omap_st_is_enabled(unsigned int id)
 463 {
 464         struct omap_mcbsp *mcbsp;
 465         struct omap_mcbsp_st_data *st_data;
 466
 467         if (!omap_mcbsp_check_valid_id(id)) {
 468                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 469                 return -ENODEV;
 470         }
 471
 472         mcbsp = id_to_mcbsp_ptr(id);
 473         st_data = mcbsp->st_data;
 474
 475         if (!st_data)
 476                 return -ENODEV;
 477
 478
 479         return st_data->enabled;
 480 }
 481 EXPORT_SYMBOL(omap_st_is_enabled);
 482
 483 /*
 484  * omap_mcbsp_set_tx_threshold configures how to deal
 485  * with transmit threshold. the threshold value and handler can be
 486  * configure in here.
 487  */
 488 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 489 {
 490         struct omap_mcbsp *mcbsp;
 491
 492         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 493                 return;
 494
 495         if (!omap_mcbsp_check_valid_id(id)) {
 496                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 497                 return;
 498         }
 499         mcbsp = id_to_mcbsp_ptr(id);
 500
 501         MCBSP_WRITE(mcbsp, THRSH2, threshold);
 502 }
 503 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 504
 505 /*
 506  * omap_mcbsp_set_rx_threshold configures how to deal
 507  * with receive threshold. the threshold value and handler can be
 508  * configure in here.
 509  */
 510 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 511 {
 512         struct omap_mcbsp *mcbsp;
 513
 514         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 515                 return;
 516
 517         if (!omap_mcbsp_check_valid_id(id)) {
 518                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 519                 return;
 520         }
 521         mcbsp = id_to_mcbsp_ptr(id);
 522
 523         MCBSP_WRITE(mcbsp, THRSH1, threshold);
 524 }
 525 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 526
 527 /*
 528  * omap_mcbsp_get_max_tx_thres just return the current configured
 529  * maximum threshold for transmission
 530  */
 531 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 532 {
 533         struct omap_mcbsp *mcbsp;
 534
 535         if (!omap_mcbsp_check_valid_id(id)) {
 536                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 537                 return -ENODEV;
 538         }
 539         mcbsp = id_to_mcbsp_ptr(id);
 540
 541         return mcbsp->max_tx_thres;
 542 }
 543 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 544
 545 /*
 546  * omap_mcbsp_get_max_rx_thres just return the current configured
 547  * maximum threshold for reception
 548  */
 549 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 550 {
 551         struct omap_mcbsp *mcbsp;
 552
 553         if (!omap_mcbsp_check_valid_id(id)) {
 554                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 555                 return -ENODEV;
 556         }
 557         mcbsp = id_to_mcbsp_ptr(id);
 558
 559         return mcbsp->max_rx_thres;
 560 }
 561 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 562
 563 u16 omap_mcbsp_get_fifo_size(unsigned int id)
 564 {
 565         struct omap_mcbsp *mcbsp;
 566
 567         if (!omap_mcbsp_check_valid_id(id)) {
 568                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 569                 return -ENODEV;
 570         }
 571         mcbsp = id_to_mcbsp_ptr(id);
 572
 573         return mcbsp->pdata->buffer_size;
 574 }
 575 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
 576
 577 #define MCBSP2_FIFO_SIZE        0x500 /* 1024 + 256 locations */
 578 #define MCBSP1345_FIFO_SIZE     0x80  /* 128 locations */
 579 /*
 580  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 581  */
 582 u16 omap_mcbsp_get_tx_delay(unsigned int id)
 583 {
 584         struct omap_mcbsp *mcbsp;
 585         u16 buffstat;
 586
 587         if (!omap_mcbsp_check_valid_id(id)) {
 588                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 589                 return -ENODEV;
 590         }
 591         mcbsp = id_to_mcbsp_ptr(id);
 592
 593         /* Returns the number of free locations in the buffer */
 594         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 595
 596         /* Number of slots are different in McBSP ports */
 597         if (mcbsp->id == 2)
 598                 return MCBSP2_FIFO_SIZE - buffstat;
 599         else
 600                 return MCBSP1345_FIFO_SIZE - buffstat;
 601 }
 602 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
 603
 604 /*
 605  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 606  * to reach the threshold value (when the DMA will be triggered to read it)
 607  */
 608 u16 omap_mcbsp_get_rx_delay(unsigned int id)
 609 {
 610         struct omap_mcbsp *mcbsp;
 611         u16 buffstat, threshold;
 612
 613         if (!omap_mcbsp_check_valid_id(id)) {
 614                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 615                 return -ENODEV;
 616         }
 617         mcbsp = id_to_mcbsp_ptr(id);
 618
 619         /* Returns the number of used locations in the buffer */
 620         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 621         /* RX threshold */
 622         threshold = MCBSP_READ(mcbsp, THRSH1);
 623
 624         /* Return the number of location till we reach the threshold limit */
 625         if (threshold <= buffstat)
 626                 return 0;
 627         else
 628                 return threshold - buffstat;
 629 }
 630 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
 631
 632 /*
 633  * omap_mcbsp_get_dma_op_mode just return the current configured
 634  * operating mode for the mcbsp channel
 635  */
 636 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 637 {
 638         struct omap_mcbsp *mcbsp;
 639         int dma_op_mode;
 640
 641         if (!omap_mcbsp_check_valid_id(id)) {
 642                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 643                 return -ENODEV;
 644         }
 645         mcbsp = id_to_mcbsp_ptr(id);
 646
 647         dma_op_mode = mcbsp->dma_op_mode;
 648
 649         return dma_op_mode;
 650 }
 651 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 652
 653 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 654 {
 655         /*
 656          * Enable wakup behavior, smart idle and all wakeups
 657          * REVISIT: some wakeups may be unnecessary
 658          */
 659         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 660                 u16 syscon;
 661
 662                 syscon = MCBSP_READ(mcbsp, SYSCON);
 663                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 664
 665                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 666                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 667                                         CLOCKACTIVITY(0x02));
 668                         MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 669                 } else {
 670                         syscon |= SIDLEMODE(0x01);
 671                 }
 672
 673                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 674         }
 675 }
 676
 677 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 678 {
 679         /*
 680          * Disable wakup behavior, smart idle and all wakeups
 681          */
 682         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 683                 u16 syscon;
 684
 685                 syscon = MCBSP_READ(mcbsp, SYSCON);
 686                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 687                 /*
 688                  * HW bug workaround - If no_idle mode is taken, we need to
 689                  * go to smart_idle before going to always_idle, or the
 690                  * device will not hit retention anymore.
 691                  */
 692                 syscon |= SIDLEMODE(0x02);
 693                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 694
 695                 syscon &= ~(SIDLEMODE(0x03));
 696                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 697
 698                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 699         }
 700 }
 701 #else
 702 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 703 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 704 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 705 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 706 #endif
 707
 708 /*
 709  * We can choose between IRQ based or polled IO.
 710  * This needs to be called before omap_mcbsp_request().
 711  */
 712 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 713 {
 714         struct omap_mcbsp *mcbsp;
 715
 716         if (!omap_mcbsp_check_valid_id(id)) {
 717                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 718                 return -ENODEV;
 719         }
 720         mcbsp = id_to_mcbsp_ptr(id);
 721
 722         spin_lock(&mcbsp->lock);
 723
 724         if (!mcbsp->free) {
 725                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 726                         mcbsp->id);
 727                 spin_unlock(&mcbsp->lock);
 728                 return -EINVAL;
 729         }
 730
 731         mcbsp->io_type = io_type;
 732
 733         spin_unlock(&mcbsp->lock);
 734
 735         return 0;
 736 }
 737 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 738
 739 int omap_mcbsp_request(unsigned int id)
 740 {
 741         struct omap_mcbsp *mcbsp;
 742         void *reg_cache;
 743         int err;
 744
 745         if (!omap_mcbsp_check_valid_id(id)) {
 746                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 747                 return -ENODEV;
 748         }
 749         mcbsp = id_to_mcbsp_ptr(id);
 750
 751         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
 752         if (!reg_cache) {
 753                 return -ENOMEM;
 754         }
 755
 756         spin_lock(&mcbsp->lock);
 757         if (!mcbsp->free) {
 758                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 759                         mcbsp->id);
 760                 err = -EBUSY;
 761                 goto err_kfree;
 762         }
 763
 764         mcbsp->free = 0;
 765         mcbsp->reg_cache = reg_cache;
 766         spin_unlock(&mcbsp->lock);
 767
 768         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 769                 mcbsp->pdata->ops->request(id);
 770
 771         clk_enable(mcbsp->iclk);
 772         clk_enable(mcbsp->fclk);
 773
 774         /* Do procedure specific to omap34xx arch, if applicable */
 775         omap34xx_mcbsp_request(mcbsp);
 776
 777         /*
 778          * Make sure that transmitter, receiver and sample-rate generator are
 779          * not running before activating IRQs.
 780          */
 781         MCBSP_WRITE(mcbsp, SPCR1, 0);
 782         MCBSP_WRITE(mcbsp, SPCR2, 0);
 783
 784         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 785                 /* We need to get IRQs here */
 786                 init_completion(&mcbsp->tx_irq_completion);
 787                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 788                                         0, "McBSP", (void *)mcbsp);
 789                 if (err != 0) {
 790                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 791                                         "for McBSP%d\n", mcbsp->tx_irq,
 792                                         mcbsp->id);
 793                         goto err_clk_disable;
 794                 }
 795
 796                 if (mcbsp->rx_irq) {
 797                         init_completion(&mcbsp->rx_irq_completion);
 798                         err = request_irq(mcbsp->rx_irq,
 799                                         omap_mcbsp_rx_irq_handler,
 800                                         0, "McBSP", (void *)mcbsp);
 801                         if (err != 0) {
 802                                 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 803                                                 "for McBSP%d\n", mcbsp->rx_irq,
 804                                                 mcbsp->id);
 805                                 goto err_free_irq;
 806                         }
 807                 }
 808         }
 809
 810         return 0;
 811 err_free_irq:
 812         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 813 err_clk_disable:
 814         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 815                 mcbsp->pdata->ops->free(id);
 816
 817         /* Do procedure specific to omap34xx arch, if applicable */
 818         omap34xx_mcbsp_free(mcbsp);
 819
 820         clk_disable(mcbsp->fclk);
 821         clk_disable(mcbsp->iclk);
 822
 823         spin_lock(&mcbsp->lock);
 824         mcbsp->free = 1;
 825         mcbsp->reg_cache = NULL;
 826 err_kfree:
 827         spin_unlock(&mcbsp->lock);
 828         kfree(reg_cache);
 829
 830         return err;
 831 }
 832 EXPORT_SYMBOL(omap_mcbsp_request);
 833
 834 void omap_mcbsp_free(unsigned int id)
 835 {
 836         struct omap_mcbsp *mcbsp;
 837         void *reg_cache;
 838
 839         if (!omap_mcbsp_check_valid_id(id)) {
 840                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 841                 return;
 842         }
 843         mcbsp = id_to_mcbsp_ptr(id);
 844
 845         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 846                 mcbsp->pdata->ops->free(id);
 847
 848         /* Do procedure specific to omap34xx arch, if applicable */
 849         omap34xx_mcbsp_free(mcbsp);
 850
 851         clk_disable(mcbsp->fclk);
 852         clk_disable(mcbsp->iclk);
 853
 854         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 855                 /* Free IRQs */
 856                 if (mcbsp->rx_irq)
 857                         free_irq(mcbsp->rx_irq, (void *)mcbsp);
 858                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 859         }
 860
 861         reg_cache = mcbsp->reg_cache;
 862
 863         spin_lock(&mcbsp->lock);
 864         if (mcbsp->free)
 865                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 866         else
 867                 mcbsp->free = 1;
 868         mcbsp->reg_cache = NULL;
 869         spin_unlock(&mcbsp->lock);
 870
 871         if (reg_cache)
 872                 kfree(reg_cache);
 873 }
 874 EXPORT_SYMBOL(omap_mcbsp_free);
 875
 876 /*
 877  * Here we start the McBSP, by enabling transmitter, receiver or both.
 878  * If no transmitter or receiver is active prior calling, then sample-rate
 879  * generator and frame sync are started.
 880  */
 881 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 882 {
 883         struct omap_mcbsp *mcbsp;
 884         int idle;
 885         u16 w;
 886
 887         if (!omap_mcbsp_check_valid_id(id)) {
 888                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 889                 return;
 890         }
 891         mcbsp = id_to_mcbsp_ptr(id);
 892
 893         if (cpu_is_omap34xx())
 894                 omap_st_start(mcbsp);
 895
 896         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
 897         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 898
 899         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 900                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 901
 902         if (idle) {
 903                 /* Start the sample generator */
 904                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 905                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 906         }
 907
 908         /* Enable transmitter and receiver */
 909         tx &= 1;
 910         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 911         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 912
 913         rx &= 1;
 914         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 915         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 916
 917         /*
 918          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 919          * REVISIT: 100us may give enough time for two CLKSRG, however
 920          * due to some unknown PM related, clock gating etc. reason it
 921          * is now at 500us.
 922          */
 923         udelay(500);
 924
 925         if (idle) {
 926                 /* Start frame sync */
 927                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 928                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 929         }
 930
 931         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 932                 /* Release the transmitter and receiver */
 933                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 934                 w &= ~(tx ? XDISABLE : 0);
 935                 MCBSP_WRITE(mcbsp, XCCR, w);
 936                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 937                 w &= ~(rx ? RDISABLE : 0);
 938                 MCBSP_WRITE(mcbsp, RCCR, w);
 939         }
 940
 941         /* Dump McBSP Regs */
 942         omap_mcbsp_dump_reg(id);
 943 }
 944 EXPORT_SYMBOL(omap_mcbsp_start);
 945
 946 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 947 {
 948         struct omap_mcbsp *mcbsp;
 949         int idle;
 950         u16 w;
 951
 952         if (!omap_mcbsp_check_valid_id(id)) {
 953                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 954                 return;
 955         }
 956
 957         mcbsp = id_to_mcbsp_ptr(id);
 958
 959         /* Reset transmitter */
 960         tx &= 1;
 961         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 962                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 963                 w |= (tx ? XDISABLE : 0);
 964                 MCBSP_WRITE(mcbsp, XCCR, w);
 965         }
 966         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 967         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 968
 969         /* Reset receiver */
 970         rx &= 1;
 971         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 972                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 973                 w |= (rx ? RDISABLE : 0);
 974                 MCBSP_WRITE(mcbsp, RCCR, w);
 975         }
 976         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 977         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 978
 979         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 980                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 981
 982         if (idle) {
 983                 /* Reset the sample rate generator */
 984                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 985                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 986         }
 987
 988         if (cpu_is_omap34xx())
 989                 omap_st_stop(mcbsp);
 990 }
 991 EXPORT_SYMBOL(omap_mcbsp_stop);
 992
 993 /* polled mcbsp i/o operations */
 994 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 995 {
 996         struct omap_mcbsp *mcbsp;
 997
 998         if (!omap_mcbsp_check_valid_id(id)) {
 999                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1000                 return -ENODEV;
1001         }
1002
1003         mcbsp = id_to_mcbsp_ptr(id);
1004
1005         MCBSP_WRITE(mcbsp, DXR1, buf);
1006         /* if frame sync error - clear the error */
1007         if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1008                 /* clear error */
1009                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1010                 /* resend */
1011                 return -1;
1012         } else {
1013                 /* wait for transmit confirmation */
1014                 int attemps = 0;
1015                 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1016                         if (attemps++ > 1000) {
1017                                 MCBSP_WRITE(mcbsp, SPCR2,
1018                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1019                                                 (~XRST));
1020                                 udelay(10);
1021                                 MCBSP_WRITE(mcbsp, SPCR2,
1022                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1023                                                 (XRST));
1024                                 udelay(10);
1025                                 dev_err(mcbsp->dev, "Could not write to"
1026                                         " McBSP%d Register\n", mcbsp->id);
1027                                 return -2;
1028                         }
1029                 }
1030         }
1031
1032         return 0;
1033 }
1034 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1035
1036 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1037 {
1038         struct omap_mcbsp *mcbsp;
1039
1040         if (!omap_mcbsp_check_valid_id(id)) {
1041                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1042                 return -ENODEV;
1043         }
1044         mcbsp = id_to_mcbsp_ptr(id);
1045
1046         /* if frame sync error - clear the error */
1047         if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1048                 /* clear error */
1049                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1050                 /* resend */
1051                 return -1;
1052         } else {
1053                 /* wait for recieve confirmation */
1054                 int attemps = 0;
1055                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1056                         if (attemps++ > 1000) {
1057                                 MCBSP_WRITE(mcbsp, SPCR1,
1058                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1059                                                 (~RRST));
1060                                 udelay(10);
1061                                 MCBSP_WRITE(mcbsp, SPCR1,
1062                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1063                                                 (RRST));
1064                                 udelay(10);
1065                                 dev_err(mcbsp->dev, "Could not read from"
1066                                         " McBSP%d Register\n", mcbsp->id);
1067                                 return -2;
1068                         }
1069                 }
1070         }
1071         *buf = MCBSP_READ(mcbsp, DRR1);
1072
1073         return 0;
1074 }
1075 EXPORT_SYMBOL(omap_mcbsp_pollread);
1076
1077 /*
1078  * IRQ based word transmission.
1079  */
1080 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1081 {
1082         struct omap_mcbsp *mcbsp;
1083         omap_mcbsp_word_length word_length;
1084
1085         if (!omap_mcbsp_check_valid_id(id)) {
1086                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1087                 return;
1088         }
1089
1090         mcbsp = id_to_mcbsp_ptr(id);
1091         word_length = mcbsp->tx_word_length;
1092
1093         wait_for_completion(&mcbsp->tx_irq_completion);
1094
1095         if (word_length > OMAP_MCBSP_WORD_16)
1096                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1097         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1098 }
1099 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1100
1101 u32 omap_mcbsp_recv_word(unsigned int id)
1102 {
1103         struct omap_mcbsp *mcbsp;
1104         u16 word_lsb, word_msb = 0;
1105         omap_mcbsp_word_length word_length;
1106
1107         if (!omap_mcbsp_check_valid_id(id)) {
1108                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1109                 return -ENODEV;
1110         }
1111         mcbsp = id_to_mcbsp_ptr(id);
1112
1113         word_length = mcbsp->rx_word_length;
1114
1115         wait_for_completion(&mcbsp->rx_irq_completion);
1116
1117         if (word_length > OMAP_MCBSP_WORD_16)
1118                 word_msb = MCBSP_READ(mcbsp, DRR2);
1119         word_lsb = MCBSP_READ(mcbsp, DRR1);
1120
1121         return (word_lsb | (word_msb << 16));
1122 }
1123 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1124
1125 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1126 {
1127         struct omap_mcbsp *mcbsp;
1128         omap_mcbsp_word_length tx_word_length;
1129         omap_mcbsp_word_length rx_word_length;
1130         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1131
1132         if (!omap_mcbsp_check_valid_id(id)) {
1133                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1134                 return -ENODEV;
1135         }
1136         mcbsp = id_to_mcbsp_ptr(id);
1137         tx_word_length = mcbsp->tx_word_length;
1138         rx_word_length = mcbsp->rx_word_length;
1139
1140         if (tx_word_length != rx_word_length)
1141                 return -EINVAL;
1142
1143         /* First we wait for the transmitter to be ready */
1144         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1145         while (!(spcr2 & XRDY)) {
1146                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1147                 if (attempts++ > 1000) {
1148                         /* We must reset the transmitter */
1149                         MCBSP_WRITE(mcbsp, SPCR2,
1150                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1151                         udelay(10);
1152                         MCBSP_WRITE(mcbsp, SPCR2,
1153                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1154                         udelay(10);
1155                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1156                                 "ready\n", mcbsp->id);
1157                         return -EAGAIN;
1158                 }
1159         }
1160
1161         /* Now we can push the data */
1162         if (tx_word_length > OMAP_MCBSP_WORD_16)
1163                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1164         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1165
1166         /* We wait for the receiver to be ready */
1167         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1168         while (!(spcr1 & RRDY)) {
1169                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1170                 if (attempts++ > 1000) {
1171                         /* We must reset the receiver */
1172                         MCBSP_WRITE(mcbsp, SPCR1,
1173                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1174                         udelay(10);
1175                         MCBSP_WRITE(mcbsp, SPCR1,
1176                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1177                         udelay(10);
1178                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1179                                 "ready\n", mcbsp->id);
1180                         return -EAGAIN;
1181                 }
1182         }
1183
1184         /* Receiver is ready, let's read the dummy data */
1185         if (rx_word_length > OMAP_MCBSP_WORD_16)
1186                 word_msb = MCBSP_READ(mcbsp, DRR2);
1187         word_lsb = MCBSP_READ(mcbsp, DRR1);
1188
1189         return 0;
1190 }
1191 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1192
1193 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1194 {
1195         struct omap_mcbsp *mcbsp;
1196         u32 clock_word = 0;
1197         omap_mcbsp_word_length tx_word_length;
1198         omap_mcbsp_word_length rx_word_length;
1199         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1200
1201         if (!omap_mcbsp_check_valid_id(id)) {
1202                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1203                 return -ENODEV;
1204         }
1205
1206         mcbsp = id_to_mcbsp_ptr(id);
1207
1208         tx_word_length = mcbsp->tx_word_length;
1209         rx_word_length = mcbsp->rx_word_length;
1210
1211         if (tx_word_length != rx_word_length)
1212                 return -EINVAL;
1213
1214         /* First we wait for the transmitter to be ready */
1215         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1216         while (!(spcr2 & XRDY)) {
1217                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1218                 if (attempts++ > 1000) {
1219                         /* We must reset the transmitter */
1220                         MCBSP_WRITE(mcbsp, SPCR2,
1221                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1222                         udelay(10);
1223                         MCBSP_WRITE(mcbsp, SPCR2,
1224                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1225                         udelay(10);
1226                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1227                                 "ready\n", mcbsp->id);
1228                         return -EAGAIN;
1229                 }
1230         }
1231
1232         /* We first need to enable the bus clock */
1233         if (tx_word_length > OMAP_MCBSP_WORD_16)
1234                 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1235         MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1236
1237         /* We wait for the receiver to be ready */
1238         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1239         while (!(spcr1 & RRDY)) {
1240                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1241                 if (attempts++ > 1000) {
1242                         /* We must reset the receiver */
1243                         MCBSP_WRITE(mcbsp, SPCR1,
1244                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1245                         udelay(10);
1246                         MCBSP_WRITE(mcbsp, SPCR1,
1247                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1248                         udelay(10);
1249                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1250                                 "ready\n", mcbsp->id);
1251                         return -EAGAIN;
1252                 }
1253         }
1254
1255         /* Receiver is ready, there is something for us */
1256         if (rx_word_length > OMAP_MCBSP_WORD_16)
1257                 word_msb = MCBSP_READ(mcbsp, DRR2);
1258         word_lsb = MCBSP_READ(mcbsp, DRR1);
1259
1260         word[0] = (word_lsb | (word_msb << 16));
1261
1262         return 0;
1263 }
1264 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1265
1266 /*
1267  * Simple DMA based buffer rx/tx routines.
1268  * Nothing fancy, just a single buffer tx/rx through DMA.
1269  * The DMA resources are released once the transfer is done.
1270  * For anything fancier, you should use your own customized DMA
1271  * routines and callbacks.
1272  */
1273 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1274                                 unsigned int length)
1275 {
1276         struct omap_mcbsp *mcbsp;
1277         int dma_tx_ch;
1278         int src_port = 0;
1279         int dest_port = 0;
1280         int sync_dev = 0;
1281
1282         if (!omap_mcbsp_check_valid_id(id)) {
1283                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1284                 return -ENODEV;
1285         }
1286         mcbsp = id_to_mcbsp_ptr(id);
1287
1288         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1289                                 omap_mcbsp_tx_dma_callback,
1290                                 mcbsp,
1291                                 &dma_tx_ch)) {
1292                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1293                                 "McBSP%d TX. Trying IRQ based TX\n",
1294                                 mcbsp->id);
1295                 return -EAGAIN;
1296         }
1297         mcbsp->dma_tx_lch = dma_tx_ch;
1298
1299         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1300                 dma_tx_ch);
1301
1302         init_completion(&mcbsp->tx_dma_completion);
1303
1304         if (cpu_class_is_omap1()) {
1305                 src_port = OMAP_DMA_PORT_TIPB;
1306                 dest_port = OMAP_DMA_PORT_EMIFF;
1307         }
1308         if (cpu_class_is_omap2())
1309                 sync_dev = mcbsp->dma_tx_sync;
1310
1311         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1312                                      OMAP_DMA_DATA_TYPE_S16,
1313                                      length >> 1, 1,
1314                                      OMAP_DMA_SYNC_ELEMENT,
1315          sync_dev, 0);
1316
1317         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1318                                  src_port,
1319                                  OMAP_DMA_AMODE_CONSTANT,
1320                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1321                                  0, 0);
1322
1323         omap_set_dma_src_params(mcbsp->dma_tx_lch,
1324                                 dest_port,
1325                                 OMAP_DMA_AMODE_POST_INC,
1326                                 buffer,
1327                                 0, 0);
1328
1329         omap_start_dma(mcbsp->dma_tx_lch);
1330         wait_for_completion(&mcbsp->tx_dma_completion);
1331
1332         return 0;
1333 }
1334 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1335
1336 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1337                                 unsigned int length)
1338 {
1339         struct omap_mcbsp *mcbsp;
1340         int dma_rx_ch;
1341         int src_port = 0;
1342         int dest_port = 0;
1343         int sync_dev = 0;
1344
1345         if (!omap_mcbsp_check_valid_id(id)) {
1346                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1347                 return -ENODEV;
1348         }
1349         mcbsp = id_to_mcbsp_ptr(id);
1350
1351         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1352                                 omap_mcbsp_rx_dma_callback,
1353                                 mcbsp,
1354                                 &dma_rx_ch)) {
1355                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1356                                 "McBSP%d RX. Trying IRQ based RX\n",
1357                                 mcbsp->id);
1358                 return -EAGAIN;
1359         }
1360         mcbsp->dma_rx_lch = dma_rx_ch;
1361
1362         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1363                 dma_rx_ch);
1364
1365         init_completion(&mcbsp->rx_dma_completion);
1366
1367         if (cpu_class_is_omap1()) {
1368                 src_port = OMAP_DMA_PORT_TIPB;
1369                 dest_port = OMAP_DMA_PORT_EMIFF;
1370         }
1371         if (cpu_class_is_omap2())
1372                 sync_dev = mcbsp->dma_rx_sync;
1373
1374         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1375                                         OMAP_DMA_DATA_TYPE_S16,
1376                                         length >> 1, 1,
1377                                         OMAP_DMA_SYNC_ELEMENT,
1378                                         sync_dev, 0);
1379
1380         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1381                                 src_port,
1382                                 OMAP_DMA_AMODE_CONSTANT,
1383                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1384                                 0, 0);
1385
1386         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1387                                         dest_port,
1388                                         OMAP_DMA_AMODE_POST_INC,
1389                                         buffer,
1390                                         0, 0);
1391
1392         omap_start_dma(mcbsp->dma_rx_lch);
1393         wait_for_completion(&mcbsp->rx_dma_completion);
1394
1395         return 0;
1396 }
1397 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1398
1399 /*
1400  * SPI wrapper.
1401  * Since SPI setup is much simpler than the generic McBSP one,
1402  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1403  * Once this is done, you can call omap_mcbsp_start().
1404  */
1405 void omap_mcbsp_set_spi_mode(unsigned int id,
1406                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1407 {
1408         struct omap_mcbsp *mcbsp;
1409         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1410
1411         if (!omap_mcbsp_check_valid_id(id)) {
1412                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1413                 return;
1414         }
1415         mcbsp = id_to_mcbsp_ptr(id);
1416
1417         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1418
1419         /* SPI has only one frame */
1420         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1421         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1422
1423         /* Clock stop mode */
1424         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1425                 mcbsp_cfg.spcr1 |= (1 << 12);
1426         else
1427                 mcbsp_cfg.spcr1 |= (3 << 11);
1428
1429         /* Set clock parities */
1430         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1431                 mcbsp_cfg.pcr0 |= CLKRP;
1432         else
1433                 mcbsp_cfg.pcr0 &= ~CLKRP;
1434
1435         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1436                 mcbsp_cfg.pcr0 &= ~CLKXP;
1437         else
1438                 mcbsp_cfg.pcr0 |= CLKXP;
1439
1440         /* Set SCLKME to 0 and CLKSM to 1 */
1441         mcbsp_cfg.pcr0 &= ~SCLKME;
1442         mcbsp_cfg.srgr2 |= CLKSM;
1443
1444         /* Set FSXP */
1445         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1446                 mcbsp_cfg.pcr0 &= ~FSXP;
1447         else
1448                 mcbsp_cfg.pcr0 |= FSXP;
1449
1450         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1451                 mcbsp_cfg.pcr0 |= CLKXM;
1452                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1453                 mcbsp_cfg.pcr0 |= FSXM;
1454                 mcbsp_cfg.srgr2 &= ~FSGM;
1455                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1456                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1457         } else {
1458                 mcbsp_cfg.pcr0 &= ~CLKXM;
1459                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1460                 mcbsp_cfg.pcr0 &= ~FSXM;
1461                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1462                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1463         }
1464
1465         mcbsp_cfg.xcr2 &= ~XPHASE;
1466         mcbsp_cfg.rcr2 &= ~RPHASE;
1467
1468         omap_mcbsp_config(id, &mcbsp_cfg);
1469 }
1470 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1471
1472 #ifdef CONFIG_ARCH_OMAP3
1473 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1474 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1475 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1476 static ssize_t prop##_show(struct device *dev,                          \
1477                         struct device_attribute *attr, char *buf)       \
1478 {                                                                       \
1479         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1480                                                                         \
1481         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1482 }                                                                       \
1483                                                                         \
1484 static ssize_t prop##_store(struct device *dev,                         \
1485                                 struct device_attribute *attr,          \
1486                                 const char *buf, size_t size)           \
1487 {                                                                       \
1488         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1489         unsigned long val;                                              \
1490         int status;                                                     \
1491                                                                         \
1492         status = strict_strtoul(buf, 0, &val);                          \
1493         if (status)                                                     \
1494                 return status;                                          \
1495                                                                         \
1496         if (!valid_threshold(mcbsp, val))                               \
1497                 return -EDOM;                                           \
1498                                                                         \
1499         mcbsp->prop = val;                                              \
1500         return size;                                                    \
1501 }                                                                       \
1502                                                                         \
1503 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1504
1505 THRESHOLD_PROP_BUILDER(max_tx_thres);
1506 THRESHOLD_PROP_BUILDER(max_rx_thres);
1507
1508 static const char *dma_op_modes[] = {
1509         "element", "threshold", "frame",
1510 };
1511
1512 static ssize_t dma_op_mode_show(struct device *dev,
1513                         struct device_attribute *attr, char *buf)
1514 {
1515         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1516         int dma_op_mode, i = 0;
1517         ssize_t len = 0;
1518         const char * const *s;
1519
1520         dma_op_mode = mcbsp->dma_op_mode;
1521
1522         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1523                 if (dma_op_mode == i)
1524                         len += sprintf(buf + len, "[%s] ", *s);
1525                 else
1526                         len += sprintf(buf + len, "%s ", *s);
1527         }
1528         len += sprintf(buf + len, "\n");
1529
1530         return len;
1531 }
1532
1533 static ssize_t dma_op_mode_store(struct device *dev,
1534                                 struct device_attribute *attr,
1535                                 const char *buf, size_t size)
1536 {
1537         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1538         const char * const *s;
1539         int i = 0;
1540
1541         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1542                 if (sysfs_streq(buf, *s))
1543                         break;
1544
1545         if (i == ARRAY_SIZE(dma_op_modes))
1546                 return -EINVAL;
1547
1548         spin_lock_irq(&mcbsp->lock);
1549         if (!mcbsp->free) {
1550                 size = -EBUSY;
1551                 goto unlock;
1552         }
1553         mcbsp->dma_op_mode = i;
1554
1555 unlock:
1556         spin_unlock_irq(&mcbsp->lock);
1557
1558         return size;
1559 }
1560
1561 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1562
1563 static ssize_t st_taps_show(struct device *dev,
1564                             struct device_attribute *attr, char *buf)
1565 {
1566         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1567         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1568         ssize_t status = 0;
1569         int i;
1570
1571         spin_lock_irq(&mcbsp->lock);
1572         for (i = 0; i < st_data->nr_taps; i++)
1573                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1574                                   st_data->taps[i]);
1575         if (i)
1576                 status += sprintf(&buf[status], "\n");
1577         spin_unlock_irq(&mcbsp->lock);
1578
1579         return status;
1580 }
1581
1582 static ssize_t st_taps_store(struct device *dev,
1583                              struct device_attribute *attr,
1584                              const char *buf, size_t size)
1585 {
1586         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1587         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1588         int val, tmp, status, i = 0;
1589
1590         spin_lock_irq(&mcbsp->lock);
1591         memset(st_data->taps, 0, sizeof(st_data->taps));
1592         st_data->nr_taps = 0;
1593
1594         do {
1595                 status = sscanf(buf, "%d%n", &val, &tmp);
1596                 if (status < 0 || status == 0) {
1597                         size = -EINVAL;
1598                         goto out;
1599                 }
1600                 if (val < -32768 || val > 32767) {
1601                         size = -EINVAL;
1602                         goto out;
1603                 }
1604                 st_data->taps[i++] = val;
1605                 buf += tmp;
1606                 if (*buf != ',')
1607                         break;
1608                 buf++;
1609         } while (1);
1610
1611         st_data->nr_taps = i;
1612
1613 out:
1614         spin_unlock_irq(&mcbsp->lock);
1615
1616         return size;
1617 }
1618
1619 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1620
1621 static const struct attribute *additional_attrs[] = {
1622         &dev_attr_max_tx_thres.attr,
1623         &dev_attr_max_rx_thres.attr,
1624         &dev_attr_dma_op_mode.attr,
1625         NULL,
1626 };
1627
1628 static const struct attribute_group additional_attr_group = {
1629         .attrs = (struct attribute **)additional_attrs,
1630 };
1631
1632 static inline int __devinit omap_additional_add(struct device *dev)
1633 {
1634         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1635 }
1636
1637 static inline void __devexit omap_additional_remove(struct device *dev)
1638 {
1639         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1640 }
1641
1642 static const struct attribute *sidetone_attrs[] = {
1643         &dev_attr_st_taps.attr,
1644         NULL,
1645 };
1646
1647 static const struct attribute_group sidetone_attr_group = {
1648         .attrs = (struct attribute **)sidetone_attrs,
1649 };
1650
1651 int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1652 {
1653         struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1654         struct omap_mcbsp_st_data *st_data;
1655         int err;
1656
1657         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1658         if (!st_data) {
1659                 err = -ENOMEM;
1660                 goto err1;
1661         }
1662
1663         st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1664         if (!st_data->io_base_st) {
1665                 err = -ENOMEM;
1666                 goto err2;
1667         }
1668
1669         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1670         if (err)
1671                 goto err3;
1672
1673         mcbsp->st_data = st_data;
1674         return 0;
1675
1676 err3:
1677         iounmap(st_data->io_base_st);
1678 err2:
1679         kfree(st_data);
1680 err1:
1681         return err;
1682
1683 }
1684
1685 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1686 {
1687         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1688
1689         if (st_data) {
1690                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1691                 iounmap(st_data->io_base_st);
1692                 kfree(st_data);
1693         }
1694 }
1695
1696 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1697 {
1698         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1699         if (cpu_is_omap34xx()) {
1700                 mcbsp->max_tx_thres = max_thres(mcbsp);
1701                 mcbsp->max_rx_thres = max_thres(mcbsp);
1702                 /*
1703                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1704                  * for mcbsp2 instances.
1705                  */
1706                 if (omap_additional_add(mcbsp->dev))
1707                         dev_warn(mcbsp->dev,
1708                                 "Unable to create additional controls\n");
1709
1710                 if (mcbsp->id == 2 || mcbsp->id == 3)
1711                         if (omap_st_add(mcbsp))
1712                                 dev_warn(mcbsp->dev,
1713                                  "Unable to create sidetone controls\n");
1714
1715         } else {
1716                 mcbsp->max_tx_thres = -EINVAL;
1717                 mcbsp->max_rx_thres = -EINVAL;
1718         }
1719 }
1720
1721 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1722 {
1723         if (cpu_is_omap34xx()) {
1724                 omap_additional_remove(mcbsp->dev);
1725
1726                 if (mcbsp->id == 2 || mcbsp->id == 3)
1727                         omap_st_remove(mcbsp);
1728         }
1729 }
1730 #else
1731 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1732 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1733 #endif /* CONFIG_ARCH_OMAP3 */
1734
1735 /*
1736  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1737  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1738  */
1739 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1740 {
1741         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1742         struct omap_mcbsp *mcbsp;
1743         int id = pdev->id - 1;
1744         int ret = 0;
1745
1746         if (!pdata) {
1747                 dev_err(&pdev->dev, "McBSP device initialized without"
1748                                 "platform data\n");
1749                 ret = -EINVAL;
1750                 goto exit;
1751         }
1752
1753         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1754
1755         if (id >= omap_mcbsp_count) {
1756                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1757                 ret = -EINVAL;
1758                 goto exit;
1759         }
1760
1761         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1762         if (!mcbsp) {
1763                 ret = -ENOMEM;
1764                 goto exit;
1765         }
1766
1767         spin_lock_init(&mcbsp->lock);
1768         mcbsp->id = id + 1;
1769         mcbsp->free = 1;
1770         mcbsp->dma_tx_lch = -1;
1771         mcbsp->dma_rx_lch = -1;
1772
1773         mcbsp->phys_base = pdata->phys_base;
1774         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1775         if (!mcbsp->io_base) {
1776                 ret = -ENOMEM;
1777                 goto err_ioremap;
1778         }
1779
1780         /* Default I/O is IRQ based */
1781         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1782         mcbsp->tx_irq = pdata->tx_irq;
1783         mcbsp->rx_irq = pdata->rx_irq;
1784         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1785         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1786
1787         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1788         if (IS_ERR(mcbsp->iclk)) {
1789                 ret = PTR_ERR(mcbsp->iclk);
1790                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1791                 goto err_iclk;
1792         }
1793
1794         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1795         if (IS_ERR(mcbsp->fclk)) {
1796                 ret = PTR_ERR(mcbsp->fclk);
1797                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1798                 goto err_fclk;
1799         }
1800
1801         mcbsp->pdata = pdata;
1802         mcbsp->dev = &pdev->dev;
1803         mcbsp_ptr[id] = mcbsp;
1804         platform_set_drvdata(pdev, mcbsp);
1805
1806         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1807         omap34xx_device_init(mcbsp);
1808
1809         return 0;
1810
1811 err_fclk:
1812         clk_put(mcbsp->iclk);
1813 err_iclk:
1814         iounmap(mcbsp->io_base);
1815 err_ioremap:
1816         kfree(mcbsp);
1817 exit:
1818         return ret;
1819 }
1820
1821 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1822 {
1823         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1824
1825         platform_set_drvdata(pdev, NULL);
1826         if (mcbsp) {
1827
1828                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1829                                 mcbsp->pdata->ops->free)
1830                         mcbsp->pdata->ops->free(mcbsp->id);
1831
1832                 omap34xx_device_exit(mcbsp);
1833
1834                 clk_disable(mcbsp->fclk);
1835                 clk_disable(mcbsp->iclk);
1836                 clk_put(mcbsp->fclk);
1837                 clk_put(mcbsp->iclk);
1838
1839                 iounmap(mcbsp->io_base);
1840
1841                 mcbsp->fclk = NULL;
1842                 mcbsp->iclk = NULL;
1843                 mcbsp->free = 0;
1844                 mcbsp->dev = NULL;
1845         }
1846
1847         return 0;
1848 }
1849
1850 static struct platform_driver omap_mcbsp_driver = {
1851         .probe          = omap_mcbsp_probe,
1852         .remove         = __devexit_p(omap_mcbsp_remove),
1853         .driver         = {
1854                 .name   = "omap-mcbsp",
1855         },
1856 };
1857
1858 int __init omap_mcbsp_init(void)
1859 {
1860         /* Register the McBSP driver */
1861         return platform_driver_register(&omap_mcbsp_driver);
1862 }