1 // include/asm-arm/mach-omap/usb.h
3 #ifndef __ASM_ARCH_OMAP_USB_H
4 #define __ASM_ARCH_OMAP_USB_H
6 #include <linux/usb/musb.h>
7 #include <plat/board.h>
9 #define OMAP3_HS_USB_PORTS 3
10 enum ehci_hcd_omap_mode {
11 EHCI_HCD_OMAP_MODE_UNKNOWN,
12 EHCI_HCD_OMAP_MODE_PHY,
13 EHCI_HCD_OMAP_MODE_TLL,
16 enum ohci_omap3_port_mode {
17 OMAP_OHCI_PORT_MODE_UNUSED,
18 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
19 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
20 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
21 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
22 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
23 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
24 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
25 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
26 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
27 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM,
30 struct ehci_hcd_omap_platform_data {
31 enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
34 /* have to be valid if phy_reset is true and portx is in phy mode */
35 int reset_gpio_port[OMAP3_HS_USB_PORTS];
38 struct ohci_hcd_omap_platform_data {
39 enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS];
41 /* Set this to true for ES2.x silicon */
42 unsigned es2_compatibility:1;
45 /*-------------------------------------------------------------------------*/
47 #define OMAP1_OTG_BASE 0xfffb0400
48 #define OMAP1_UDC_BASE 0xfffb4000
49 #define OMAP1_OHCI_BASE 0xfffba000
51 #define OMAP2_OHCI_BASE 0x4805e000
52 #define OMAP2_UDC_BASE 0x4805e200
53 #define OMAP2_OTG_BASE 0x4805e300
55 #ifdef CONFIG_ARCH_OMAP1
57 #define OTG_BASE OMAP1_OTG_BASE
58 #define UDC_BASE OMAP1_UDC_BASE
59 #define OMAP_OHCI_BASE OMAP1_OHCI_BASE
63 #define OTG_BASE OMAP2_OTG_BASE
64 #define UDC_BASE OMAP2_UDC_BASE
65 #define OMAP_OHCI_BASE OMAP2_OHCI_BASE
67 struct omap_musb_board_data {
74 enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
76 extern void usb_musb_init(struct omap_musb_board_data *board_data);
78 extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
80 extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
84 void omap_usb_init(struct omap_usb_config *pdata);
86 /*-------------------------------------------------------------------------*/
89 * OTG and transceiver registers, for OMAPs starting with ARM926
91 #define OTG_REV (OTG_BASE + 0x00)
92 #define OTG_SYSCON_1 (OTG_BASE + 0x04)
93 # define USB2_TRX_MODE(w) (((w)>>24)&0x07)
94 # define USB1_TRX_MODE(w) (((w)>>20)&0x07)
95 # define USB0_TRX_MODE(w) (((w)>>16)&0x07)
96 # define OTG_IDLE_EN (1 << 15)
97 # define HST_IDLE_EN (1 << 14)
98 # define DEV_IDLE_EN (1 << 13)
99 # define OTG_RESET_DONE (1 << 2)
100 # define OTG_SOFT_RESET (1 << 1)
101 #define OTG_SYSCON_2 (OTG_BASE + 0x08)
102 # define OTG_EN (1 << 31)
103 # define USBX_SYNCHRO (1 << 30)
104 # define OTG_MST16 (1 << 29)
105 # define SRP_GPDATA (1 << 28)
106 # define SRP_GPDVBUS (1 << 27)
107 # define SRP_GPUVBUS(w) (((w)>>24)&0x07)
108 # define A_WAIT_VRISE(w) (((w)>>20)&0x07)
109 # define B_ASE_BRST(w) (((w)>>16)&0x07)
110 # define SRP_DPW (1 << 14)
111 # define SRP_DATA (1 << 13)
112 # define SRP_VBUS (1 << 12)
113 # define OTG_PADEN (1 << 10)
114 # define HMC_PADEN (1 << 9)
115 # define UHOST_EN (1 << 8)
116 # define HMC_TLLSPEED (1 << 7)
117 # define HMC_TLLATTACH (1 << 6)
118 # define OTG_HMC(w) (((w)>>0)&0x3f)
119 #define OTG_CTRL (OTG_BASE + 0x0c)
120 # define OTG_USB2_EN (1 << 29)
121 # define OTG_USB2_DP (1 << 28)
122 # define OTG_USB2_DM (1 << 27)
123 # define OTG_USB1_EN (1 << 26)
124 # define OTG_USB1_DP (1 << 25)
125 # define OTG_USB1_DM (1 << 24)
126 # define OTG_USB0_EN (1 << 23)
127 # define OTG_USB0_DP (1 << 22)
128 # define OTG_USB0_DM (1 << 21)
129 # define OTG_ASESSVLD (1 << 20)
130 # define OTG_BSESSEND (1 << 19)
131 # define OTG_BSESSVLD (1 << 18)
132 # define OTG_VBUSVLD (1 << 17)
133 # define OTG_ID (1 << 16)
134 # define OTG_DRIVER_SEL (1 << 15)
135 # define OTG_A_SETB_HNPEN (1 << 12)
136 # define OTG_A_BUSREQ (1 << 11)
137 # define OTG_B_HNPEN (1 << 9)
138 # define OTG_B_BUSREQ (1 << 8)
139 # define OTG_BUSDROP (1 << 7)
140 # define OTG_PULLDOWN (1 << 5)
141 # define OTG_PULLUP (1 << 4)
142 # define OTG_DRV_VBUS (1 << 3)
143 # define OTG_PD_VBUS (1 << 2)
144 # define OTG_PU_VBUS (1 << 1)
145 # define OTG_PU_ID (1 << 0)
146 #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
147 # define DRIVER_SWITCH (1 << 15)
148 # define A_VBUS_ERR (1 << 13)
149 # define A_REQ_TMROUT (1 << 12)
150 # define A_SRP_DETECT (1 << 11)
151 # define B_HNP_FAIL (1 << 10)
152 # define B_SRP_TMROUT (1 << 9)
153 # define B_SRP_DONE (1 << 8)
154 # define B_SRP_STARTED (1 << 7)
155 # define OPRT_CHG (1 << 0)
156 #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
157 // same bits as in IRQ_EN
158 #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
159 # define OTGVPD (1 << 14)
160 # define OTGVPU (1 << 13)
161 # define OTGPUID (1 << 12)
162 # define USB2VDR (1 << 10)
163 # define USB2PDEN (1 << 9)
164 # define USB2PUEN (1 << 8)
165 # define USB1VDR (1 << 6)
166 # define USB1PDEN (1 << 5)
167 # define USB1PUEN (1 << 4)
168 # define USB0VDR (1 << 2)
169 # define USB0PDEN (1 << 1)
170 # define USB0PUEN (1 << 0)
171 #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
172 #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
174 /*-------------------------------------------------------------------------*/
177 #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
178 # define CONF_USB2_UNI_R (1 << 8)
179 # define CONF_USB1_UNI_R (1 << 7)
180 # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
181 # define CONF_USB0_ISOLATE_R (1 << 3)
182 # define CONF_USB_PWRDN_DM_R (1 << 2)
183 # define CONF_USB_PWRDN_DP_R (1 << 1)
186 # define USB_UNIDIR 0x0
187 # define USB_UNIDIR_TLL 0x1
188 # define USB_BIDIR 0x2
189 # define USB_BIDIR_TLL 0x3
190 # define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
191 # define USBT2TLL5PI (1 << 17)
192 # define USB0PUENACTLOI (1 << 16)
193 # define USBSTANDBYCTRL (1 << 15)
195 #endif /* __ASM_ARCH_OMAP_USB_H */