1 // include/asm-arm/mach-omap/usb.h
3 #ifndef __ASM_ARCH_OMAP_USB_H
4 #define __ASM_ARCH_OMAP_USB_H
7 #include <linux/platform_device.h>
8 #include <linux/usb/musb.h>
10 #define OMAP3_HS_USB_PORTS 3
12 enum usbhs_omap_port_mode {
13 OMAP_USBHS_PORT_MODE_UNUSED,
14 OMAP_EHCI_PORT_MODE_PHY,
15 OMAP_EHCI_PORT_MODE_TLL,
16 OMAP_EHCI_PORT_MODE_HSIC,
17 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
18 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
19 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
20 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
21 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
22 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
23 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
24 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
25 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
26 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
29 struct usbhs_omap_board_data {
30 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
32 /* have to be valid if phy_reset is true and portx is in phy mode */
33 int reset_gpio_port[OMAP3_HS_USB_PORTS];
35 /* Set this to true for ES2.x silicon */
36 unsigned es2_compatibility:1;
41 * Regulators for USB PHYs.
42 * Each PHY can have a separate regulator.
44 struct regulator *regulator[OMAP3_HS_USB_PORTS];
47 #ifdef CONFIG_ARCH_OMAP2PLUS
49 struct ehci_hcd_omap_platform_data {
50 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
51 int reset_gpio_port[OMAP3_HS_USB_PORTS];
52 struct regulator *regulator[OMAP3_HS_USB_PORTS];
56 struct ohci_hcd_omap_platform_data {
57 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
58 unsigned es2_compatibility:1;
61 struct usbhs_omap_platform_data {
62 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
64 struct ehci_hcd_omap_platform_data *ehci_data;
65 struct ohci_hcd_omap_platform_data *ohci_data;
68 struct usbtll_omap_platform_data {
69 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
71 /*-------------------------------------------------------------------------*/
73 struct omap_musb_board_data {
78 void (*set_phy_power)(u8 on);
79 void (*clear_irq)(void);
80 void (*set_mode)(u8 mode);
84 enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
86 extern void usb_musb_init(struct omap_musb_board_data *board_data);
88 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
89 extern int omap_tll_enable(void);
90 extern int omap_tll_disable(void);
92 extern int omap4430_phy_power(struct device *dev, int ID, int on);
93 extern int omap4430_phy_set_clk(struct device *dev, int on);
94 extern int omap4430_phy_init(struct device *dev);
95 extern int omap4430_phy_exit(struct device *dev);
96 extern int omap4430_phy_suspend(struct device *dev, int suspend);
100 extern void am35x_musb_reset(void);
101 extern void am35x_musb_phy_power(u8 on);
102 extern void am35x_musb_clear_irq(void);
103 extern void am35x_set_mode(u8 musb_mode);
104 extern void ti81xx_musb_phy_power(u8 on);
107 /* USB 2.0 PHY Control */
108 #define CONF2_PHY_GPIOMODE (1 << 23)
109 #define CONF2_OTGMODE (3 << 14)
110 #define CONF2_NO_OVERRIDE (0 << 14)
111 #define CONF2_FORCE_HOST (1 << 14)
112 #define CONF2_FORCE_DEVICE (2 << 14)
113 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
114 #define CONF2_SESENDEN (1 << 13)
115 #define CONF2_VBDTCTEN (1 << 12)
116 #define CONF2_REFFREQ_24MHZ (2 << 8)
117 #define CONF2_REFFREQ_26MHZ (7 << 8)
118 #define CONF2_REFFREQ_13MHZ (6 << 8)
119 #define CONF2_REFFREQ (0xf << 8)
120 #define CONF2_PHYCLKGD (1 << 7)
121 #define CONF2_VBUSSENSE (1 << 6)
122 #define CONF2_PHY_PLLON (1 << 5)
123 #define CONF2_RESET (1 << 4)
124 #define CONF2_PHYPWRDN (1 << 3)
125 #define CONF2_OTGPWRDN (1 << 2)
126 #define CONF2_DATPOL (1 << 1)
128 /* TI81XX specific definitions */
129 #define USBCTRL0 0x620
130 #define USBSTAT0 0x624
132 /* TI816X PHY controls bits */
133 #define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
134 #define TI816X_USBPHY_REFCLK_OSC (1 << 8)
136 /* TI814X PHY controls bits */
137 #define USBPHY_CM_PWRDN (1 << 0)
138 #define USBPHY_OTG_PWRDN (1 << 1)
139 #define USBPHY_CHGDET_DIS (1 << 2)
140 #define USBPHY_CHGDET_RSTRT (1 << 3)
141 #define USBPHY_SRCONDM (1 << 4)
142 #define USBPHY_SINKONDP (1 << 5)
143 #define USBPHY_CHGISINK_EN (1 << 6)
144 #define USBPHY_CHGVSRC_EN (1 << 7)
145 #define USBPHY_DMPULLUP (1 << 8)
146 #define USBPHY_DPPULLUP (1 << 9)
147 #define USBPHY_CDET_EXTCTL (1 << 10)
148 #define USBPHY_GPIO_MODE (1 << 12)
149 #define USBPHY_DPOPBUFCTL (1 << 13)
150 #define USBPHY_DMOPBUFCTL (1 << 14)
151 #define USBPHY_DPINPUT (1 << 15)
152 #define USBPHY_DMINPUT (1 << 16)
153 #define USBPHY_DPGPIO_PD (1 << 17)
154 #define USBPHY_DMGPIO_PD (1 << 18)
155 #define USBPHY_OTGVDET_EN (1 << 19)
156 #define USBPHY_OTGSESSEND_EN (1 << 20)
157 #define USBPHY_DATA_POLARITY (1 << 23)
159 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
160 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
161 u32 omap1_usb1_init(unsigned nwires);
162 u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
164 static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
168 static inline u32 omap1_usb1_init(unsigned nwires)
173 static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
179 #endif /* __ASM_ARCH_OMAP_USB_H */