2 * arch/arm/plat-omap/include/mach/mcbsp.h
4 * Defines for Multi-Channel Buffered Serial Port
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
25 #define __ASM_ARCH_OMAP_MCBSP_H
27 #include <linux/completion.h>
28 #include <linux/spinlock.h>
30 #include <mach/hardware.h>
31 #include <plat/clock.h>
33 #define OMAP7XX_MCBSP1_BASE 0xfffb1000
34 #define OMAP7XX_MCBSP2_BASE 0xfffb1800
36 #define OMAP1510_MCBSP1_BASE 0xe1011800
37 #define OMAP1510_MCBSP2_BASE 0xfffb1000
38 #define OMAP1510_MCBSP3_BASE 0xe1017000
40 #define OMAP1610_MCBSP1_BASE 0xe1011800
41 #define OMAP1610_MCBSP2_BASE 0xfffb1000
42 #define OMAP1610_MCBSP3_BASE 0xe1017000
44 #define OMAP24XX_MCBSP1_BASE 0x48074000
45 #define OMAP24XX_MCBSP2_BASE 0x48076000
46 #define OMAP2430_MCBSP3_BASE 0x4808c000
47 #define OMAP2430_MCBSP4_BASE 0x4808e000
48 #define OMAP2430_MCBSP5_BASE 0x48096000
50 #define OMAP34XX_MCBSP1_BASE 0x48074000
51 #define OMAP34XX_MCBSP2_BASE 0x49022000
52 #define OMAP34XX_MCBSP2_ST_BASE 0x49028000
53 #define OMAP34XX_MCBSP3_BASE 0x49024000
54 #define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
55 #define OMAP34XX_MCBSP3_BASE 0x49024000
56 #define OMAP34XX_MCBSP4_BASE 0x49026000
57 #define OMAP34XX_MCBSP5_BASE 0x48096000
59 #define OMAP44XX_MCBSP1_BASE 0x49022000
60 #define OMAP44XX_MCBSP2_BASE 0x49024000
61 #define OMAP44XX_MCBSP3_BASE 0x49026000
62 #define OMAP44XX_MCBSP4_BASE 0x48096000
64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
66 #define OMAP_MCBSP_REG_DRR2 0x00
67 #define OMAP_MCBSP_REG_DRR1 0x02
68 #define OMAP_MCBSP_REG_DXR2 0x04
69 #define OMAP_MCBSP_REG_DXR1 0x06
70 #define OMAP_MCBSP_REG_SPCR2 0x08
71 #define OMAP_MCBSP_REG_SPCR1 0x0a
72 #define OMAP_MCBSP_REG_RCR2 0x0c
73 #define OMAP_MCBSP_REG_RCR1 0x0e
74 #define OMAP_MCBSP_REG_XCR2 0x10
75 #define OMAP_MCBSP_REG_XCR1 0x12
76 #define OMAP_MCBSP_REG_SRGR2 0x14
77 #define OMAP_MCBSP_REG_SRGR1 0x16
78 #define OMAP_MCBSP_REG_MCR2 0x18
79 #define OMAP_MCBSP_REG_MCR1 0x1a
80 #define OMAP_MCBSP_REG_RCERA 0x1c
81 #define OMAP_MCBSP_REG_RCERB 0x1e
82 #define OMAP_MCBSP_REG_XCERA 0x20
83 #define OMAP_MCBSP_REG_XCERB 0x22
84 #define OMAP_MCBSP_REG_PCR0 0x24
85 #define OMAP_MCBSP_REG_RCERC 0x26
86 #define OMAP_MCBSP_REG_RCERD 0x28
87 #define OMAP_MCBSP_REG_XCERC 0x2A
88 #define OMAP_MCBSP_REG_XCERD 0x2C
89 #define OMAP_MCBSP_REG_RCERE 0x2E
90 #define OMAP_MCBSP_REG_RCERF 0x30
91 #define OMAP_MCBSP_REG_XCERE 0x32
92 #define OMAP_MCBSP_REG_XCERF 0x34
93 #define OMAP_MCBSP_REG_RCERG 0x36
94 #define OMAP_MCBSP_REG_RCERH 0x38
95 #define OMAP_MCBSP_REG_XCERG 0x3A
96 #define OMAP_MCBSP_REG_XCERH 0x3C
98 /* Dummy defines, these are not available on omap1 */
99 #define OMAP_MCBSP_REG_XCCR 0x00
100 #define OMAP_MCBSP_REG_RCCR 0x00
102 #define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
103 #define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
105 #define AUDIO_MCBSP OMAP_MCBSP1
106 #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
107 #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
111 #define OMAP_MCBSP_REG_DRR2 0x00
112 #define OMAP_MCBSP_REG_DRR1 0x04
113 #define OMAP_MCBSP_REG_DXR2 0x08
114 #define OMAP_MCBSP_REG_DXR1 0x0C
115 #define OMAP_MCBSP_REG_DRR 0x00
116 #define OMAP_MCBSP_REG_DXR 0x08
117 #define OMAP_MCBSP_REG_SPCR2 0x10
118 #define OMAP_MCBSP_REG_SPCR1 0x14
119 #define OMAP_MCBSP_REG_RCR2 0x18
120 #define OMAP_MCBSP_REG_RCR1 0x1C
121 #define OMAP_MCBSP_REG_XCR2 0x20
122 #define OMAP_MCBSP_REG_XCR1 0x24
123 #define OMAP_MCBSP_REG_SRGR2 0x28
124 #define OMAP_MCBSP_REG_SRGR1 0x2C
125 #define OMAP_MCBSP_REG_MCR2 0x30
126 #define OMAP_MCBSP_REG_MCR1 0x34
127 #define OMAP_MCBSP_REG_RCERA 0x38
128 #define OMAP_MCBSP_REG_RCERB 0x3C
129 #define OMAP_MCBSP_REG_XCERA 0x40
130 #define OMAP_MCBSP_REG_XCERB 0x44
131 #define OMAP_MCBSP_REG_PCR0 0x48
132 #define OMAP_MCBSP_REG_RCERC 0x4C
133 #define OMAP_MCBSP_REG_RCERD 0x50
134 #define OMAP_MCBSP_REG_XCERC 0x54
135 #define OMAP_MCBSP_REG_XCERD 0x58
136 #define OMAP_MCBSP_REG_RCERE 0x5C
137 #define OMAP_MCBSP_REG_RCERF 0x60
138 #define OMAP_MCBSP_REG_XCERE 0x64
139 #define OMAP_MCBSP_REG_XCERF 0x68
140 #define OMAP_MCBSP_REG_RCERG 0x6C
141 #define OMAP_MCBSP_REG_RCERH 0x70
142 #define OMAP_MCBSP_REG_XCERG 0x74
143 #define OMAP_MCBSP_REG_XCERH 0x78
144 #define OMAP_MCBSP_REG_SYSCON 0x8C
145 #define OMAP_MCBSP_REG_THRSH2 0x90
146 #define OMAP_MCBSP_REG_THRSH1 0x94
147 #define OMAP_MCBSP_REG_IRQST 0xA0
148 #define OMAP_MCBSP_REG_IRQEN 0xA4
149 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
150 #define OMAP_MCBSP_REG_XCCR 0xAC
151 #define OMAP_MCBSP_REG_RCCR 0xB0
152 #define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
153 #define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
154 #define OMAP_MCBSP_REG_SSELCR 0xBC
156 #define OMAP_ST_REG_REV 0x00
157 #define OMAP_ST_REG_SYSCONFIG 0x10
158 #define OMAP_ST_REG_IRQSTATUS 0x18
159 #define OMAP_ST_REG_IRQENABLE 0x1C
160 #define OMAP_ST_REG_SGAINCR 0x24
161 #define OMAP_ST_REG_SFIRCR 0x28
162 #define OMAP_ST_REG_SSELCR 0x2C
164 #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
165 #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
167 #define AUDIO_MCBSP OMAP_MCBSP2
168 #define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
169 #define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
173 /************************** McBSP SPCR1 bit definitions ***********************/
177 #define RSYNC_ERR 0x0008
178 #define RINTM(value) ((value)<<4) /* bits 4:5 */
181 #define CLKSTP(value) ((value)<<11) /* bits 11:12 */
182 #define RJUST(value) ((value)<<13) /* bits 13:14 */
186 /************************** McBSP SPCR2 bit definitions ***********************/
189 #define XEMPTY 0x0004
190 #define XSYNC_ERR 0x0008
191 #define XINTM(value) ((value)<<4) /* bits 4:5 */
197 /************************** McBSP PCR bit definitions *************************/
202 #define DR_STAT 0x0010
203 #define DX_STAT 0x0020
204 #define CLKS_STAT 0x0040
205 #define SCLKME 0x0080
212 #define IDLE_EN 0x4000
214 /************************** McBSP RCR1 bit definitions ************************/
215 #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
216 #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
218 /************************** McBSP XCR1 bit definitions ************************/
219 #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
220 #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
222 /*************************** McBSP RCR2 bit definitions ***********************/
223 #define RDATDLY(value) (value) /* Bits 0:1 */
225 #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
226 #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
227 #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
228 #define RPHASE 0x8000
230 /*************************** McBSP XCR2 bit definitions ***********************/
231 #define XDATDLY(value) (value) /* Bits 0:1 */
233 #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
234 #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
235 #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
236 #define XPHASE 0x8000
238 /************************* McBSP SRGR1 bit definitions ************************/
239 #define CLKGDV(value) (value) /* Bits 0:7 */
240 #define FWID(value) ((value)<<8) /* Bits 8:15 */
242 /************************* McBSP SRGR2 bit definitions ************************/
243 #define FPER(value) (value) /* Bits 0:11 */
249 /************************* McBSP MCR1 bit definitions *************************/
251 #define RCBLK(value) ((value)<<2) /* Bits 2:4 */
252 #define RPABLK(value) ((value)<<5) /* Bits 5:6 */
253 #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
255 /************************* McBSP MCR2 bit definitions *************************/
256 #define XMCM(value) (value) /* Bits 0:1 */
257 #define XCBLK(value) ((value)<<2) /* Bits 2:4 */
258 #define XPABLK(value) ((value)<<5) /* Bits 5:6 */
259 #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
261 /*********************** McBSP XCCR bit definitions *************************/
262 #define EXTCLKGATE 0x8000
263 #define PPCONNECT 0x4000
264 #define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
265 #define XFULL_CYCLE 0x0800
267 #define XDMAEN 0x0008
268 #define XDISABLE 0x0001
270 /********************** McBSP RCCR bit definitions *************************/
271 #define RFULL_CYCLE 0x0800
272 #define RDMAEN 0x0008
273 #define RDISABLE 0x0001
275 /********************** McBSP SYSCONFIG bit definitions ********************/
276 #define CLOCKACTIVITY(value) ((value)<<8)
277 #define SIDLEMODE(value) ((value)<<3)
278 #define ENAWAKEUP 0x0004
279 #define SOFTRST 0x0002
281 /********************** McBSP SSELCR bit definitions ***********************/
282 #define SIDETONEEN 0x0400
284 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
285 #define ST_AUTOIDLE 0x0001
287 /********************** McBSP Sidetone SGAINCR bit definitions *************/
288 #define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
289 #define ST_CH0GAIN(value) (value) /* Bits 0:15 */
291 /********************** McBSP Sidetone SFIRCR bit definitions **************/
292 #define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
294 /********************** McBSP Sidetone SSELCR bit definitions **************/
295 #define ST_COEFFWRDONE 0x0004
296 #define ST_COEFFWREN 0x0002
297 #define ST_SIDETONEEN 0x0001
299 /********************** McBSP DMA operating modes **************************/
300 #define MCBSP_DMA_MODE_ELEMENT 0
301 #define MCBSP_DMA_MODE_THRESHOLD 1
302 #define MCBSP_DMA_MODE_FRAME 2
304 /********************** McBSP WAKEUPEN bit definitions *********************/
305 #define XEMPTYEOFEN 0x4000
306 #define XRDYEN 0x0400
307 #define XEOFEN 0x0200
308 #define XFSXEN 0x0100
309 #define XSYNCERREN 0x0080
310 #define RRDYEN 0x0008
311 #define REOFEN 0x0004
312 #define RFSREN 0x0002
313 #define RSYNCERREN 0x0001
315 /* we don't do multichannel for now */
316 struct omap_mcbsp_reg_cfg {
352 typedef int __bitwise omap_mcbsp_io_type_t;
353 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
354 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
357 OMAP_MCBSP_WORD_8 = 0,
363 } omap_mcbsp_word_length;
366 OMAP_MCBSP_CLK_RISING = 0,
367 OMAP_MCBSP_CLK_FALLING,
368 } omap_mcbsp_clk_polarity;
371 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
372 OMAP_MCBSP_FS_ACTIVE_LOW,
373 } omap_mcbsp_fs_polarity;
376 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
377 OMAP_MCBSP_CLK_STP_MODE_DELAY,
378 } omap_mcbsp_clk_stp_mode;
381 /******* SPI specific mode **********/
383 OMAP_MCBSP_SPI_MASTER = 0,
384 OMAP_MCBSP_SPI_SLAVE,
385 } omap_mcbsp_spi_mode;
387 struct omap_mcbsp_spi_cfg {
388 omap_mcbsp_spi_mode spi_mode;
389 omap_mcbsp_clk_polarity rx_clock_polarity;
390 omap_mcbsp_clk_polarity tx_clock_polarity;
391 omap_mcbsp_fs_polarity fsx_polarity;
393 omap_mcbsp_clk_stp_mode clk_stp_mode;
394 omap_mcbsp_word_length word_length;
397 /* Platform specific configuration */
398 struct omap_mcbsp_ops {
399 void (*request)(unsigned int);
400 void (*free)(unsigned int);
403 struct omap_mcbsp_platform_data {
404 unsigned long phys_base;
405 u8 dma_rx_sync, dma_tx_sync;
407 struct omap_mcbsp_ops *ops;
408 #ifdef CONFIG_ARCH_OMAP3
409 /* Sidetone block for McBSP 2 and 3 */
410 unsigned long phys_base_st;
415 struct omap_mcbsp_st_data {
416 void __iomem *io_base_st;
419 s16 taps[128]; /* Sidetone filter coefficients */
420 int nr_taps; /* Number of filter coefficients in use */
427 unsigned long phys_base;
428 void __iomem *io_base;
431 omap_mcbsp_word_length rx_word_length;
432 omap_mcbsp_word_length tx_word_length;
434 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
435 /* IRQ based TX/RX */
445 /* Completion queues */
446 struct completion tx_irq_completion;
447 struct completion rx_irq_completion;
448 struct completion tx_dma_completion;
449 struct completion rx_dma_completion;
451 /* Protect the field .free, while checking if the mcbsp is in use */
453 struct omap_mcbsp_platform_data *pdata;
456 #ifdef CONFIG_ARCH_OMAP3
457 struct omap_mcbsp_st_data *st_data;
464 extern struct omap_mcbsp **mcbsp_ptr;
465 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
467 int omap_mcbsp_init(void);
468 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
470 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
471 #ifdef CONFIG_ARCH_OMAP3
472 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
473 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
474 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
475 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
476 u16 omap_mcbsp_get_tx_delay(unsigned int id);
477 u16 omap_mcbsp_get_rx_delay(unsigned int id);
478 int omap_mcbsp_get_dma_op_mode(unsigned int id);
480 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
482 static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
484 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
485 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
486 static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
487 static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
488 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
490 int omap_mcbsp_request(unsigned int id);
491 void omap_mcbsp_free(unsigned int id);
492 void omap_mcbsp_start(unsigned int id, int tx, int rx);
493 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
494 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
495 u32 omap_mcbsp_recv_word(unsigned int id);
497 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
498 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
499 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
500 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
503 /* SPI specific API */
504 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
506 /* Polled read/write functions */
507 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
508 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
509 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
511 #ifdef CONFIG_ARCH_OMAP3
512 /* Sidetone specific API */
513 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
514 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
515 int omap_st_enable(unsigned int id);
516 int omap_st_disable(unsigned int id);
517 int omap_st_is_enabled(unsigned int id);
519 static inline int omap_st_set_chgain(unsigned int id, int channel,
520 s16 chgain) { return 0; }
521 static inline int omap_st_get_chgain(unsigned int id, int channel,
522 s16 *chgain) { return 0; }
523 static inline int omap_st_enable(unsigned int id) { return 0; }
524 static inline int omap_st_disable(unsigned int id) { return 0; }
525 static inline int omap_st_is_enabled(unsigned int id) { return 0; }