2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30 #include <plat/powerdomain.h>
33 * OMAP1510 GPIO registers
35 #define OMAP1510_GPIO_BASE 0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
44 #define OMAP1510_IH_GPIO_BASE 64
47 * OMAP1610 specific GPIO registers
49 #define OMAP1610_GPIO1_BASE 0xfffbe400
50 #define OMAP1610_GPIO2_BASE 0xfffbec00
51 #define OMAP1610_GPIO3_BASE 0xfffbb400
52 #define OMAP1610_GPIO4_BASE 0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
72 * OMAP7XX specific GPIO registers
74 #define OMAP7XX_GPIO1_BASE 0xfffbc000
75 #define OMAP7XX_GPIO2_BASE 0xfffbc800
76 #define OMAP7XX_GPIO3_BASE 0xfffbd000
77 #define OMAP7XX_GPIO4_BASE 0xfffbd800
78 #define OMAP7XX_GPIO5_BASE 0xfffbe000
79 #define OMAP7XX_GPIO6_BASE 0xfffbe800
80 #define OMAP7XX_GPIO_DATA_INPUT 0x00
81 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
83 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
84 #define OMAP7XX_GPIO_INT_MASK 0x10
85 #define OMAP7XX_GPIO_INT_STATUS 0x14
87 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
90 * omap24xx specific GPIO registers
92 #define OMAP242X_GPIO1_BASE 0x48018000
93 #define OMAP242X_GPIO2_BASE 0x4801a000
94 #define OMAP242X_GPIO3_BASE 0x4801c000
95 #define OMAP242X_GPIO4_BASE 0x4801e000
97 #define OMAP243X_GPIO1_BASE 0x4900C000
98 #define OMAP243X_GPIO2_BASE 0x4900E000
99 #define OMAP243X_GPIO3_BASE 0x49010000
100 #define OMAP243X_GPIO4_BASE 0x49012000
101 #define OMAP243X_GPIO5_BASE 0x480B6000
103 #define OMAP24XX_GPIO_REVISION 0x0000
104 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
105 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
106 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
107 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
109 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
110 #define OMAP24XX_GPIO_WAKE_EN 0x0020
111 #define OMAP24XX_GPIO_CTRL 0x0030
112 #define OMAP24XX_GPIO_OE 0x0034
113 #define OMAP24XX_GPIO_DATAIN 0x0038
114 #define OMAP24XX_GPIO_DATAOUT 0x003c
115 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
116 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
117 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
118 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
119 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
120 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
121 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
122 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
123 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
124 #define OMAP24XX_GPIO_SETWKUENA 0x0084
125 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
126 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
128 #define OMAP4_GPIO_REVISION 0x0000
129 #define OMAP4_GPIO_SYSCONFIG 0x0010
130 #define OMAP4_GPIO_EOI 0x0020
131 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
133 #define OMAP4_GPIO_IRQSTATUS0 0x002c
134 #define OMAP4_GPIO_IRQSTATUS1 0x0030
135 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
136 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
137 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
138 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139 #define OMAP4_GPIO_IRQWAKEN0 0x0044
140 #define OMAP4_GPIO_IRQWAKEN1 0x0048
141 #define OMAP4_GPIO_SYSSTATUS 0x0114
142 #define OMAP4_GPIO_IRQENABLE1 0x011c
143 #define OMAP4_GPIO_WAKE_EN 0x0120
144 #define OMAP4_GPIO_IRQSTATUS2 0x0128
145 #define OMAP4_GPIO_IRQENABLE2 0x012c
146 #define OMAP4_GPIO_CTRL 0x0130
147 #define OMAP4_GPIO_OE 0x0134
148 #define OMAP4_GPIO_DATAIN 0x0138
149 #define OMAP4_GPIO_DATAOUT 0x013c
150 #define OMAP4_GPIO_LEVELDETECT0 0x0140
151 #define OMAP4_GPIO_LEVELDETECT1 0x0144
152 #define OMAP4_GPIO_RISINGDETECT 0x0148
153 #define OMAP4_GPIO_FALLINGDETECT 0x014c
154 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
155 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
156 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
157 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
158 #define OMAP4_GPIO_CLEARWKUENA 0x0180
159 #define OMAP4_GPIO_SETWKUENA 0x0184
160 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
161 #define OMAP4_GPIO_SETDATAOUT 0x0194
163 * omap34xx specific GPIO registers
166 #define OMAP34XX_GPIO1_BASE 0x48310000
167 #define OMAP34XX_GPIO2_BASE 0x49050000
168 #define OMAP34XX_GPIO3_BASE 0x49052000
169 #define OMAP34XX_GPIO4_BASE 0x49054000
170 #define OMAP34XX_GPIO5_BASE 0x49056000
171 #define OMAP34XX_GPIO6_BASE 0x49058000
174 * OMAP44XX specific GPIO registers
176 #define OMAP44XX_GPIO1_BASE 0x4a310000
177 #define OMAP44XX_GPIO2_BASE 0x48055000
178 #define OMAP44XX_GPIO3_BASE 0x48057000
179 #define OMAP44XX_GPIO4_BASE 0x48059000
180 #define OMAP44XX_GPIO5_BASE 0x4805B000
181 #define OMAP44XX_GPIO6_BASE 0x4805D000
187 u16 virtual_irq_start;
189 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
193 u32 non_wakeup_gpios;
194 u32 enabled_non_wakeup_gpios;
197 u32 saved_fallingdetect;
198 u32 saved_risingdetect;
202 struct gpio_chip chip;
205 u32 dbck_enable_mask;
208 #define METHOD_MPUIO 0
209 #define METHOD_GPIO_1510 1
210 #define METHOD_GPIO_1610 2
211 #define METHOD_GPIO_7XX 3
212 #define METHOD_GPIO_24XX 5
213 #define METHOD_GPIO_44XX 6
215 #ifdef CONFIG_ARCH_OMAP16XX
216 static struct gpio_bank gpio_bank_1610[5] = {
217 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
219 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
221 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
223 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
225 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
230 #ifdef CONFIG_ARCH_OMAP15XX
231 static struct gpio_bank gpio_bank_1510[2] = {
232 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
234 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
239 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
240 static struct gpio_bank gpio_bank_7xx[7] = {
241 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
243 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
245 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
247 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
249 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
251 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
253 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
258 #ifdef CONFIG_ARCH_OMAP2
260 static struct gpio_bank gpio_bank_242x[4] = {
261 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
263 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
265 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
267 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
271 static struct gpio_bank gpio_bank_243x[5] = {
272 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
274 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
276 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
278 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
280 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
286 #ifdef CONFIG_ARCH_OMAP3
287 static struct gpio_bank gpio_bank_34xx[6] = {
288 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
290 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
292 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
294 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
296 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
298 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
302 struct omap3_gpio_regs {
316 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
319 #ifdef CONFIG_ARCH_OMAP4
320 static struct gpio_bank gpio_bank_44xx[6] = {
321 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
323 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
325 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
327 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
329 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
331 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
337 static struct gpio_bank *gpio_bank;
338 static int gpio_bank_count;
340 static inline struct gpio_bank *get_gpio_bank(int gpio)
342 if (cpu_is_omap15xx()) {
343 if (OMAP_GPIO_IS_MPUIO(gpio))
344 return &gpio_bank[0];
345 return &gpio_bank[1];
347 if (cpu_is_omap16xx()) {
348 if (OMAP_GPIO_IS_MPUIO(gpio))
349 return &gpio_bank[0];
350 return &gpio_bank[1 + (gpio >> 4)];
352 if (cpu_is_omap7xx()) {
353 if (OMAP_GPIO_IS_MPUIO(gpio))
354 return &gpio_bank[0];
355 return &gpio_bank[1 + (gpio >> 5)];
357 if (cpu_is_omap24xx())
358 return &gpio_bank[gpio >> 5];
359 if (cpu_is_omap34xx() || cpu_is_omap44xx())
360 return &gpio_bank[gpio >> 5];
365 static inline int get_gpio_index(int gpio)
367 if (cpu_is_omap7xx())
369 if (cpu_is_omap24xx())
371 if (cpu_is_omap34xx() || cpu_is_omap44xx())
376 static inline int gpio_valid(int gpio)
380 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
381 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
385 if (cpu_is_omap15xx() && gpio < 16)
387 if ((cpu_is_omap16xx()) && gpio < 64)
389 if (cpu_is_omap7xx() && gpio < 192)
391 if (cpu_is_omap2420() && gpio < 128)
393 if (cpu_is_omap2430() && gpio < 160)
395 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
400 static int check_gpio(int gpio)
402 if (unlikely(gpio_valid(gpio) < 0)) {
403 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
410 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
412 void __iomem *reg = bank->base;
415 switch (bank->method) {
416 #ifdef CONFIG_ARCH_OMAP1
418 reg += OMAP_MPUIO_IO_CNTL;
421 #ifdef CONFIG_ARCH_OMAP15XX
422 case METHOD_GPIO_1510:
423 reg += OMAP1510_GPIO_DIR_CONTROL;
426 #ifdef CONFIG_ARCH_OMAP16XX
427 case METHOD_GPIO_1610:
428 reg += OMAP1610_GPIO_DIRECTION;
431 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
432 case METHOD_GPIO_7XX:
433 reg += OMAP7XX_GPIO_DIR_CONTROL;
436 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
437 case METHOD_GPIO_24XX:
438 reg += OMAP24XX_GPIO_OE;
441 #if defined(CONFIG_ARCH_OMAP4)
442 case METHOD_GPIO_44XX:
443 reg += OMAP4_GPIO_OE;
450 l = __raw_readl(reg);
455 __raw_writel(l, reg);
458 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
460 void __iomem *reg = bank->base;
463 switch (bank->method) {
464 #ifdef CONFIG_ARCH_OMAP1
466 reg += OMAP_MPUIO_OUTPUT;
467 l = __raw_readl(reg);
474 #ifdef CONFIG_ARCH_OMAP15XX
475 case METHOD_GPIO_1510:
476 reg += OMAP1510_GPIO_DATA_OUTPUT;
477 l = __raw_readl(reg);
484 #ifdef CONFIG_ARCH_OMAP16XX
485 case METHOD_GPIO_1610:
487 reg += OMAP1610_GPIO_SET_DATAOUT;
489 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
493 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
494 case METHOD_GPIO_7XX:
495 reg += OMAP7XX_GPIO_DATA_OUTPUT;
496 l = __raw_readl(reg);
503 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
504 case METHOD_GPIO_24XX:
506 reg += OMAP24XX_GPIO_SETDATAOUT;
508 reg += OMAP24XX_GPIO_CLEARDATAOUT;
512 #ifdef CONFIG_ARCH_OMAP4
513 case METHOD_GPIO_44XX:
515 reg += OMAP4_GPIO_SETDATAOUT;
517 reg += OMAP4_GPIO_CLEARDATAOUT;
525 __raw_writel(l, reg);
528 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
532 if (check_gpio(gpio) < 0)
535 switch (bank->method) {
536 #ifdef CONFIG_ARCH_OMAP1
538 reg += OMAP_MPUIO_INPUT_LATCH;
541 #ifdef CONFIG_ARCH_OMAP15XX
542 case METHOD_GPIO_1510:
543 reg += OMAP1510_GPIO_DATA_INPUT;
546 #ifdef CONFIG_ARCH_OMAP16XX
547 case METHOD_GPIO_1610:
548 reg += OMAP1610_GPIO_DATAIN;
551 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
552 case METHOD_GPIO_7XX:
553 reg += OMAP7XX_GPIO_DATA_INPUT;
556 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
557 case METHOD_GPIO_24XX:
558 reg += OMAP24XX_GPIO_DATAIN;
561 #ifdef CONFIG_ARCH_OMAP4
562 case METHOD_GPIO_44XX:
563 reg += OMAP4_GPIO_DATAIN;
569 return (__raw_readl(reg)
570 & (1 << get_gpio_index(gpio))) != 0;
573 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
577 if (check_gpio(gpio) < 0)
581 switch (bank->method) {
582 #ifdef CONFIG_ARCH_OMAP1
584 reg += OMAP_MPUIO_OUTPUT;
587 #ifdef CONFIG_ARCH_OMAP15XX
588 case METHOD_GPIO_1510:
589 reg += OMAP1510_GPIO_DATA_OUTPUT;
592 #ifdef CONFIG_ARCH_OMAP16XX
593 case METHOD_GPIO_1610:
594 reg += OMAP1610_GPIO_DATAOUT;
597 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
598 case METHOD_GPIO_7XX:
599 reg += OMAP7XX_GPIO_DATA_OUTPUT;
602 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
603 case METHOD_GPIO_24XX:
604 reg += OMAP24XX_GPIO_DATAOUT;
607 #ifdef CONFIG_ARCH_OMAP4
608 case METHOD_GPIO_44XX:
609 reg += OMAP4_GPIO_DATAOUT;
616 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
619 #define MOD_REG_BIT(reg, bit_mask, set) \
621 int l = __raw_readl(base + reg); \
622 if (set) l |= bit_mask; \
623 else l &= ~bit_mask; \
624 __raw_writel(l, base + reg); \
628 * _set_gpio_debounce - low level gpio debounce time
629 * @bank: the gpio bank we're acting upon
630 * @gpio: the gpio number on this @gpio
631 * @debounce: debounce time to use
633 * OMAP's debounce time is in 31us steps so we need
634 * to convert and round up to the closest unit.
636 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
639 void __iomem *reg = bank->base;
645 else if (debounce > 7936)
648 debounce = (debounce / 0x1f) - 1;
650 l = 1 << get_gpio_index(gpio);
652 if (cpu_is_omap44xx())
653 reg += OMAP4_GPIO_DEBOUNCINGTIME;
655 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
657 __raw_writel(debounce, reg);
660 if (cpu_is_omap44xx())
661 reg += OMAP4_GPIO_DEBOUNCENABLE;
663 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
665 val = __raw_readl(reg);
669 if (cpu_is_omap34xx() || cpu_is_omap44xx())
670 clk_enable(bank->dbck);
673 if (cpu_is_omap34xx() || cpu_is_omap44xx())
674 clk_disable(bank->dbck);
676 bank->dbck_enable_mask = val;
678 __raw_writel(val, reg);
681 #ifdef CONFIG_ARCH_OMAP2PLUS
682 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
685 void __iomem *base = bank->base;
686 u32 gpio_bit = 1 << gpio;
689 if (cpu_is_omap44xx()) {
690 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
691 trigger & IRQ_TYPE_LEVEL_LOW);
692 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
693 trigger & IRQ_TYPE_LEVEL_HIGH);
694 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
695 trigger & IRQ_TYPE_EDGE_RISING);
696 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
697 trigger & IRQ_TYPE_EDGE_FALLING);
699 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
700 trigger & IRQ_TYPE_LEVEL_LOW);
701 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
702 trigger & IRQ_TYPE_LEVEL_HIGH);
703 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
704 trigger & IRQ_TYPE_EDGE_RISING);
705 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
706 trigger & IRQ_TYPE_EDGE_FALLING);
708 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
709 if (cpu_is_omap44xx()) {
711 __raw_writel(1 << gpio, bank->base+
712 OMAP4_GPIO_IRQWAKEN0);
714 val = __raw_readl(bank->base +
715 OMAP4_GPIO_IRQWAKEN0);
716 __raw_writel(val & (~(1 << gpio)), bank->base +
717 OMAP4_GPIO_IRQWAKEN0);
721 * GPIO wakeup request can only be generated on edge
724 if (trigger & IRQ_TYPE_EDGE_BOTH)
725 __raw_writel(1 << gpio, bank->base
726 + OMAP24XX_GPIO_SETWKUENA);
728 __raw_writel(1 << gpio, bank->base
729 + OMAP24XX_GPIO_CLEARWKUENA);
732 /* This part needs to be executed always for OMAP34xx */
733 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
735 * Log the edge gpio and manually trigger the IRQ
736 * after resume if the input level changes
737 * to avoid irq lost during PER RET/OFF mode
738 * Applies for omap2 non-wakeup gpio and all omap3 gpios
740 if (trigger & IRQ_TYPE_EDGE_BOTH)
741 bank->enabled_non_wakeup_gpios |= gpio_bit;
743 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
746 if (cpu_is_omap44xx()) {
748 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
749 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
752 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
753 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
758 #ifdef CONFIG_ARCH_OMAP1
760 * This only applies to chips that can't do both rising and falling edge
761 * detection at once. For all other chips, this function is a noop.
763 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
765 void __iomem *reg = bank->base;
768 switch (bank->method) {
770 reg += OMAP_MPUIO_GPIO_INT_EDGE;
772 #ifdef CONFIG_ARCH_OMAP15XX
773 case METHOD_GPIO_1510:
774 reg += OMAP1510_GPIO_INT_CONTROL;
777 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
778 case METHOD_GPIO_7XX:
779 reg += OMAP7XX_GPIO_INT_CONTROL;
786 l = __raw_readl(reg);
792 __raw_writel(l, reg);
796 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
798 void __iomem *reg = bank->base;
801 switch (bank->method) {
802 #ifdef CONFIG_ARCH_OMAP1
804 reg += OMAP_MPUIO_GPIO_INT_EDGE;
805 l = __raw_readl(reg);
806 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
807 bank->toggle_mask |= 1 << gpio;
808 if (trigger & IRQ_TYPE_EDGE_RISING)
810 else if (trigger & IRQ_TYPE_EDGE_FALLING)
816 #ifdef CONFIG_ARCH_OMAP15XX
817 case METHOD_GPIO_1510:
818 reg += OMAP1510_GPIO_INT_CONTROL;
819 l = __raw_readl(reg);
820 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
821 bank->toggle_mask |= 1 << gpio;
822 if (trigger & IRQ_TYPE_EDGE_RISING)
824 else if (trigger & IRQ_TYPE_EDGE_FALLING)
830 #ifdef CONFIG_ARCH_OMAP16XX
831 case METHOD_GPIO_1610:
833 reg += OMAP1610_GPIO_EDGE_CTRL2;
835 reg += OMAP1610_GPIO_EDGE_CTRL1;
837 l = __raw_readl(reg);
838 l &= ~(3 << (gpio << 1));
839 if (trigger & IRQ_TYPE_EDGE_RISING)
840 l |= 2 << (gpio << 1);
841 if (trigger & IRQ_TYPE_EDGE_FALLING)
842 l |= 1 << (gpio << 1);
844 /* Enable wake-up during idle for dynamic tick */
845 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
847 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
850 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
851 case METHOD_GPIO_7XX:
852 reg += OMAP7XX_GPIO_INT_CONTROL;
853 l = __raw_readl(reg);
854 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
855 bank->toggle_mask |= 1 << gpio;
856 if (trigger & IRQ_TYPE_EDGE_RISING)
858 else if (trigger & IRQ_TYPE_EDGE_FALLING)
864 #ifdef CONFIG_ARCH_OMAP2PLUS
865 case METHOD_GPIO_24XX:
866 case METHOD_GPIO_44XX:
867 set_24xx_gpio_triggering(bank, gpio, trigger);
873 __raw_writel(l, reg);
879 static int gpio_irq_type(unsigned irq, unsigned type)
881 struct gpio_bank *bank;
886 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
887 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
889 gpio = irq - IH_GPIO_BASE;
891 if (check_gpio(gpio) < 0)
894 if (type & ~IRQ_TYPE_SENSE_MASK)
897 /* OMAP1 allows only only edge triggering */
898 if (!cpu_class_is_omap2()
899 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
902 bank = get_irq_chip_data(irq);
903 spin_lock_irqsave(&bank->lock, flags);
904 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
906 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
907 irq_desc[irq].status |= type;
909 spin_unlock_irqrestore(&bank->lock, flags);
911 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
912 __set_irq_handler_unlocked(irq, handle_level_irq);
913 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
914 __set_irq_handler_unlocked(irq, handle_edge_irq);
919 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
921 void __iomem *reg = bank->base;
923 switch (bank->method) {
924 #ifdef CONFIG_ARCH_OMAP1
926 /* MPUIO irqstatus is reset by reading the status register,
927 * so do nothing here */
930 #ifdef CONFIG_ARCH_OMAP15XX
931 case METHOD_GPIO_1510:
932 reg += OMAP1510_GPIO_INT_STATUS;
935 #ifdef CONFIG_ARCH_OMAP16XX
936 case METHOD_GPIO_1610:
937 reg += OMAP1610_GPIO_IRQSTATUS1;
940 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
941 case METHOD_GPIO_7XX:
942 reg += OMAP7XX_GPIO_INT_STATUS;
945 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
946 case METHOD_GPIO_24XX:
947 reg += OMAP24XX_GPIO_IRQSTATUS1;
950 #if defined(CONFIG_ARCH_OMAP4)
951 case METHOD_GPIO_44XX:
952 reg += OMAP4_GPIO_IRQSTATUS0;
959 __raw_writel(gpio_mask, reg);
961 /* Workaround for clearing DSP GPIO interrupts to allow retention */
962 if (cpu_is_omap24xx() || cpu_is_omap34xx())
963 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
964 else if (cpu_is_omap44xx())
965 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
967 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
968 __raw_writel(gpio_mask, reg);
970 /* Flush posted write for the irq status to avoid spurious interrupts */
975 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
977 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
980 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
982 void __iomem *reg = bank->base;
987 switch (bank->method) {
988 #ifdef CONFIG_ARCH_OMAP1
990 reg += OMAP_MPUIO_GPIO_MASKIT;
995 #ifdef CONFIG_ARCH_OMAP15XX
996 case METHOD_GPIO_1510:
997 reg += OMAP1510_GPIO_INT_MASK;
1002 #ifdef CONFIG_ARCH_OMAP16XX
1003 case METHOD_GPIO_1610:
1004 reg += OMAP1610_GPIO_IRQENABLE1;
1008 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1009 case METHOD_GPIO_7XX:
1010 reg += OMAP7XX_GPIO_INT_MASK;
1015 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1016 case METHOD_GPIO_24XX:
1017 reg += OMAP24XX_GPIO_IRQENABLE1;
1021 #if defined(CONFIG_ARCH_OMAP4)
1022 case METHOD_GPIO_44XX:
1023 reg += OMAP4_GPIO_IRQSTATUSSET0;
1032 l = __raw_readl(reg);
1039 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1041 void __iomem *reg = bank->base;
1044 switch (bank->method) {
1045 #ifdef CONFIG_ARCH_OMAP1
1047 reg += OMAP_MPUIO_GPIO_MASKIT;
1048 l = __raw_readl(reg);
1055 #ifdef CONFIG_ARCH_OMAP15XX
1056 case METHOD_GPIO_1510:
1057 reg += OMAP1510_GPIO_INT_MASK;
1058 l = __raw_readl(reg);
1065 #ifdef CONFIG_ARCH_OMAP16XX
1066 case METHOD_GPIO_1610:
1068 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1070 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1074 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1075 case METHOD_GPIO_7XX:
1076 reg += OMAP7XX_GPIO_INT_MASK;
1077 l = __raw_readl(reg);
1084 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1085 case METHOD_GPIO_24XX:
1087 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1089 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1093 #ifdef CONFIG_ARCH_OMAP4
1094 case METHOD_GPIO_44XX:
1096 reg += OMAP4_GPIO_IRQSTATUSSET0;
1098 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1106 __raw_writel(l, reg);
1109 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1111 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1115 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1116 * 1510 does not seem to have a wake-up register. If JTAG is connected
1117 * to the target, system will wake up always on GPIO events. While
1118 * system is running all registered GPIO interrupts need to have wake-up
1119 * enabled. When system is suspended, only selected GPIO interrupts need
1120 * to have wake-up enabled.
1122 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1124 unsigned long uninitialized_var(flags);
1126 switch (bank->method) {
1127 #ifdef CONFIG_ARCH_OMAP16XX
1129 case METHOD_GPIO_1610:
1130 spin_lock_irqsave(&bank->lock, flags);
1132 bank->suspend_wakeup |= (1 << gpio);
1134 bank->suspend_wakeup &= ~(1 << gpio);
1135 spin_unlock_irqrestore(&bank->lock, flags);
1138 #ifdef CONFIG_ARCH_OMAP2PLUS
1139 case METHOD_GPIO_24XX:
1140 case METHOD_GPIO_44XX:
1141 if (bank->non_wakeup_gpios & (1 << gpio)) {
1142 printk(KERN_ERR "Unable to modify wakeup on "
1143 "non-wakeup GPIO%d\n",
1144 (bank - gpio_bank) * 32 + gpio);
1147 spin_lock_irqsave(&bank->lock, flags);
1149 bank->suspend_wakeup |= (1 << gpio);
1151 bank->suspend_wakeup &= ~(1 << gpio);
1152 spin_unlock_irqrestore(&bank->lock, flags);
1156 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1162 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1164 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1165 _set_gpio_irqenable(bank, gpio, 0);
1166 _clear_gpio_irqstatus(bank, gpio);
1167 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1170 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1171 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1173 unsigned int gpio = irq - IH_GPIO_BASE;
1174 struct gpio_bank *bank;
1177 if (check_gpio(gpio) < 0)
1179 bank = get_irq_chip_data(irq);
1180 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1185 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1187 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1188 unsigned long flags;
1190 spin_lock_irqsave(&bank->lock, flags);
1192 /* Set trigger to none. You need to enable the desired trigger with
1193 * request_irq() or set_irq_type().
1195 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1197 #ifdef CONFIG_ARCH_OMAP15XX
1198 if (bank->method == METHOD_GPIO_1510) {
1201 /* Claim the pin for MPU */
1202 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1203 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1206 if (!cpu_class_is_omap1()) {
1207 if (!bank->mod_usage) {
1208 void __iomem *reg = bank->base;
1211 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1212 reg += OMAP24XX_GPIO_CTRL;
1213 else if (cpu_is_omap44xx())
1214 reg += OMAP4_GPIO_CTRL;
1215 ctrl = __raw_readl(reg);
1216 /* Module is enabled, clocks are not gated */
1218 __raw_writel(ctrl, reg);
1220 bank->mod_usage |= 1 << offset;
1222 spin_unlock_irqrestore(&bank->lock, flags);
1227 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1229 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1230 unsigned long flags;
1232 spin_lock_irqsave(&bank->lock, flags);
1233 #ifdef CONFIG_ARCH_OMAP16XX
1234 if (bank->method == METHOD_GPIO_1610) {
1235 /* Disable wake-up during idle for dynamic tick */
1236 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1237 __raw_writel(1 << offset, reg);
1240 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1241 if (bank->method == METHOD_GPIO_24XX) {
1242 /* Disable wake-up during idle for dynamic tick */
1243 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1244 __raw_writel(1 << offset, reg);
1247 #ifdef CONFIG_ARCH_OMAP4
1248 if (bank->method == METHOD_GPIO_44XX) {
1249 /* Disable wake-up during idle for dynamic tick */
1250 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1251 __raw_writel(1 << offset, reg);
1254 if (!cpu_class_is_omap1()) {
1255 bank->mod_usage &= ~(1 << offset);
1256 if (!bank->mod_usage) {
1257 void __iomem *reg = bank->base;
1260 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1261 reg += OMAP24XX_GPIO_CTRL;
1262 else if (cpu_is_omap44xx())
1263 reg += OMAP4_GPIO_CTRL;
1264 ctrl = __raw_readl(reg);
1265 /* Module is disabled, clocks are gated */
1267 __raw_writel(ctrl, reg);
1270 _reset_gpio(bank, bank->chip.base + offset);
1271 spin_unlock_irqrestore(&bank->lock, flags);
1275 * We need to unmask the GPIO bank interrupt as soon as possible to
1276 * avoid missing GPIO interrupts for other lines in the bank.
1277 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1278 * in the bank to avoid missing nested interrupts for a GPIO line.
1279 * If we wait to unmask individual GPIO lines in the bank after the
1280 * line's interrupt handler has been run, we may miss some nested
1283 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1285 void __iomem *isr_reg = NULL;
1287 unsigned int gpio_irq, gpio_index;
1288 struct gpio_bank *bank;
1292 desc->chip->ack(irq);
1294 bank = get_irq_data(irq);
1295 #ifdef CONFIG_ARCH_OMAP1
1296 if (bank->method == METHOD_MPUIO)
1297 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1299 #ifdef CONFIG_ARCH_OMAP15XX
1300 if (bank->method == METHOD_GPIO_1510)
1301 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1303 #if defined(CONFIG_ARCH_OMAP16XX)
1304 if (bank->method == METHOD_GPIO_1610)
1305 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1307 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1308 if (bank->method == METHOD_GPIO_7XX)
1309 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1311 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1312 if (bank->method == METHOD_GPIO_24XX)
1313 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1315 #if defined(CONFIG_ARCH_OMAP4)
1316 if (bank->method == METHOD_GPIO_44XX)
1317 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1320 if (WARN_ON(!isr_reg))
1324 u32 isr_saved, level_mask = 0;
1327 enabled = _get_gpio_irqbank_mask(bank);
1328 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1330 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1333 if (cpu_class_is_omap2()) {
1334 level_mask = bank->level_mask & enabled;
1337 /* clear edge sensitive interrupts before handler(s) are
1338 called so that we don't miss any interrupt occurred while
1340 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1341 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1342 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1344 /* if there is only edge sensitive GPIO pin interrupts
1345 configured, we could unmask GPIO bank interrupt immediately */
1346 if (!level_mask && !unmasked) {
1348 desc->chip->unmask(irq);
1356 gpio_irq = bank->virtual_irq_start;
1357 for (; isr != 0; isr >>= 1, gpio_irq++) {
1358 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1363 #ifdef CONFIG_ARCH_OMAP1
1365 * Some chips can't respond to both rising and falling
1366 * at the same time. If this irq was requested with
1367 * both flags, we need to flip the ICR data for the IRQ
1368 * to respond to the IRQ for the opposite direction.
1369 * This will be indicated in the bank toggle_mask.
1371 if (bank->toggle_mask & (1 << gpio_index))
1372 _toggle_gpio_edge_triggering(bank, gpio_index);
1375 generic_handle_irq(gpio_irq);
1378 /* if bank has any level sensitive GPIO pin interrupt
1379 configured, we must unmask the bank interrupt only after
1380 handler(s) are executed in order to avoid spurious bank
1384 desc->chip->unmask(irq);
1388 static void gpio_irq_shutdown(unsigned int irq)
1390 unsigned int gpio = irq - IH_GPIO_BASE;
1391 struct gpio_bank *bank = get_irq_chip_data(irq);
1393 _reset_gpio(bank, gpio);
1396 static void gpio_ack_irq(unsigned int irq)
1398 unsigned int gpio = irq - IH_GPIO_BASE;
1399 struct gpio_bank *bank = get_irq_chip_data(irq);
1401 _clear_gpio_irqstatus(bank, gpio);
1404 static void gpio_mask_irq(unsigned int irq)
1406 unsigned int gpio = irq - IH_GPIO_BASE;
1407 struct gpio_bank *bank = get_irq_chip_data(irq);
1409 _set_gpio_irqenable(bank, gpio, 0);
1410 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1413 static void gpio_unmask_irq(unsigned int irq)
1415 unsigned int gpio = irq - IH_GPIO_BASE;
1416 struct gpio_bank *bank = get_irq_chip_data(irq);
1417 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1418 struct irq_desc *desc = irq_to_desc(irq);
1419 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1422 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1424 /* For level-triggered GPIOs, the clearing must be done after
1425 * the HW source is cleared, thus after the handler has run */
1426 if (bank->level_mask & irq_mask) {
1427 _set_gpio_irqenable(bank, gpio, 0);
1428 _clear_gpio_irqstatus(bank, gpio);
1431 _set_gpio_irqenable(bank, gpio, 1);
1434 static struct irq_chip gpio_irq_chip = {
1436 .shutdown = gpio_irq_shutdown,
1437 .ack = gpio_ack_irq,
1438 .mask = gpio_mask_irq,
1439 .unmask = gpio_unmask_irq,
1440 .set_type = gpio_irq_type,
1441 .set_wake = gpio_wake_enable,
1444 /*---------------------------------------------------------------------*/
1446 #ifdef CONFIG_ARCH_OMAP1
1448 /* MPUIO uses the always-on 32k clock */
1450 static void mpuio_ack_irq(unsigned int irq)
1452 /* The ISR is reset automatically, so do nothing here. */
1455 static void mpuio_mask_irq(unsigned int irq)
1457 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1458 struct gpio_bank *bank = get_irq_chip_data(irq);
1460 _set_gpio_irqenable(bank, gpio, 0);
1463 static void mpuio_unmask_irq(unsigned int irq)
1465 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1466 struct gpio_bank *bank = get_irq_chip_data(irq);
1468 _set_gpio_irqenable(bank, gpio, 1);
1471 static struct irq_chip mpuio_irq_chip = {
1473 .ack = mpuio_ack_irq,
1474 .mask = mpuio_mask_irq,
1475 .unmask = mpuio_unmask_irq,
1476 .set_type = gpio_irq_type,
1477 #ifdef CONFIG_ARCH_OMAP16XX
1478 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1479 .set_wake = gpio_wake_enable,
1484 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1487 #ifdef CONFIG_ARCH_OMAP16XX
1489 #include <linux/platform_device.h>
1491 static int omap_mpuio_suspend_noirq(struct device *dev)
1493 struct platform_device *pdev = to_platform_device(dev);
1494 struct gpio_bank *bank = platform_get_drvdata(pdev);
1495 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1496 unsigned long flags;
1498 spin_lock_irqsave(&bank->lock, flags);
1499 bank->saved_wakeup = __raw_readl(mask_reg);
1500 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1501 spin_unlock_irqrestore(&bank->lock, flags);
1506 static int omap_mpuio_resume_noirq(struct device *dev)
1508 struct platform_device *pdev = to_platform_device(dev);
1509 struct gpio_bank *bank = platform_get_drvdata(pdev);
1510 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1511 unsigned long flags;
1513 spin_lock_irqsave(&bank->lock, flags);
1514 __raw_writel(bank->saved_wakeup, mask_reg);
1515 spin_unlock_irqrestore(&bank->lock, flags);
1520 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1521 .suspend_noirq = omap_mpuio_suspend_noirq,
1522 .resume_noirq = omap_mpuio_resume_noirq,
1525 /* use platform_driver for this, now that there's no longer any
1526 * point to sys_device (other than not disturbing old code).
1528 static struct platform_driver omap_mpuio_driver = {
1531 .pm = &omap_mpuio_dev_pm_ops,
1535 static struct platform_device omap_mpuio_device = {
1539 .driver = &omap_mpuio_driver.driver,
1541 /* could list the /proc/iomem resources */
1544 static inline void mpuio_init(void)
1546 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1548 if (platform_driver_register(&omap_mpuio_driver) == 0)
1549 (void) platform_device_register(&omap_mpuio_device);
1553 static inline void mpuio_init(void) {}
1558 extern struct irq_chip mpuio_irq_chip;
1560 #define bank_is_mpuio(bank) 0
1561 static inline void mpuio_init(void) {}
1565 /*---------------------------------------------------------------------*/
1567 /* REVISIT these are stupid implementations! replace by ones that
1568 * don't switch on METHOD_* and which mostly avoid spinlocks
1571 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1573 struct gpio_bank *bank;
1574 unsigned long flags;
1576 bank = container_of(chip, struct gpio_bank, chip);
1577 spin_lock_irqsave(&bank->lock, flags);
1578 _set_gpio_direction(bank, offset, 1);
1579 spin_unlock_irqrestore(&bank->lock, flags);
1583 static int gpio_is_input(struct gpio_bank *bank, int mask)
1585 void __iomem *reg = bank->base;
1587 switch (bank->method) {
1589 reg += OMAP_MPUIO_IO_CNTL;
1591 case METHOD_GPIO_1510:
1592 reg += OMAP1510_GPIO_DIR_CONTROL;
1594 case METHOD_GPIO_1610:
1595 reg += OMAP1610_GPIO_DIRECTION;
1597 case METHOD_GPIO_7XX:
1598 reg += OMAP7XX_GPIO_DIR_CONTROL;
1600 case METHOD_GPIO_24XX:
1601 reg += OMAP24XX_GPIO_OE;
1603 case METHOD_GPIO_44XX:
1604 reg += OMAP4_GPIO_OE;
1607 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1610 return __raw_readl(reg) & mask;
1613 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1615 struct gpio_bank *bank;
1620 gpio = chip->base + offset;
1621 bank = get_gpio_bank(gpio);
1623 mask = 1 << get_gpio_index(gpio);
1625 if (gpio_is_input(bank, mask))
1626 return _get_gpio_datain(bank, gpio);
1628 return _get_gpio_dataout(bank, gpio);
1631 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1633 struct gpio_bank *bank;
1634 unsigned long flags;
1636 bank = container_of(chip, struct gpio_bank, chip);
1637 spin_lock_irqsave(&bank->lock, flags);
1638 _set_gpio_dataout(bank, offset, value);
1639 _set_gpio_direction(bank, offset, 0);
1640 spin_unlock_irqrestore(&bank->lock, flags);
1644 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1647 struct gpio_bank *bank;
1648 unsigned long flags;
1650 bank = container_of(chip, struct gpio_bank, chip);
1651 spin_lock_irqsave(&bank->lock, flags);
1652 _set_gpio_debounce(bank, offset, debounce);
1653 spin_unlock_irqrestore(&bank->lock, flags);
1658 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1660 struct gpio_bank *bank;
1661 unsigned long flags;
1663 bank = container_of(chip, struct gpio_bank, chip);
1664 spin_lock_irqsave(&bank->lock, flags);
1665 _set_gpio_dataout(bank, offset, value);
1666 spin_unlock_irqrestore(&bank->lock, flags);
1669 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1671 struct gpio_bank *bank;
1673 bank = container_of(chip, struct gpio_bank, chip);
1674 return bank->virtual_irq_start + offset;
1677 /*---------------------------------------------------------------------*/
1679 static int initialized;
1680 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1681 static struct clk * gpio_ick;
1684 #if defined(CONFIG_ARCH_OMAP2)
1685 static struct clk * gpio_fck;
1688 #if defined(CONFIG_ARCH_OMAP2430)
1689 static struct clk * gpio5_ick;
1690 static struct clk * gpio5_fck;
1693 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1694 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1697 static void __init omap_gpio_show_rev(void)
1701 if (cpu_is_omap16xx())
1702 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1703 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1704 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1705 else if (cpu_is_omap44xx())
1706 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1710 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1711 (rev >> 4) & 0x0f, rev & 0x0f);
1714 /* This lock class tells lockdep that GPIO irqs are in a different
1715 * category than their parents, so it won't report false recursion.
1717 static struct lock_class_key gpio_lock_class;
1719 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1721 if (cpu_class_is_omap2()) {
1722 if (cpu_is_omap44xx()) {
1723 __raw_writel(0xffffffff, bank->base +
1724 OMAP4_GPIO_IRQSTATUSCLR0);
1725 __raw_writel(0x00000000, bank->base +
1726 OMAP4_GPIO_DEBOUNCENABLE);
1727 /* Initialize interface clk ungated, module enabled */
1728 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1729 } else if (cpu_is_omap34xx()) {
1730 __raw_writel(0x00000000, bank->base +
1731 OMAP24XX_GPIO_IRQENABLE1);
1732 __raw_writel(0xffffffff, bank->base +
1733 OMAP24XX_GPIO_IRQSTATUS1);
1734 __raw_writel(0x00000000, bank->base +
1735 OMAP24XX_GPIO_DEBOUNCE_EN);
1737 /* Initialize interface clk ungated, module enabled */
1738 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1739 } else if (cpu_is_omap24xx()) {
1740 static const u32 non_wakeup_gpios[] = {
1741 0xe203ffc0, 0x08700040
1743 if (id < ARRAY_SIZE(non_wakeup_gpios))
1744 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1746 } else if (cpu_class_is_omap1()) {
1747 if (bank_is_mpuio(bank))
1748 __raw_writew(0xffff, bank->base
1749 + OMAP_MPUIO_GPIO_MASKIT);
1750 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1751 __raw_writew(0xffff, bank->base
1752 + OMAP1510_GPIO_INT_MASK);
1753 __raw_writew(0x0000, bank->base
1754 + OMAP1510_GPIO_INT_STATUS);
1756 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1757 __raw_writew(0x0000, bank->base
1758 + OMAP1610_GPIO_IRQENABLE1);
1759 __raw_writew(0xffff, bank->base
1760 + OMAP1610_GPIO_IRQSTATUS1);
1761 __raw_writew(0x0014, bank->base
1762 + OMAP1610_GPIO_SYSCONFIG);
1765 * Enable system clock for GPIO module.
1766 * The CAM_CLK_CTRL *is* really the right place.
1768 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1771 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1772 __raw_writel(0xffffffff, bank->base
1773 + OMAP7XX_GPIO_INT_MASK);
1774 __raw_writel(0x00000000, bank->base
1775 + OMAP7XX_GPIO_INT_STATUS);
1780 static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1782 int j, bank_width = 16;
1785 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX)
1786 bank_width = 32; /* 7xx has 32-bit GPIOs */
1788 if ((bank->method == METHOD_GPIO_24XX) ||
1789 (bank->method == METHOD_GPIO_44XX))
1792 bank->mod_usage = 0;
1794 * REVISIT eventually switch from OMAP-specific gpio structs
1795 * over to the generic ones
1797 bank->chip.request = omap_gpio_request;
1798 bank->chip.free = omap_gpio_free;
1799 bank->chip.direction_input = gpio_input;
1800 bank->chip.get = gpio_get;
1801 bank->chip.direction_output = gpio_output;
1802 bank->chip.set_debounce = gpio_debounce;
1803 bank->chip.set = gpio_set;
1804 bank->chip.to_irq = gpio_2irq;
1805 if (bank_is_mpuio(bank)) {
1806 bank->chip.label = "mpuio";
1807 #ifdef CONFIG_ARCH_OMAP16XX
1808 bank->chip.dev = &omap_mpuio_device.dev;
1810 bank->chip.base = OMAP_MPUIO(0);
1812 bank->chip.label = "gpio";
1813 bank->chip.base = gpio;
1816 bank->chip.ngpio = bank_width;
1818 gpiochip_add(&bank->chip);
1820 for (j = bank->virtual_irq_start;
1821 j < bank->virtual_irq_start + bank_width; j++) {
1822 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1823 set_irq_chip_data(j, bank);
1824 if (bank_is_mpuio(bank))
1825 set_irq_chip(j, &mpuio_irq_chip);
1827 set_irq_chip(j, &gpio_irq_chip);
1828 set_irq_handler(j, handle_simple_irq);
1829 set_irq_flags(j, IRQF_VALID);
1831 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1832 set_irq_data(bank->irq, bank);
1835 static int __init _omap_gpio_init(void)
1838 struct gpio_bank *bank;
1839 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1844 #if defined(CONFIG_ARCH_OMAP1)
1845 if (cpu_is_omap15xx()) {
1846 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1847 if (IS_ERR(gpio_ick))
1848 printk("Could not get arm_gpio_ck\n");
1850 clk_enable(gpio_ick);
1853 #if defined(CONFIG_ARCH_OMAP2)
1854 if (cpu_class_is_omap2()) {
1855 gpio_ick = clk_get(NULL, "gpios_ick");
1856 if (IS_ERR(gpio_ick))
1857 printk("Could not get gpios_ick\n");
1859 clk_enable(gpio_ick);
1860 gpio_fck = clk_get(NULL, "gpios_fck");
1861 if (IS_ERR(gpio_fck))
1862 printk("Could not get gpios_fck\n");
1864 clk_enable(gpio_fck);
1867 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1869 #if defined(CONFIG_ARCH_OMAP2430)
1870 if (cpu_is_omap2430()) {
1871 gpio5_ick = clk_get(NULL, "gpio5_ick");
1872 if (IS_ERR(gpio5_ick))
1873 printk("Could not get gpio5_ick\n");
1875 clk_enable(gpio5_ick);
1876 gpio5_fck = clk_get(NULL, "gpio5_fck");
1877 if (IS_ERR(gpio5_fck))
1878 printk("Could not get gpio5_fck\n");
1880 clk_enable(gpio5_fck);
1886 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1887 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1888 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1889 sprintf(clk_name, "gpio%d_ick", i + 1);
1890 gpio_iclks[i] = clk_get(NULL, clk_name);
1891 if (IS_ERR(gpio_iclks[i]))
1892 printk(KERN_ERR "Could not get %s\n", clk_name);
1894 clk_enable(gpio_iclks[i]);
1900 #ifdef CONFIG_ARCH_OMAP15XX
1901 if (cpu_is_omap15xx()) {
1902 gpio_bank_count = 2;
1903 gpio_bank = gpio_bank_1510;
1907 #if defined(CONFIG_ARCH_OMAP16XX)
1908 if (cpu_is_omap16xx()) {
1909 gpio_bank_count = 5;
1910 gpio_bank = gpio_bank_1610;
1914 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1915 if (cpu_is_omap7xx()) {
1916 gpio_bank_count = 7;
1917 gpio_bank = gpio_bank_7xx;
1921 #ifdef CONFIG_ARCH_OMAP2
1922 if (cpu_is_omap242x()) {
1923 gpio_bank_count = 4;
1924 gpio_bank = gpio_bank_242x;
1926 if (cpu_is_omap243x()) {
1927 gpio_bank_count = 5;
1928 gpio_bank = gpio_bank_243x;
1931 #ifdef CONFIG_ARCH_OMAP3
1932 if (cpu_is_omap34xx()) {
1933 gpio_bank_count = OMAP34XX_NR_GPIOS;
1934 gpio_bank = gpio_bank_34xx;
1937 #ifdef CONFIG_ARCH_OMAP4
1938 if (cpu_is_omap44xx()) {
1939 gpio_bank_count = OMAP34XX_NR_GPIOS;
1940 gpio_bank = gpio_bank_44xx;
1943 for (i = 0; i < gpio_bank_count; i++) {
1945 bank = &gpio_bank[i];
1946 spin_lock_init(&bank->lock);
1948 /* Static mapping, never released */
1949 bank->base = ioremap(bank->pbase, bank_size);
1951 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1955 omap_gpio_mod_init(bank, i);
1956 omap_gpio_chip_init(bank);
1958 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1959 sprintf(clk_name, "gpio%d_dbck", i + 1);
1960 bank->dbck = clk_get(NULL, clk_name);
1961 if (IS_ERR(bank->dbck))
1962 printk(KERN_ERR "Could not get %s\n", clk_name);
1966 omap_gpio_show_rev();
1971 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1972 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1976 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1979 for (i = 0; i < gpio_bank_count; i++) {
1980 struct gpio_bank *bank = &gpio_bank[i];
1981 void __iomem *wake_status;
1982 void __iomem *wake_clear;
1983 void __iomem *wake_set;
1984 unsigned long flags;
1986 switch (bank->method) {
1987 #ifdef CONFIG_ARCH_OMAP16XX
1988 case METHOD_GPIO_1610:
1989 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1990 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1991 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1994 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1995 case METHOD_GPIO_24XX:
1996 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1997 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1998 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
2001 #ifdef CONFIG_ARCH_OMAP4
2002 case METHOD_GPIO_44XX:
2003 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
2004 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2005 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2012 spin_lock_irqsave(&bank->lock, flags);
2013 bank->saved_wakeup = __raw_readl(wake_status);
2014 __raw_writel(0xffffffff, wake_clear);
2015 __raw_writel(bank->suspend_wakeup, wake_set);
2016 spin_unlock_irqrestore(&bank->lock, flags);
2022 static int omap_gpio_resume(struct sys_device *dev)
2026 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
2029 for (i = 0; i < gpio_bank_count; i++) {
2030 struct gpio_bank *bank = &gpio_bank[i];
2031 void __iomem *wake_clear;
2032 void __iomem *wake_set;
2033 unsigned long flags;
2035 switch (bank->method) {
2036 #ifdef CONFIG_ARCH_OMAP16XX
2037 case METHOD_GPIO_1610:
2038 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
2039 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
2042 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
2043 case METHOD_GPIO_24XX:
2044 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
2045 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
2048 #ifdef CONFIG_ARCH_OMAP4
2049 case METHOD_GPIO_44XX:
2050 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2051 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2058 spin_lock_irqsave(&bank->lock, flags);
2059 __raw_writel(0xffffffff, wake_clear);
2060 __raw_writel(bank->saved_wakeup, wake_set);
2061 spin_unlock_irqrestore(&bank->lock, flags);
2067 static struct sysdev_class omap_gpio_sysclass = {
2069 .suspend = omap_gpio_suspend,
2070 .resume = omap_gpio_resume,
2073 static struct sys_device omap_gpio_device = {
2075 .cls = &omap_gpio_sysclass,
2080 #ifdef CONFIG_ARCH_OMAP2PLUS
2082 static int workaround_enabled;
2084 void omap2_gpio_prepare_for_idle(int power_state)
2089 if (cpu_is_omap34xx())
2092 for (i = min; i < gpio_bank_count; i++) {
2093 struct gpio_bank *bank = &gpio_bank[i];
2097 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
2098 clk_disable(bank->dbck);
2100 if (power_state > PWRDM_POWER_OFF)
2103 /* If going to OFF, remove triggering for all
2104 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2105 * generated. See OMAP2420 Errata item 1.101. */
2106 if (!(bank->enabled_non_wakeup_gpios))
2109 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2110 bank->saved_datain = __raw_readl(bank->base +
2111 OMAP24XX_GPIO_DATAIN);
2112 l1 = __raw_readl(bank->base +
2113 OMAP24XX_GPIO_FALLINGDETECT);
2114 l2 = __raw_readl(bank->base +
2115 OMAP24XX_GPIO_RISINGDETECT);
2118 if (cpu_is_omap44xx()) {
2119 bank->saved_datain = __raw_readl(bank->base +
2121 l1 = __raw_readl(bank->base +
2122 OMAP4_GPIO_FALLINGDETECT);
2123 l2 = __raw_readl(bank->base +
2124 OMAP4_GPIO_RISINGDETECT);
2127 bank->saved_fallingdetect = l1;
2128 bank->saved_risingdetect = l2;
2129 l1 &= ~bank->enabled_non_wakeup_gpios;
2130 l2 &= ~bank->enabled_non_wakeup_gpios;
2132 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2133 __raw_writel(l1, bank->base +
2134 OMAP24XX_GPIO_FALLINGDETECT);
2135 __raw_writel(l2, bank->base +
2136 OMAP24XX_GPIO_RISINGDETECT);
2139 if (cpu_is_omap44xx()) {
2140 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2141 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2147 workaround_enabled = 0;
2150 workaround_enabled = 1;
2153 void omap2_gpio_resume_after_idle(void)
2158 if (cpu_is_omap34xx())
2160 for (i = min; i < gpio_bank_count; i++) {
2161 struct gpio_bank *bank = &gpio_bank[i];
2162 u32 l = 0, gen, gen0, gen1;
2165 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
2166 clk_enable(bank->dbck);
2168 if (!workaround_enabled)
2171 if (!(bank->enabled_non_wakeup_gpios))
2174 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2175 __raw_writel(bank->saved_fallingdetect,
2176 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2177 __raw_writel(bank->saved_risingdetect,
2178 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2179 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2182 if (cpu_is_omap44xx()) {
2183 __raw_writel(bank->saved_fallingdetect,
2184 bank->base + OMAP4_GPIO_FALLINGDETECT);
2185 __raw_writel(bank->saved_risingdetect,
2186 bank->base + OMAP4_GPIO_RISINGDETECT);
2187 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2190 /* Check if any of the non-wakeup interrupt GPIOs have changed
2191 * state. If so, generate an IRQ by software. This is
2192 * horribly racy, but it's the best we can do to work around
2193 * this silicon bug. */
2194 l ^= bank->saved_datain;
2195 l &= bank->enabled_non_wakeup_gpios;
2198 * No need to generate IRQs for the rising edge for gpio IRQs
2199 * configured with falling edge only; and vice versa.
2201 gen0 = l & bank->saved_fallingdetect;
2202 gen0 &= bank->saved_datain;
2204 gen1 = l & bank->saved_risingdetect;
2205 gen1 &= ~(bank->saved_datain);
2207 /* FIXME: Consider GPIO IRQs with level detections properly! */
2208 gen = l & (~(bank->saved_fallingdetect) &
2209 ~(bank->saved_risingdetect));
2210 /* Consider all GPIO IRQs needed to be updated */
2216 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2217 old0 = __raw_readl(bank->base +
2218 OMAP24XX_GPIO_LEVELDETECT0);
2219 old1 = __raw_readl(bank->base +
2220 OMAP24XX_GPIO_LEVELDETECT1);
2221 __raw_writel(old0 | gen, bank->base +
2222 OMAP24XX_GPIO_LEVELDETECT0);
2223 __raw_writel(old1 | gen, bank->base +
2224 OMAP24XX_GPIO_LEVELDETECT1);
2225 __raw_writel(old0, bank->base +
2226 OMAP24XX_GPIO_LEVELDETECT0);
2227 __raw_writel(old1, bank->base +
2228 OMAP24XX_GPIO_LEVELDETECT1);
2231 if (cpu_is_omap44xx()) {
2232 old0 = __raw_readl(bank->base +
2233 OMAP4_GPIO_LEVELDETECT0);
2234 old1 = __raw_readl(bank->base +
2235 OMAP4_GPIO_LEVELDETECT1);
2236 __raw_writel(old0 | l, bank->base +
2237 OMAP4_GPIO_LEVELDETECT0);
2238 __raw_writel(old1 | l, bank->base +
2239 OMAP4_GPIO_LEVELDETECT1);
2240 __raw_writel(old0, bank->base +
2241 OMAP4_GPIO_LEVELDETECT0);
2242 __raw_writel(old1, bank->base +
2243 OMAP4_GPIO_LEVELDETECT1);
2252 #ifdef CONFIG_ARCH_OMAP3
2253 /* save the registers of bank 2-6 */
2254 void omap_gpio_save_context(void)
2258 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2259 for (i = 1; i < gpio_bank_count; i++) {
2260 struct gpio_bank *bank = &gpio_bank[i];
2261 gpio_context[i].sysconfig =
2262 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2263 gpio_context[i].irqenable1 =
2264 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2265 gpio_context[i].irqenable2 =
2266 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2267 gpio_context[i].wake_en =
2268 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2269 gpio_context[i].ctrl =
2270 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2271 gpio_context[i].oe =
2272 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2273 gpio_context[i].leveldetect0 =
2274 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2275 gpio_context[i].leveldetect1 =
2276 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2277 gpio_context[i].risingdetect =
2278 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2279 gpio_context[i].fallingdetect =
2280 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2281 gpio_context[i].dataout =
2282 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2286 /* restore the required registers of bank 2-6 */
2287 void omap_gpio_restore_context(void)
2291 for (i = 1; i < gpio_bank_count; i++) {
2292 struct gpio_bank *bank = &gpio_bank[i];
2293 __raw_writel(gpio_context[i].sysconfig,
2294 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2295 __raw_writel(gpio_context[i].irqenable1,
2296 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2297 __raw_writel(gpio_context[i].irqenable2,
2298 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2299 __raw_writel(gpio_context[i].wake_en,
2300 bank->base + OMAP24XX_GPIO_WAKE_EN);
2301 __raw_writel(gpio_context[i].ctrl,
2302 bank->base + OMAP24XX_GPIO_CTRL);
2303 __raw_writel(gpio_context[i].oe,
2304 bank->base + OMAP24XX_GPIO_OE);
2305 __raw_writel(gpio_context[i].leveldetect0,
2306 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2307 __raw_writel(gpio_context[i].leveldetect1,
2308 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2309 __raw_writel(gpio_context[i].risingdetect,
2310 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2311 __raw_writel(gpio_context[i].fallingdetect,
2312 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2313 __raw_writel(gpio_context[i].dataout,
2314 bank->base + OMAP24XX_GPIO_DATAOUT);
2320 * This may get called early from board specific init
2321 * for boards that have interrupts routed via FPGA.
2323 int __init omap_gpio_init(void)
2326 return _omap_gpio_init();
2331 static int __init omap_gpio_sysinit(void)
2336 ret = _omap_gpio_init();
2340 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2341 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2343 ret = sysdev_class_register(&omap_gpio_sysclass);
2345 ret = sysdev_register(&omap_gpio_device);
2353 arch_initcall(omap_gpio_sysinit);