2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * omap24xx specific GPIO registers
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_WAKE_EN 0x0020
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
133 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
138 u16 virtual_irq_start;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
154 struct gpio_chip chip;
158 #define METHOD_MPUIO 0
159 #define METHOD_GPIO_1510 1
160 #define METHOD_GPIO_1610 2
161 #define METHOD_GPIO_730 3
162 #define METHOD_GPIO_24XX 4
164 #ifdef CONFIG_ARCH_OMAP16XX
165 static struct gpio_bank gpio_bank_1610[5] = {
166 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
167 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
170 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
174 #ifdef CONFIG_ARCH_OMAP15XX
175 static struct gpio_bank gpio_bank_1510[2] = {
176 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
177 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
181 #ifdef CONFIG_ARCH_OMAP730
182 static struct gpio_bank gpio_bank_730[7] = {
183 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
184 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
185 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
186 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
187 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
188 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
189 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
193 #ifdef CONFIG_ARCH_OMAP24XX
195 static struct gpio_bank gpio_bank_242x[4] = {
196 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
199 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
202 static struct gpio_bank gpio_bank_243x[5] = {
203 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
207 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
212 #ifdef CONFIG_ARCH_OMAP34XX
213 static struct gpio_bank gpio_bank_34xx[6] = {
214 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
219 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
224 static struct gpio_bank *gpio_bank;
225 static int gpio_bank_count;
227 static inline struct gpio_bank *get_gpio_bank(int gpio)
229 if (cpu_is_omap15xx()) {
230 if (OMAP_GPIO_IS_MPUIO(gpio))
231 return &gpio_bank[0];
232 return &gpio_bank[1];
234 if (cpu_is_omap16xx()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio))
236 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 4)];
239 if (cpu_is_omap730()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio))
241 return &gpio_bank[0];
242 return &gpio_bank[1 + (gpio >> 5)];
244 if (cpu_is_omap24xx())
245 return &gpio_bank[gpio >> 5];
246 if (cpu_is_omap34xx())
247 return &gpio_bank[gpio >> 5];
250 static inline int get_gpio_index(int gpio)
252 if (cpu_is_omap730())
254 if (cpu_is_omap24xx())
256 if (cpu_is_omap34xx())
261 static inline int gpio_valid(int gpio)
265 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
266 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
270 if (cpu_is_omap15xx() && gpio < 16)
272 if ((cpu_is_omap16xx()) && gpio < 64)
274 if (cpu_is_omap730() && gpio < 192)
276 if (cpu_is_omap24xx() && gpio < 128)
278 if (cpu_is_omap34xx() && gpio < 160)
283 static int check_gpio(int gpio)
285 if (unlikely(gpio_valid(gpio)) < 0) {
286 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
293 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
295 void __iomem *reg = bank->base;
298 switch (bank->method) {
299 #ifdef CONFIG_ARCH_OMAP1
301 reg += OMAP_MPUIO_IO_CNTL;
304 #ifdef CONFIG_ARCH_OMAP15XX
305 case METHOD_GPIO_1510:
306 reg += OMAP1510_GPIO_DIR_CONTROL;
309 #ifdef CONFIG_ARCH_OMAP16XX
310 case METHOD_GPIO_1610:
311 reg += OMAP1610_GPIO_DIRECTION;
314 #ifdef CONFIG_ARCH_OMAP730
315 case METHOD_GPIO_730:
316 reg += OMAP730_GPIO_DIR_CONTROL;
319 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
320 case METHOD_GPIO_24XX:
321 reg += OMAP24XX_GPIO_OE;
328 l = __raw_readl(reg);
333 __raw_writel(l, reg);
336 void omap_set_gpio_direction(int gpio, int is_input)
338 struct gpio_bank *bank;
341 if (check_gpio(gpio) < 0)
343 bank = get_gpio_bank(gpio);
344 spin_lock_irqsave(&bank->lock, flags);
345 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
346 spin_unlock_irqrestore(&bank->lock, flags);
349 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
351 void __iomem *reg = bank->base;
354 switch (bank->method) {
355 #ifdef CONFIG_ARCH_OMAP1
357 reg += OMAP_MPUIO_OUTPUT;
358 l = __raw_readl(reg);
365 #ifdef CONFIG_ARCH_OMAP15XX
366 case METHOD_GPIO_1510:
367 reg += OMAP1510_GPIO_DATA_OUTPUT;
368 l = __raw_readl(reg);
375 #ifdef CONFIG_ARCH_OMAP16XX
376 case METHOD_GPIO_1610:
378 reg += OMAP1610_GPIO_SET_DATAOUT;
380 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
384 #ifdef CONFIG_ARCH_OMAP730
385 case METHOD_GPIO_730:
386 reg += OMAP730_GPIO_DATA_OUTPUT;
387 l = __raw_readl(reg);
394 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
395 case METHOD_GPIO_24XX:
397 reg += OMAP24XX_GPIO_SETDATAOUT;
399 reg += OMAP24XX_GPIO_CLEARDATAOUT;
407 __raw_writel(l, reg);
410 static int __omap_get_gpio_datain(int gpio)
412 struct gpio_bank *bank;
415 if (check_gpio(gpio) < 0)
417 bank = get_gpio_bank(gpio);
419 switch (bank->method) {
420 #ifdef CONFIG_ARCH_OMAP1
422 reg += OMAP_MPUIO_INPUT_LATCH;
425 #ifdef CONFIG_ARCH_OMAP15XX
426 case METHOD_GPIO_1510:
427 reg += OMAP1510_GPIO_DATA_INPUT;
430 #ifdef CONFIG_ARCH_OMAP16XX
431 case METHOD_GPIO_1610:
432 reg += OMAP1610_GPIO_DATAIN;
435 #ifdef CONFIG_ARCH_OMAP730
436 case METHOD_GPIO_730:
437 reg += OMAP730_GPIO_DATA_INPUT;
440 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
441 case METHOD_GPIO_24XX:
442 reg += OMAP24XX_GPIO_DATAIN;
448 return (__raw_readl(reg)
449 & (1 << get_gpio_index(gpio))) != 0;
452 #define MOD_REG_BIT(reg, bit_mask, set) \
454 int l = __raw_readl(base + reg); \
455 if (set) l |= bit_mask; \
456 else l &= ~bit_mask; \
457 __raw_writel(l, base + reg); \
460 void omap_set_gpio_debounce(int gpio, int enable)
462 struct gpio_bank *bank;
464 u32 val, l = 1 << get_gpio_index(gpio);
466 if (cpu_class_is_omap1())
469 bank = get_gpio_bank(gpio);
472 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
473 val = __raw_readl(reg);
475 if (enable && !(val & l))
477 else if (!enable && val & l)
482 if (cpu_is_omap34xx())
483 enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
485 __raw_writel(val, reg);
487 EXPORT_SYMBOL(omap_set_gpio_debounce);
489 void omap_set_gpio_debounce_time(int gpio, int enc_time)
491 struct gpio_bank *bank;
494 if (cpu_class_is_omap1())
497 bank = get_gpio_bank(gpio);
501 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
502 __raw_writel(enc_time, reg);
504 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
506 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
507 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
510 void __iomem *base = bank->base;
511 u32 gpio_bit = 1 << gpio;
513 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
514 trigger & IRQ_TYPE_LEVEL_LOW);
515 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
516 trigger & IRQ_TYPE_LEVEL_HIGH);
517 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
518 trigger & IRQ_TYPE_EDGE_RISING);
519 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
520 trigger & IRQ_TYPE_EDGE_FALLING);
522 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
524 __raw_writel(1 << gpio, bank->base
525 + OMAP24XX_GPIO_SETWKUENA);
527 __raw_writel(1 << gpio, bank->base
528 + OMAP24XX_GPIO_CLEARWKUENA);
531 bank->enabled_non_wakeup_gpios |= gpio_bit;
533 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
537 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
538 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
542 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
544 void __iomem *reg = bank->base;
547 switch (bank->method) {
548 #ifdef CONFIG_ARCH_OMAP1
550 reg += OMAP_MPUIO_GPIO_INT_EDGE;
551 l = __raw_readl(reg);
552 if (trigger & IRQ_TYPE_EDGE_RISING)
554 else if (trigger & IRQ_TYPE_EDGE_FALLING)
560 #ifdef CONFIG_ARCH_OMAP15XX
561 case METHOD_GPIO_1510:
562 reg += OMAP1510_GPIO_INT_CONTROL;
563 l = __raw_readl(reg);
564 if (trigger & IRQ_TYPE_EDGE_RISING)
566 else if (trigger & IRQ_TYPE_EDGE_FALLING)
572 #ifdef CONFIG_ARCH_OMAP16XX
573 case METHOD_GPIO_1610:
575 reg += OMAP1610_GPIO_EDGE_CTRL2;
577 reg += OMAP1610_GPIO_EDGE_CTRL1;
579 l = __raw_readl(reg);
580 l &= ~(3 << (gpio << 1));
581 if (trigger & IRQ_TYPE_EDGE_RISING)
582 l |= 2 << (gpio << 1);
583 if (trigger & IRQ_TYPE_EDGE_FALLING)
584 l |= 1 << (gpio << 1);
586 /* Enable wake-up during idle for dynamic tick */
587 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
589 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
592 #ifdef CONFIG_ARCH_OMAP730
593 case METHOD_GPIO_730:
594 reg += OMAP730_GPIO_INT_CONTROL;
595 l = __raw_readl(reg);
596 if (trigger & IRQ_TYPE_EDGE_RISING)
598 else if (trigger & IRQ_TYPE_EDGE_FALLING)
604 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
605 case METHOD_GPIO_24XX:
606 set_24xx_gpio_triggering(bank, gpio, trigger);
612 __raw_writel(l, reg);
618 static int gpio_irq_type(unsigned irq, unsigned type)
620 struct gpio_bank *bank;
625 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
626 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
628 gpio = irq - IH_GPIO_BASE;
630 if (check_gpio(gpio) < 0)
633 if (type & ~IRQ_TYPE_SENSE_MASK)
636 /* OMAP1 allows only only edge triggering */
637 if (!cpu_class_is_omap2()
638 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
641 bank = get_irq_chip_data(irq);
642 spin_lock_irqsave(&bank->lock, flags);
643 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
645 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
646 irq_desc[irq].status |= type;
648 spin_unlock_irqrestore(&bank->lock, flags);
650 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
651 __set_irq_handler_unlocked(irq, handle_level_irq);
652 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
653 __set_irq_handler_unlocked(irq, handle_edge_irq);
658 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
660 void __iomem *reg = bank->base;
662 switch (bank->method) {
663 #ifdef CONFIG_ARCH_OMAP1
665 /* MPUIO irqstatus is reset by reading the status register,
666 * so do nothing here */
669 #ifdef CONFIG_ARCH_OMAP15XX
670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_STATUS;
674 #ifdef CONFIG_ARCH_OMAP16XX
675 case METHOD_GPIO_1610:
676 reg += OMAP1610_GPIO_IRQSTATUS1;
679 #ifdef CONFIG_ARCH_OMAP730
680 case METHOD_GPIO_730:
681 reg += OMAP730_GPIO_INT_STATUS;
684 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
685 case METHOD_GPIO_24XX:
686 reg += OMAP24XX_GPIO_IRQSTATUS1;
693 __raw_writel(gpio_mask, reg);
695 /* Workaround for clearing DSP GPIO interrupts to allow retention */
696 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
697 if (cpu_is_omap24xx() || cpu_is_omap34xx())
698 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
702 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
704 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
707 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
709 void __iomem *reg = bank->base;
714 switch (bank->method) {
715 #ifdef CONFIG_ARCH_OMAP1
717 reg += OMAP_MPUIO_GPIO_MASKIT;
722 #ifdef CONFIG_ARCH_OMAP15XX
723 case METHOD_GPIO_1510:
724 reg += OMAP1510_GPIO_INT_MASK;
729 #ifdef CONFIG_ARCH_OMAP16XX
730 case METHOD_GPIO_1610:
731 reg += OMAP1610_GPIO_IRQENABLE1;
735 #ifdef CONFIG_ARCH_OMAP730
736 case METHOD_GPIO_730:
737 reg += OMAP730_GPIO_INT_MASK;
742 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
743 case METHOD_GPIO_24XX:
744 reg += OMAP24XX_GPIO_IRQENABLE1;
753 l = __raw_readl(reg);
760 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
762 void __iomem *reg = bank->base;
765 switch (bank->method) {
766 #ifdef CONFIG_ARCH_OMAP1
768 reg += OMAP_MPUIO_GPIO_MASKIT;
769 l = __raw_readl(reg);
776 #ifdef CONFIG_ARCH_OMAP15XX
777 case METHOD_GPIO_1510:
778 reg += OMAP1510_GPIO_INT_MASK;
779 l = __raw_readl(reg);
786 #ifdef CONFIG_ARCH_OMAP16XX
787 case METHOD_GPIO_1610:
789 reg += OMAP1610_GPIO_SET_IRQENABLE1;
791 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
795 #ifdef CONFIG_ARCH_OMAP730
796 case METHOD_GPIO_730:
797 reg += OMAP730_GPIO_INT_MASK;
798 l = __raw_readl(reg);
805 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
806 case METHOD_GPIO_24XX:
808 reg += OMAP24XX_GPIO_SETIRQENABLE1;
810 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
818 __raw_writel(l, reg);
821 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
823 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
827 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
828 * 1510 does not seem to have a wake-up register. If JTAG is connected
829 * to the target, system will wake up always on GPIO events. While
830 * system is running all registered GPIO interrupts need to have wake-up
831 * enabled. When system is suspended, only selected GPIO interrupts need
832 * to have wake-up enabled.
834 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
838 switch (bank->method) {
839 #ifdef CONFIG_ARCH_OMAP16XX
841 case METHOD_GPIO_1610:
842 spin_lock_irqsave(&bank->lock, flags);
844 bank->suspend_wakeup |= (1 << gpio);
845 enable_irq_wake(bank->irq);
847 disable_irq_wake(bank->irq);
848 bank->suspend_wakeup &= ~(1 << gpio);
850 spin_unlock_irqrestore(&bank->lock, flags);
853 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
854 case METHOD_GPIO_24XX:
855 if (bank->non_wakeup_gpios & (1 << gpio)) {
856 printk(KERN_ERR "Unable to modify wakeup on "
857 "non-wakeup GPIO%d\n",
858 (bank - gpio_bank) * 32 + gpio);
861 spin_lock_irqsave(&bank->lock, flags);
863 bank->suspend_wakeup |= (1 << gpio);
864 enable_irq_wake(bank->irq);
866 disable_irq_wake(bank->irq);
867 bank->suspend_wakeup &= ~(1 << gpio);
869 spin_unlock_irqrestore(&bank->lock, flags);
873 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
879 static void _reset_gpio(struct gpio_bank *bank, int gpio)
881 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
882 _set_gpio_irqenable(bank, gpio, 0);
883 _clear_gpio_irqstatus(bank, gpio);
884 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
887 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
888 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
890 unsigned int gpio = irq - IH_GPIO_BASE;
891 struct gpio_bank *bank;
894 if (check_gpio(gpio) < 0)
896 bank = get_irq_chip_data(irq);
897 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
902 int omap_request_gpio(int gpio)
904 struct gpio_bank *bank;
908 if (check_gpio(gpio) < 0)
911 status = gpio_request(gpio, NULL);
915 bank = get_gpio_bank(gpio);
916 spin_lock_irqsave(&bank->lock, flags);
918 /* Set trigger to none. You need to enable the desired trigger with
919 * request_irq() or set_irq_type().
921 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
923 #ifdef CONFIG_ARCH_OMAP15XX
924 if (bank->method == METHOD_GPIO_1510) {
927 /* Claim the pin for MPU */
928 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
929 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
932 spin_unlock_irqrestore(&bank->lock, flags);
937 void omap_free_gpio(int gpio)
939 struct gpio_bank *bank;
942 if (check_gpio(gpio) < 0)
944 bank = get_gpio_bank(gpio);
945 spin_lock_irqsave(&bank->lock, flags);
946 if (unlikely(!gpiochip_is_requested(&bank->chip,
947 get_gpio_index(gpio)))) {
948 spin_unlock_irqrestore(&bank->lock, flags);
949 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
953 #ifdef CONFIG_ARCH_OMAP16XX
954 if (bank->method == METHOD_GPIO_1610) {
955 /* Disable wake-up during idle for dynamic tick */
956 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
957 __raw_writel(1 << get_gpio_index(gpio), reg);
960 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
961 if (bank->method == METHOD_GPIO_24XX) {
962 /* Disable wake-up during idle for dynamic tick */
963 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
964 __raw_writel(1 << get_gpio_index(gpio), reg);
967 _reset_gpio(bank, gpio);
968 spin_unlock_irqrestore(&bank->lock, flags);
973 * We need to unmask the GPIO bank interrupt as soon as possible to
974 * avoid missing GPIO interrupts for other lines in the bank.
975 * Then we need to mask-read-clear-unmask the triggered GPIO lines
976 * in the bank to avoid missing nested interrupts for a GPIO line.
977 * If we wait to unmask individual GPIO lines in the bank after the
978 * line's interrupt handler has been run, we may miss some nested
981 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
983 void __iomem *isr_reg = NULL;
985 unsigned int gpio_irq;
986 struct gpio_bank *bank;
990 desc->chip->ack(irq);
992 bank = get_irq_data(irq);
993 #ifdef CONFIG_ARCH_OMAP1
994 if (bank->method == METHOD_MPUIO)
995 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
997 #ifdef CONFIG_ARCH_OMAP15XX
998 if (bank->method == METHOD_GPIO_1510)
999 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1001 #if defined(CONFIG_ARCH_OMAP16XX)
1002 if (bank->method == METHOD_GPIO_1610)
1003 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1005 #ifdef CONFIG_ARCH_OMAP730
1006 if (bank->method == METHOD_GPIO_730)
1007 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1009 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1010 if (bank->method == METHOD_GPIO_24XX)
1011 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1014 u32 isr_saved, level_mask = 0;
1017 enabled = _get_gpio_irqbank_mask(bank);
1018 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1020 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1023 if (cpu_class_is_omap2()) {
1024 level_mask = bank->level_mask & enabled;
1027 /* clear edge sensitive interrupts before handler(s) are
1028 called so that we don't miss any interrupt occurred while
1030 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1031 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1032 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1034 /* if there is only edge sensitive GPIO pin interrupts
1035 configured, we could unmask GPIO bank interrupt immediately */
1036 if (!level_mask && !unmasked) {
1038 desc->chip->unmask(irq);
1046 gpio_irq = bank->virtual_irq_start;
1047 for (; isr != 0; isr >>= 1, gpio_irq++) {
1051 generic_handle_irq(gpio_irq);
1054 /* if bank has any level sensitive GPIO pin interrupt
1055 configured, we must unmask the bank interrupt only after
1056 handler(s) are executed in order to avoid spurious bank
1059 desc->chip->unmask(irq);
1063 static void gpio_irq_shutdown(unsigned int irq)
1065 unsigned int gpio = irq - IH_GPIO_BASE;
1066 struct gpio_bank *bank = get_irq_chip_data(irq);
1068 _reset_gpio(bank, gpio);
1071 static void gpio_ack_irq(unsigned int irq)
1073 unsigned int gpio = irq - IH_GPIO_BASE;
1074 struct gpio_bank *bank = get_irq_chip_data(irq);
1076 _clear_gpio_irqstatus(bank, gpio);
1079 static void gpio_mask_irq(unsigned int irq)
1081 unsigned int gpio = irq - IH_GPIO_BASE;
1082 struct gpio_bank *bank = get_irq_chip_data(irq);
1084 _set_gpio_irqenable(bank, gpio, 0);
1087 static void gpio_unmask_irq(unsigned int irq)
1089 unsigned int gpio = irq - IH_GPIO_BASE;
1090 struct gpio_bank *bank = get_irq_chip_data(irq);
1091 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1093 /* For level-triggered GPIOs, the clearing must be done after
1094 * the HW source is cleared, thus after the handler has run */
1095 if (bank->level_mask & irq_mask) {
1096 _set_gpio_irqenable(bank, gpio, 0);
1097 _clear_gpio_irqstatus(bank, gpio);
1100 _set_gpio_irqenable(bank, gpio, 1);
1103 static struct irq_chip gpio_irq_chip = {
1105 .shutdown = gpio_irq_shutdown,
1106 .ack = gpio_ack_irq,
1107 .mask = gpio_mask_irq,
1108 .unmask = gpio_unmask_irq,
1109 .set_type = gpio_irq_type,
1110 .set_wake = gpio_wake_enable,
1113 /*---------------------------------------------------------------------*/
1115 #ifdef CONFIG_ARCH_OMAP1
1117 /* MPUIO uses the always-on 32k clock */
1119 static void mpuio_ack_irq(unsigned int irq)
1121 /* The ISR is reset automatically, so do nothing here. */
1124 static void mpuio_mask_irq(unsigned int irq)
1126 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1127 struct gpio_bank *bank = get_irq_chip_data(irq);
1129 _set_gpio_irqenable(bank, gpio, 0);
1132 static void mpuio_unmask_irq(unsigned int irq)
1134 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1135 struct gpio_bank *bank = get_irq_chip_data(irq);
1137 _set_gpio_irqenable(bank, gpio, 1);
1140 static struct irq_chip mpuio_irq_chip = {
1142 .ack = mpuio_ack_irq,
1143 .mask = mpuio_mask_irq,
1144 .unmask = mpuio_unmask_irq,
1145 .set_type = gpio_irq_type,
1146 #ifdef CONFIG_ARCH_OMAP16XX
1147 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1148 .set_wake = gpio_wake_enable,
1153 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1156 #ifdef CONFIG_ARCH_OMAP16XX
1158 #include <linux/platform_device.h>
1160 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1162 struct gpio_bank *bank = platform_get_drvdata(pdev);
1163 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1164 unsigned long flags;
1166 spin_lock_irqsave(&bank->lock, flags);
1167 bank->saved_wakeup = __raw_readl(mask_reg);
1168 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1169 spin_unlock_irqrestore(&bank->lock, flags);
1174 static int omap_mpuio_resume_early(struct platform_device *pdev)
1176 struct gpio_bank *bank = platform_get_drvdata(pdev);
1177 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1178 unsigned long flags;
1180 spin_lock_irqsave(&bank->lock, flags);
1181 __raw_writel(bank->saved_wakeup, mask_reg);
1182 spin_unlock_irqrestore(&bank->lock, flags);
1187 /* use platform_driver for this, now that there's no longer any
1188 * point to sys_device (other than not disturbing old code).
1190 static struct platform_driver omap_mpuio_driver = {
1191 .suspend_late = omap_mpuio_suspend_late,
1192 .resume_early = omap_mpuio_resume_early,
1198 static struct platform_device omap_mpuio_device = {
1202 .driver = &omap_mpuio_driver.driver,
1204 /* could list the /proc/iomem resources */
1207 static inline void mpuio_init(void)
1209 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1211 if (platform_driver_register(&omap_mpuio_driver) == 0)
1212 (void) platform_device_register(&omap_mpuio_device);
1216 static inline void mpuio_init(void) {}
1221 extern struct irq_chip mpuio_irq_chip;
1223 #define bank_is_mpuio(bank) 0
1224 static inline void mpuio_init(void) {}
1228 /*---------------------------------------------------------------------*/
1230 /* REVISIT these are stupid implementations! replace by ones that
1231 * don't switch on METHOD_* and which mostly avoid spinlocks
1234 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1236 struct gpio_bank *bank;
1237 unsigned long flags;
1239 bank = container_of(chip, struct gpio_bank, chip);
1240 spin_lock_irqsave(&bank->lock, flags);
1241 _set_gpio_direction(bank, offset, 1);
1242 spin_unlock_irqrestore(&bank->lock, flags);
1246 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1248 return __omap_get_gpio_datain(chip->base + offset);
1251 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1253 struct gpio_bank *bank;
1254 unsigned long flags;
1256 bank = container_of(chip, struct gpio_bank, chip);
1257 spin_lock_irqsave(&bank->lock, flags);
1258 _set_gpio_dataout(bank, offset, value);
1259 _set_gpio_direction(bank, offset, 0);
1260 spin_unlock_irqrestore(&bank->lock, flags);
1264 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1266 struct gpio_bank *bank;
1267 unsigned long flags;
1269 bank = container_of(chip, struct gpio_bank, chip);
1270 spin_lock_irqsave(&bank->lock, flags);
1271 _set_gpio_dataout(bank, offset, value);
1272 spin_unlock_irqrestore(&bank->lock, flags);
1275 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1277 struct gpio_bank *bank;
1279 bank = container_of(chip, struct gpio_bank, chip);
1280 return bank->virtual_irq_start + offset;
1283 /*---------------------------------------------------------------------*/
1285 static int initialized;
1286 #if !defined(CONFIG_ARCH_OMAP3)
1287 static struct clk * gpio_ick;
1290 #if defined(CONFIG_ARCH_OMAP2)
1291 static struct clk * gpio_fck;
1294 #if defined(CONFIG_ARCH_OMAP2430)
1295 static struct clk * gpio5_ick;
1296 static struct clk * gpio5_fck;
1299 #if defined(CONFIG_ARCH_OMAP3)
1300 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1303 /* This lock class tells lockdep that GPIO irqs are in a different
1304 * category than their parents, so it won't report false recursion.
1306 static struct lock_class_key gpio_lock_class;
1308 static int __init _omap_gpio_init(void)
1312 struct gpio_bank *bank;
1317 #if defined(CONFIG_ARCH_OMAP1)
1318 if (cpu_is_omap15xx()) {
1319 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1320 if (IS_ERR(gpio_ick))
1321 printk("Could not get arm_gpio_ck\n");
1323 clk_enable(gpio_ick);
1326 #if defined(CONFIG_ARCH_OMAP2)
1327 if (cpu_class_is_omap2()) {
1328 gpio_ick = clk_get(NULL, "gpios_ick");
1329 if (IS_ERR(gpio_ick))
1330 printk("Could not get gpios_ick\n");
1332 clk_enable(gpio_ick);
1333 gpio_fck = clk_get(NULL, "gpios_fck");
1334 if (IS_ERR(gpio_fck))
1335 printk("Could not get gpios_fck\n");
1337 clk_enable(gpio_fck);
1340 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1342 #if defined(CONFIG_ARCH_OMAP2430)
1343 if (cpu_is_omap2430()) {
1344 gpio5_ick = clk_get(NULL, "gpio5_ick");
1345 if (IS_ERR(gpio5_ick))
1346 printk("Could not get gpio5_ick\n");
1348 clk_enable(gpio5_ick);
1349 gpio5_fck = clk_get(NULL, "gpio5_fck");
1350 if (IS_ERR(gpio5_fck))
1351 printk("Could not get gpio5_fck\n");
1353 clk_enable(gpio5_fck);
1359 #if defined(CONFIG_ARCH_OMAP3)
1360 if (cpu_is_omap34xx()) {
1361 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1362 sprintf(clk_name, "gpio%d_ick", i + 1);
1363 gpio_iclks[i] = clk_get(NULL, clk_name);
1364 if (IS_ERR(gpio_iclks[i]))
1365 printk(KERN_ERR "Could not get %s\n", clk_name);
1367 clk_enable(gpio_iclks[i]);
1373 #ifdef CONFIG_ARCH_OMAP15XX
1374 if (cpu_is_omap15xx()) {
1375 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1376 gpio_bank_count = 2;
1377 gpio_bank = gpio_bank_1510;
1380 #if defined(CONFIG_ARCH_OMAP16XX)
1381 if (cpu_is_omap16xx()) {
1384 gpio_bank_count = 5;
1385 gpio_bank = gpio_bank_1610;
1386 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1387 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1388 (rev >> 4) & 0x0f, rev & 0x0f);
1391 #ifdef CONFIG_ARCH_OMAP730
1392 if (cpu_is_omap730()) {
1393 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1394 gpio_bank_count = 7;
1395 gpio_bank = gpio_bank_730;
1399 #ifdef CONFIG_ARCH_OMAP24XX
1400 if (cpu_is_omap242x()) {
1403 gpio_bank_count = 4;
1404 gpio_bank = gpio_bank_242x;
1405 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1406 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1407 (rev >> 4) & 0x0f, rev & 0x0f);
1409 if (cpu_is_omap243x()) {
1412 gpio_bank_count = 5;
1413 gpio_bank = gpio_bank_243x;
1414 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1415 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1416 (rev >> 4) & 0x0f, rev & 0x0f);
1419 #ifdef CONFIG_ARCH_OMAP34XX
1420 if (cpu_is_omap34xx()) {
1423 gpio_bank_count = OMAP34XX_NR_GPIOS;
1424 gpio_bank = gpio_bank_34xx;
1425 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1426 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1427 (rev >> 4) & 0x0f, rev & 0x0f);
1430 for (i = 0; i < gpio_bank_count; i++) {
1431 int j, gpio_count = 16;
1433 bank = &gpio_bank[i];
1434 spin_lock_init(&bank->lock);
1435 if (bank_is_mpuio(bank))
1436 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1437 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1438 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1439 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1441 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1442 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1443 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1444 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1446 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1447 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1448 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1450 gpio_count = 32; /* 730 has 32-bit GPIOs */
1453 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1454 if (bank->method == METHOD_GPIO_24XX) {
1455 static const u32 non_wakeup_gpios[] = {
1456 0xe203ffc0, 0x08700040
1459 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1460 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1461 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1463 /* Initialize interface clock ungated, module enabled */
1464 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1465 if (i < ARRAY_SIZE(non_wakeup_gpios))
1466 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1471 /* REVISIT eventually switch from OMAP-specific gpio structs
1472 * over to the generic ones
1474 bank->chip.direction_input = gpio_input;
1475 bank->chip.get = gpio_get;
1476 bank->chip.direction_output = gpio_output;
1477 bank->chip.set = gpio_set;
1478 bank->chip.to_irq = gpio_2irq;
1479 if (bank_is_mpuio(bank)) {
1480 bank->chip.label = "mpuio";
1481 #ifdef CONFIG_ARCH_OMAP16XX
1482 bank->chip.dev = &omap_mpuio_device.dev;
1484 bank->chip.base = OMAP_MPUIO(0);
1486 bank->chip.label = "gpio";
1487 bank->chip.base = gpio;
1490 bank->chip.ngpio = gpio_count;
1492 gpiochip_add(&bank->chip);
1494 for (j = bank->virtual_irq_start;
1495 j < bank->virtual_irq_start + gpio_count; j++) {
1496 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1497 set_irq_chip_data(j, bank);
1498 if (bank_is_mpuio(bank))
1499 set_irq_chip(j, &mpuio_irq_chip);
1501 set_irq_chip(j, &gpio_irq_chip);
1502 set_irq_handler(j, handle_simple_irq);
1503 set_irq_flags(j, IRQF_VALID);
1505 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1506 set_irq_data(bank->irq, bank);
1508 if (cpu_is_omap34xx()) {
1509 sprintf(clk_name, "gpio%d_dbck", i + 1);
1510 bank->dbck = clk_get(NULL, clk_name);
1511 if (IS_ERR(bank->dbck))
1512 printk(KERN_ERR "Could not get %s\n", clk_name);
1516 /* Enable system clock for GPIO module.
1517 * The CAM_CLK_CTRL *is* really the right place. */
1518 if (cpu_is_omap16xx())
1519 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1521 /* Enable autoidle for the OCP interface */
1522 if (cpu_is_omap24xx())
1523 omap_writel(1 << 0, 0x48019010);
1524 if (cpu_is_omap34xx())
1525 omap_writel(1 << 0, 0x48306814);
1530 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1531 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1535 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1538 for (i = 0; i < gpio_bank_count; i++) {
1539 struct gpio_bank *bank = &gpio_bank[i];
1540 void __iomem *wake_status;
1541 void __iomem *wake_clear;
1542 void __iomem *wake_set;
1543 unsigned long flags;
1545 switch (bank->method) {
1546 #ifdef CONFIG_ARCH_OMAP16XX
1547 case METHOD_GPIO_1610:
1548 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1549 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1550 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1553 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1554 case METHOD_GPIO_24XX:
1555 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1556 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1557 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1564 spin_lock_irqsave(&bank->lock, flags);
1565 bank->saved_wakeup = __raw_readl(wake_status);
1566 __raw_writel(0xffffffff, wake_clear);
1567 __raw_writel(bank->suspend_wakeup, wake_set);
1568 spin_unlock_irqrestore(&bank->lock, flags);
1574 static int omap_gpio_resume(struct sys_device *dev)
1578 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1581 for (i = 0; i < gpio_bank_count; i++) {
1582 struct gpio_bank *bank = &gpio_bank[i];
1583 void __iomem *wake_clear;
1584 void __iomem *wake_set;
1585 unsigned long flags;
1587 switch (bank->method) {
1588 #ifdef CONFIG_ARCH_OMAP16XX
1589 case METHOD_GPIO_1610:
1590 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1591 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1594 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1595 case METHOD_GPIO_24XX:
1596 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1597 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1604 spin_lock_irqsave(&bank->lock, flags);
1605 __raw_writel(0xffffffff, wake_clear);
1606 __raw_writel(bank->saved_wakeup, wake_set);
1607 spin_unlock_irqrestore(&bank->lock, flags);
1613 static struct sysdev_class omap_gpio_sysclass = {
1615 .suspend = omap_gpio_suspend,
1616 .resume = omap_gpio_resume,
1619 static struct sys_device omap_gpio_device = {
1621 .cls = &omap_gpio_sysclass,
1626 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1628 static int workaround_enabled;
1630 void omap2_gpio_prepare_for_retention(void)
1634 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1635 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1636 for (i = 0; i < gpio_bank_count; i++) {
1637 struct gpio_bank *bank = &gpio_bank[i];
1640 if (!(bank->enabled_non_wakeup_gpios))
1642 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1643 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1644 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1645 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1647 bank->saved_fallingdetect = l1;
1648 bank->saved_risingdetect = l2;
1649 l1 &= ~bank->enabled_non_wakeup_gpios;
1650 l2 &= ~bank->enabled_non_wakeup_gpios;
1651 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1652 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1653 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1658 workaround_enabled = 0;
1661 workaround_enabled = 1;
1664 void omap2_gpio_resume_after_retention(void)
1668 if (!workaround_enabled)
1670 for (i = 0; i < gpio_bank_count; i++) {
1671 struct gpio_bank *bank = &gpio_bank[i];
1674 if (!(bank->enabled_non_wakeup_gpios))
1676 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1677 __raw_writel(bank->saved_fallingdetect,
1678 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1679 __raw_writel(bank->saved_risingdetect,
1680 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1682 /* Check if any of the non-wakeup interrupt GPIOs have changed
1683 * state. If so, generate an IRQ by software. This is
1684 * horribly racy, but it's the best we can do to work around
1685 * this silicon bug. */
1686 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1687 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1689 l ^= bank->saved_datain;
1690 l &= bank->non_wakeup_gpios;
1693 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1694 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1695 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1696 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1697 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1698 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1699 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1709 * This may get called early from board specific init
1710 * for boards that have interrupts routed via FPGA.
1712 int __init omap_gpio_init(void)
1715 return _omap_gpio_init();
1720 static int __init omap_gpio_sysinit(void)
1725 ret = _omap_gpio_init();
1729 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1730 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1732 ret = sysdev_class_register(&omap_gpio_sysclass);
1734 ret = sysdev_register(&omap_gpio_device);
1742 EXPORT_SYMBOL(omap_request_gpio);
1743 EXPORT_SYMBOL(omap_free_gpio);
1744 EXPORT_SYMBOL(omap_set_gpio_direction);
1746 arch_initcall(omap_gpio_sysinit);
1749 #ifdef CONFIG_DEBUG_FS
1751 #include <linux/debugfs.h>
1752 #include <linux/seq_file.h>
1754 static int gpio_is_input(struct gpio_bank *bank, int mask)
1756 void __iomem *reg = bank->base;
1758 switch (bank->method) {
1760 reg += OMAP_MPUIO_IO_CNTL;
1762 case METHOD_GPIO_1510:
1763 reg += OMAP1510_GPIO_DIR_CONTROL;
1765 case METHOD_GPIO_1610:
1766 reg += OMAP1610_GPIO_DIRECTION;
1768 case METHOD_GPIO_730:
1769 reg += OMAP730_GPIO_DIR_CONTROL;
1771 case METHOD_GPIO_24XX:
1772 reg += OMAP24XX_GPIO_OE;
1775 return __raw_readl(reg) & mask;
1779 static int dbg_gpio_show(struct seq_file *s, void *unused)
1781 unsigned i, j, gpio;
1783 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1784 struct gpio_bank *bank = gpio_bank + i;
1785 unsigned bankwidth = 16;
1788 if (bank_is_mpuio(bank))
1789 gpio = OMAP_MPUIO(0);
1790 else if (cpu_class_is_omap2() || cpu_is_omap730())
1793 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1794 unsigned irq, value, is_in, irqstat;
1797 label = gpiochip_is_requested(&bank->chip, j);
1801 irq = bank->virtual_irq_start + j;
1802 value = gpio_get_value(gpio);
1803 is_in = gpio_is_input(bank, mask);
1805 if (bank_is_mpuio(bank))
1806 seq_printf(s, "MPUIO %2d ", j);
1808 seq_printf(s, "GPIO %3d ", gpio);
1809 seq_printf(s, "(%-20.20s): %s %s",
1811 is_in ? "in " : "out",
1812 value ? "hi" : "lo");
1814 /* FIXME for at least omap2, show pullup/pulldown state */
1816 irqstat = irq_desc[irq].status;
1817 if (is_in && ((bank->suspend_wakeup & mask)
1818 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1819 char *trigger = NULL;
1821 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1822 case IRQ_TYPE_EDGE_FALLING:
1823 trigger = "falling";
1825 case IRQ_TYPE_EDGE_RISING:
1828 case IRQ_TYPE_EDGE_BOTH:
1829 trigger = "bothedge";
1831 case IRQ_TYPE_LEVEL_LOW:
1834 case IRQ_TYPE_LEVEL_HIGH:
1841 seq_printf(s, ", irq-%d %-8s%s",
1843 (bank->suspend_wakeup & mask)
1846 seq_printf(s, "\n");
1849 if (bank_is_mpuio(bank)) {
1850 seq_printf(s, "\n");
1857 static int dbg_gpio_open(struct inode *inode, struct file *file)
1859 return single_open(file, dbg_gpio_show, &inode->i_private);
1862 static const struct file_operations debug_fops = {
1863 .open = dbg_gpio_open,
1865 .llseek = seq_lseek,
1866 .release = single_release,
1869 static int __init omap_gpio_debuginit(void)
1871 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1872 NULL, NULL, &debug_fops);
1875 late_initcall(omap_gpio_debuginit);