arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/io.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/hardware.h>
  32 #include <asm/dma.h>
  33
  34 #include <asm/arch/tc.h>
  35
  36 #undef DEBUG
  37
  38 #ifndef CONFIG_ARCH_OMAP1
  39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  40         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  41 };
  42
  43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  44 #endif
  45
  46 #define OMAP_DMA_ACTIVE                 0x01
  47 #define OMAP_DMA_CCR_EN                 (1 << 7)
  48 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  49
  50 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  51
  52 static int enable_1510_mode;
  53
  54 struct omap_dma_lch {
  55         int next_lch;
  56         int dev_id;
  57         u16 saved_csr;
  58         u16 enabled_irqs;
  59         const char *dev_name;
  60         void (*callback)(int lch, u16 ch_status, void *data);
  61         void *data;
  62
  63 #ifndef CONFIG_ARCH_OMAP1
  64         /* required for Dynamic chaining */
  65         int prev_linked_ch;
  66         int next_linked_ch;
  67         int state;
  68         int chain_id;
  69
  70         int status;
  71 #endif
  72         long flags;
  73 };
  74
  75 struct dma_link_info {
  76         int *linked_dmach_q;
  77         int no_of_lchs_linked;
  78
  79         int q_count;
  80         int q_tail;
  81         int q_head;
  82
  83         int chain_state;
  84         int chain_mode;
  85
  86 };
  87
  88 static struct dma_link_info *dma_linked_lch;
  89
  90 #ifndef CONFIG_ARCH_OMAP1
  91
  92 /* Chain handling macros */
  93 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  94         do {                                                            \
  95                 dma_linked_lch[chain_id].q_head =                       \
  96                 dma_linked_lch[chain_id].q_tail =                       \
  97                 dma_linked_lch[chain_id].q_count = 0;                   \
  98         } while (0)
  99 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 100                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 101                 dma_linked_lch[chain_id].q_count)
 102 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 103         do {                                                            \
 104                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 105                 dma_linked_lch[chain_id].q_count)                       \
 106         } while (0)
 107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 108                 (0 == dma_linked_lch[chain_id].q_count)
 109 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 110         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 112         do {                                                            \
 113                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 114                 dma_linked_lch[chain_id].q_count--;                     \
 115         } while (0)
 116
 117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 118         do {                                                            \
 119                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 120                 dma_linked_lch[chain_id].q_count++; \
 121         } while (0)
 122 #endif
 123
 124 static int dma_lch_count;
 125 static int dma_chan_count;
 126
 127 static spinlock_t dma_chan_lock;
 128 static struct omap_dma_lch *dma_chan;
 129 void __iomem *omap_dma_base;
 130
 131 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 132         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 133         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 134         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 135         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 136         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 137 };
 138
 139 static inline void disable_lnk(int lch);
 140 static void omap_disable_channel_irq(int lch);
 141 static inline void omap_enable_channel_irq(int lch);
 142
 143 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 144                                                 __func__);
 145
 146 #define dma_read(reg)                                           \
 147 ({                                                                      \
 148         u32 __val;                                                      \
 149         if (cpu_class_is_omap1())                                       \
 150                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 151         else                                                            \
 152                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 153         __val;                                                          \
 154 })
 155
 156 #define dma_write(val, reg)                                             \
 157 ({                                                                      \
 158         if (cpu_class_is_omap1())                                       \
 159                 __raw_writew((u16)val, omap_dma_base + OMAP1_DMA_##reg);\
 160         else                                                            \
 161                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 162 })
 163
 164 #ifdef CONFIG_ARCH_OMAP15XX
 165 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 166 int omap_dma_in_1510_mode(void)
 167 {
 168         return enable_1510_mode;
 169 }
 170 #else
 171 #define omap_dma_in_1510_mode()         0
 172 #endif
 173
 174 #ifdef CONFIG_ARCH_OMAP1
 175 static inline int get_gdma_dev(int req)
 176 {
 177         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 178         int shift = ((req - 1) % 5) * 6;
 179
 180         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 181 }
 182
 183 static inline void set_gdma_dev(int req, int dev)
 184 {
 185         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 186         int shift = ((req - 1) % 5) * 6;
 187         u32 l;
 188
 189         l = omap_readl(reg);
 190         l &= ~(0x3f << shift);
 191         l |= (dev - 1) << shift;
 192         omap_writel(l, reg);
 193 }
 194 #else
 195 #define set_gdma_dev(req, dev)  do {} while (0)
 196 #endif
 197
 198 /* Omap1 only */
 199 static void clear_lch_regs(int lch)
 200 {
 201         int i;
 202         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 203
 204         for (i = 0; i < 0x2c; i += 2)
 205                 __raw_writew(0, lch_base + i);
 206 }
 207
 208 void omap_set_dma_priority(int lch, int dst_port, int priority)
 209 {
 210         unsigned long reg;
 211         u32 l;
 212
 213         if (cpu_class_is_omap1()) {
 214                 switch (dst_port) {
 215                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 216                         reg = OMAP_TC_OCPT1_PRIOR;
 217                         break;
 218                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 219                         reg = OMAP_TC_OCPT2_PRIOR;
 220                         break;
 221                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 222                         reg = OMAP_TC_EMIFF_PRIOR;
 223                         break;
 224                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 225                         reg = OMAP_TC_EMIFS_PRIOR;
 226                         break;
 227                 default:
 228                         BUG();
 229                         return;
 230                 }
 231                 l = omap_readl(reg);
 232                 l &= ~(0xf << 8);
 233                 l |= (priority & 0xf) << 8;
 234                 omap_writel(l, reg);
 235         }
 236
 237         if (cpu_class_is_omap2()) {
 238                 u32 ccr;
 239
 240                 ccr = dma_read(CCR(lch));
 241                 if (priority)
 242                         ccr |= (1 << 6);
 243                 else
 244                         ccr &= ~(1 << 6);
 245                 dma_write(ccr, CCR(lch));
 246         }
 247 }
 248 EXPORT_SYMBOL(omap_set_dma_priority);
 249
 250 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 251                                   int frame_count, int sync_mode,
 252                                   int dma_trigger, int src_or_dst_synch)
 253 {
 254         u32 l;
 255
 256         l = dma_read(CSDP(lch));
 257         l &= ~0x03;
 258         l |= data_type;
 259         dma_write(l, CSDP(lch));
 260
 261         if (cpu_class_is_omap1()) {
 262                 u16 ccr;
 263
 264                 ccr = dma_read(CCR(lch));
 265                 ccr &= ~(1 << 5);
 266                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 267                         ccr |= 1 << 5;
 268                 dma_write(ccr, CCR(lch));
 269
 270                 ccr = dma_read(CCR2(lch));
 271                 ccr &= ~(1 << 2);
 272                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 273                         ccr |= 1 << 2;
 274                 dma_write(ccr, CCR2(lch));
 275         }
 276
 277         if (cpu_class_is_omap2() && dma_trigger) {
 278                 u32 val;
 279
 280                 val = dma_read(CCR(lch));
 281                 val &= ~(3 << 19);
 282                 if (dma_trigger > 63)
 283                         val |= 1 << 20;
 284                 if (dma_trigger > 31)
 285                         val |= 1 << 19;
 286
 287                 val &= ~(0x1f);
 288                 val |= (dma_trigger & 0x1f);
 289
 290                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 291                         val |= 1 << 5;
 292                 else
 293                         val &= ~(1 << 5);
 294
 295                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 296                         val |= 1 << 18;
 297                 else
 298                         val &= ~(1 << 18);
 299
 300                 if (src_or_dst_synch)
 301                         val |= 1 << 24;         /* source synch */
 302                 else
 303                         val &= ~(1 << 24);      /* dest synch */
 304
 305                 dma_write(val, CCR(lch));
 306         }
 307
 308         dma_write(elem_count, CEN(lch));
 309         dma_write(frame_count, CFN(lch));
 310 }
 311 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 312
 313 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 314 {
 315         u16 w;
 316
 317         BUG_ON(omap_dma_in_1510_mode());
 318
 319         if (cpu_class_is_omap2()) {
 320                 REVISIT_24XX();
 321                 return;
 322         }
 323
 324         w = dma_read(CCR2(lch));
 325         w &= ~0x03;
 326
 327         switch (mode) {
 328         case OMAP_DMA_CONSTANT_FILL:
 329                 w |= 0x01;
 330                 break;
 331         case OMAP_DMA_TRANSPARENT_COPY:
 332                 w |= 0x02;
 333                 break;
 334         case OMAP_DMA_COLOR_DIS:
 335                 break;
 336         default:
 337                 BUG();
 338         }
 339         dma_write(w, CCR2(lch));
 340
 341         w = dma_read(LCH_CTRL(lch));
 342         w &= ~0x0f;
 343         /* Default is channel type 2D */
 344         if (mode) {
 345                 dma_write((u16)color, COLOR_L(lch));
 346                 dma_write((u16)(color >> 16), COLOR_U(lch));
 347                 w |= 1;         /* Channel type G */
 348         }
 349         dma_write(w, LCH_CTRL(lch));
 350 }
 351 EXPORT_SYMBOL(omap_set_dma_color_mode);
 352
 353 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 354 {
 355         if (cpu_class_is_omap2()) {
 356                 u32 csdp;
 357
 358                 csdp = dma_read(CSDP(lch));
 359                 csdp &= ~(0x3 << 16);
 360                 csdp |= (mode << 16);
 361                 dma_write(csdp, CSDP(lch));
 362         }
 363 }
 364 EXPORT_SYMBOL(omap_set_dma_write_mode);
 365
 366 /* Note that src_port is only for omap1 */
 367 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 368                              unsigned long src_start,
 369                              int src_ei, int src_fi)
 370 {
 371         u32 l;
 372
 373         if (cpu_class_is_omap1()) {
 374                 u16 w;
 375
 376                 w = dma_read(CSDP(lch));
 377                 w &= ~(0x1f << 2);
 378                 w |= src_port << 2;
 379                 dma_write(w, CSDP(lch));
 380         }
 381
 382         l = dma_read(CCR(lch));
 383         l &= ~(0x03 << 12);
 384         l |= src_amode << 12;
 385         dma_write(l, CCR(lch));
 386
 387         if (cpu_class_is_omap1()) {
 388                 dma_write(src_start >> 16, CSSA_U(lch));
 389                 dma_write((u16)src_start, CSSA_L(lch));
 390         }
 391
 392         if (cpu_class_is_omap2())
 393                 dma_write(src_start, CSSA(lch));
 394
 395         dma_write(src_ei, CSEI(lch));
 396         dma_write(src_fi, CSFI(lch));
 397 }
 398 EXPORT_SYMBOL(omap_set_dma_src_params);
 399
 400 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 401 {
 402         omap_set_dma_transfer_params(lch, params->data_type,
 403                                      params->elem_count, params->frame_count,
 404                                      params->sync_mode, params->trigger,
 405                                      params->src_or_dst_synch);
 406         omap_set_dma_src_params(lch, params->src_port,
 407                                 params->src_amode, params->src_start,
 408                                 params->src_ei, params->src_fi);
 409
 410         omap_set_dma_dest_params(lch, params->dst_port,
 411                                  params->dst_amode, params->dst_start,
 412                                  params->dst_ei, params->dst_fi);
 413         if (params->read_prio || params->write_prio)
 414                 omap_dma_set_prio_lch(lch, params->read_prio,
 415                                       params->write_prio);
 416 }
 417 EXPORT_SYMBOL(omap_set_dma_params);
 418
 419 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 420 {
 421         if (cpu_class_is_omap2())
 422                 return;
 423
 424         dma_write(eidx, CSEI(lch));
 425         dma_write(fidx, CSFI(lch));
 426 }
 427 EXPORT_SYMBOL(omap_set_dma_src_index);
 428
 429 void omap_set_dma_src_data_pack(int lch, int enable)
 430 {
 431         u32 l;
 432
 433         l = dma_read(CSDP(lch));
 434         l &= ~(1 << 6);
 435         if (enable)
 436                 l |= (1 << 6);
 437         dma_write(l, CSDP(lch));
 438 }
 439 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 440
 441 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 442 {
 443         unsigned int burst = 0;
 444         u32 l;
 445
 446         l = dma_read(CSDP(lch));
 447         l &= ~(0x03 << 7);
 448
 449         switch (burst_mode) {
 450         case OMAP_DMA_DATA_BURST_DIS:
 451                 break;
 452         case OMAP_DMA_DATA_BURST_4:
 453                 if (cpu_class_is_omap2())
 454                         burst = 0x1;
 455                 else
 456                         burst = 0x2;
 457                 break;
 458         case OMAP_DMA_DATA_BURST_8:
 459                 if (cpu_class_is_omap2()) {
 460                         burst = 0x2;
 461                         break;
 462                 }
 463                 /* not supported by current hardware on OMAP1
 464                  * w |= (0x03 << 7);
 465                  * fall through
 466                  */
 467         case OMAP_DMA_DATA_BURST_16:
 468                 if (cpu_class_is_omap2()) {
 469                         burst = 0x3;
 470                         break;
 471                 }
 472                 /* OMAP1 don't support burst 16
 473                  * fall through
 474                  */
 475         default:
 476                 BUG();
 477         }
 478
 479         l |= (burst << 7);
 480         dma_write(l, CSDP(lch));
 481 }
 482 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 483
 484 /* Note that dest_port is only for OMAP1 */
 485 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 486                               unsigned long dest_start,
 487                               int dst_ei, int dst_fi)
 488 {
 489         u32 l;
 490
 491         if (cpu_class_is_omap1()) {
 492                 l = dma_read(CSDP(lch));
 493                 l &= ~(0x1f << 9);
 494                 l |= dest_port << 9;
 495                 dma_write(l, CSDP(lch));
 496         }
 497
 498         l = dma_read(CCR(lch));
 499         l &= ~(0x03 << 14);
 500         l |= dest_amode << 14;
 501         dma_write(l, CCR(lch));
 502
 503         if (cpu_class_is_omap1()) {
 504                 dma_write(dest_start >> 16, CDSA_U(lch));
 505                 dma_write(dest_start, CDSA_L(lch));
 506         }
 507
 508         if (cpu_class_is_omap2())
 509                 dma_write(dest_start, CDSA(lch));
 510
 511         dma_write(dst_ei, CDEI(lch));
 512         dma_write(dst_fi, CDFI(lch));
 513 }
 514 EXPORT_SYMBOL(omap_set_dma_dest_params);
 515
 516 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 517 {
 518         if (cpu_class_is_omap2())
 519                 return;
 520
 521         dma_write(eidx, CDEI(lch));
 522         dma_write(fidx, CDFI(lch));
 523 }
 524 EXPORT_SYMBOL(omap_set_dma_dest_index);
 525
 526 void omap_set_dma_dest_data_pack(int lch, int enable)
 527 {
 528         u32 l;
 529
 530         l = dma_read(CSDP(lch));
 531         l &= ~(1 << 13);
 532         if (enable)
 533                 l |= 1 << 13;
 534         dma_write(l, CSDP(lch));
 535 }
 536 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 537
 538 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 539 {
 540         unsigned int burst = 0;
 541         u32 l;
 542
 543         l = dma_read(CSDP(lch));
 544         l &= ~(0x03 << 14);
 545
 546         switch (burst_mode) {
 547         case OMAP_DMA_DATA_BURST_DIS:
 548                 break;
 549         case OMAP_DMA_DATA_BURST_4:
 550                 if (cpu_class_is_omap2())
 551                         burst = 0x1;
 552                 else
 553                         burst = 0x2;
 554                 break;
 555         case OMAP_DMA_DATA_BURST_8:
 556                 if (cpu_class_is_omap2())
 557                         burst = 0x2;
 558                 else
 559                         burst = 0x3;
 560                 break;
 561         case OMAP_DMA_DATA_BURST_16:
 562                 if (cpu_class_is_omap2()) {
 563                         burst = 0x3;
 564                         break;
 565                 }
 566                 /* OMAP1 don't support burst 16
 567                  * fall through
 568                  */
 569         default:
 570                 printk(KERN_ERR "Invalid DMA burst mode\n");
 571                 BUG();
 572                 return;
 573         }
 574         l |= (burst << 14);
 575         dma_write(l, CSDP(lch));
 576 }
 577 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 578
 579 static inline void omap_enable_channel_irq(int lch)
 580 {
 581         u32 status;
 582
 583         /* Clear CSR */
 584         if (cpu_class_is_omap1())
 585                 status = dma_read(CSR(lch));
 586         else if (cpu_class_is_omap2())
 587                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 588
 589         /* Enable some nice interrupts. */
 590         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 591 }
 592
 593 static void omap_disable_channel_irq(int lch)
 594 {
 595         if (cpu_class_is_omap2())
 596                 dma_write(0, CICR(lch));
 597 }
 598
 599 void omap_enable_dma_irq(int lch, u16 bits)
 600 {
 601         dma_chan[lch].enabled_irqs |= bits;
 602 }
 603 EXPORT_SYMBOL(omap_enable_dma_irq);
 604
 605 void omap_disable_dma_irq(int lch, u16 bits)
 606 {
 607         dma_chan[lch].enabled_irqs &= ~bits;
 608 }
 609 EXPORT_SYMBOL(omap_disable_dma_irq);
 610
 611 static inline void enable_lnk(int lch)
 612 {
 613         u32 l;
 614
 615         l = dma_read(CLNK_CTRL(lch));
 616
 617         if (cpu_class_is_omap1())
 618                 l &= ~(1 << 14);
 619
 620         /* Set the ENABLE_LNK bits */
 621         if (dma_chan[lch].next_lch != -1)
 622                 l = dma_chan[lch].next_lch | (1 << 15);
 623
 624 #ifndef CONFIG_ARCH_OMAP1
 625         if (cpu_class_is_omap2())
 626                 if (dma_chan[lch].next_linked_ch != -1)
 627                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 628 #endif
 629
 630         dma_write(l, CLNK_CTRL(lch));
 631 }
 632
 633 static inline void disable_lnk(int lch)
 634 {
 635         u32 l;
 636
 637         l = dma_read(CLNK_CTRL(lch));
 638
 639         /* Disable interrupts */
 640         if (cpu_class_is_omap1()) {
 641                 dma_write(0, CICR(lch));
 642                 /* Set the STOP_LNK bit */
 643                 l |= 1 << 14;
 644         }
 645
 646         if (cpu_class_is_omap2()) {
 647                 omap_disable_channel_irq(lch);
 648                 /* Clear the ENABLE_LNK bit */
 649                 l &= ~(1 << 15);
 650         }
 651
 652         dma_write(l, CLNK_CTRL(lch));
 653         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 654 }
 655
 656 static inline void omap2_enable_irq_lch(int lch)
 657 {
 658         u32 val;
 659
 660         if (!cpu_class_is_omap2())
 661                 return;
 662
 663         val = dma_read(IRQENABLE_L0);
 664         val |= 1 << lch;
 665         dma_write(val, IRQENABLE_L0);
 666 }
 667
 668 int omap_request_dma(int dev_id, const char *dev_name,
 669                      void (*callback)(int lch, u16 ch_status, void *data),
 670                      void *data, int *dma_ch_out)
 671 {
 672         int ch, free_ch = -1;
 673         unsigned long flags;
 674         struct omap_dma_lch *chan;
 675
 676         spin_lock_irqsave(&dma_chan_lock, flags);
 677         for (ch = 0; ch < dma_chan_count; ch++) {
 678                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 679                         free_ch = ch;
 680                         if (dev_id == 0)
 681                                 break;
 682                 }
 683         }
 684         if (free_ch == -1) {
 685                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 686                 return -EBUSY;
 687         }
 688         chan = dma_chan + free_ch;
 689         chan->dev_id = dev_id;
 690
 691         if (cpu_class_is_omap1())
 692                 clear_lch_regs(free_ch);
 693
 694         if (cpu_class_is_omap2())
 695                 omap_clear_dma(free_ch);
 696
 697         spin_unlock_irqrestore(&dma_chan_lock, flags);
 698
 699         chan->dev_name = dev_name;
 700         chan->callback = callback;
 701         chan->data = data;
 702
 703 #ifndef CONFIG_ARCH_OMAP1
 704         if (cpu_class_is_omap2()) {
 705                 chan->chain_id = -1;
 706                 chan->next_linked_ch = -1;
 707         }
 708 #endif
 709
 710         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 711
 712         if (cpu_class_is_omap1())
 713                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 714         else if (cpu_class_is_omap2())
 715                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 716                         OMAP2_DMA_TRANS_ERR_IRQ;
 717
 718         if (cpu_is_omap16xx()) {
 719                 /* If the sync device is set, configure it dynamically. */
 720                 if (dev_id != 0) {
 721                         set_gdma_dev(free_ch + 1, dev_id);
 722                         dev_id = free_ch + 1;
 723                 }
 724                 /*
 725                  * Disable the 1510 compatibility mode and set the sync device
 726                  * id.
 727                  */
 728                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 729         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
 730                 dma_write(dev_id, CCR(free_ch));
 731         }
 732
 733         if (cpu_class_is_omap2()) {
 734                 omap2_enable_irq_lch(free_ch);
 735                 omap_enable_channel_irq(free_ch);
 736                 /* Clear the CSR register and IRQ status register */
 737                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 738                 dma_write(1 << free_ch, IRQSTATUS_L0);
 739         }
 740
 741         *dma_ch_out = free_ch;
 742
 743         return 0;
 744 }
 745 EXPORT_SYMBOL(omap_request_dma);
 746
 747 void omap_free_dma(int lch)
 748 {
 749         unsigned long flags;
 750
 751         spin_lock_irqsave(&dma_chan_lock, flags);
 752         if (dma_chan[lch].dev_id == -1) {
 753                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 754                        lch);
 755                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 756                 return;
 757         }
 758
 759         dma_chan[lch].dev_id = -1;
 760         dma_chan[lch].next_lch = -1;
 761         dma_chan[lch].callback = NULL;
 762         spin_unlock_irqrestore(&dma_chan_lock, flags);
 763
 764         if (cpu_class_is_omap1()) {
 765                 /* Disable all DMA interrupts for the channel. */
 766                 dma_write(0, CICR(lch));
 767                 /* Make sure the DMA transfer is stopped. */
 768                 dma_write(0, CCR(lch));
 769         }
 770
 771         if (cpu_class_is_omap2()) {
 772                 u32 val;
 773                 /* Disable interrupts */
 774                 val = dma_read(IRQENABLE_L0);
 775                 val &= ~(1 << lch);
 776                 dma_write(val, IRQENABLE_L0);
 777
 778                 /* Clear the CSR register and IRQ status register */
 779                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 780                 dma_write(1 << lch, IRQSTATUS_L0);
 781
 782                 /* Disable all DMA interrupts for the channel. */
 783                 dma_write(0, CICR(lch));
 784
 785                 /* Make sure the DMA transfer is stopped. */
 786                 dma_write(0, CCR(lch));
 787                 omap_clear_dma(lch);
 788         }
 789 }
 790 EXPORT_SYMBOL(omap_free_dma);
 791
 792 /**
 793  * @brief omap_dma_set_global_params : Set global priority settings for dma
 794  *
 795  * @param arb_rate
 796  * @param max_fifo_depth
 797  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 798  *                                                  DMA_THREAD_RESERVE_ONET
 799  *                                                  DMA_THREAD_RESERVE_TWOT
 800  *                                                  DMA_THREAD_RESERVE_THREET
 801  */
 802 void
 803 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 804 {
 805         u32 reg;
 806
 807         if (!cpu_class_is_omap2()) {
 808                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 809                 return;
 810         }
 811
 812         if (arb_rate == 0)
 813                 arb_rate = 1;
 814
 815         reg = (arb_rate & 0xff) << 16;
 816         reg |= (0xff & max_fifo_depth);
 817
 818         dma_write(reg, GCR);
 819 }
 820 EXPORT_SYMBOL(omap_dma_set_global_params);
 821
 822 /**
 823  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 824  *
 825  * @param lch
 826  * @param read_prio - Read priority
 827  * @param write_prio - Write priority
 828  * Both of the above can be set with one of the following values :
 829  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 830  */
 831 int
 832 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 833                       unsigned char write_prio)
 834 {
 835         u32 l;
 836
 837         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 838                 printk(KERN_ERR "Invalid channel id\n");
 839                 return -EINVAL;
 840         }
 841         l = dma_read(CCR(lch));
 842         l &= ~((1 << 6) | (1 << 26));
 843         if (cpu_is_omap2430() || cpu_is_omap34xx())
 844                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 845         else
 846                 l |= ((read_prio & 0x1) << 6);
 847
 848         dma_write(l, CCR(lch));
 849
 850         return 0;
 851 }
 852 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 853
 854 /*
 855  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 856  * through omap_start_dma(). Any buffers in flight are discarded.
 857  */
 858 void omap_clear_dma(int lch)
 859 {
 860         unsigned long flags;
 861
 862         local_irq_save(flags);
 863
 864         if (cpu_class_is_omap1()) {
 865                 u32 l;
 866
 867                 l = dma_read(CCR(lch));
 868                 l &= ~OMAP_DMA_CCR_EN;
 869                 dma_write(l, CCR(lch));
 870
 871                 /* Clear pending interrupts */
 872                 l = dma_read(CSR(lch));
 873         }
 874
 875         if (cpu_class_is_omap2()) {
 876                 int i;
 877                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 878                 for (i = 0; i < 0x44; i += 4)
 879                         __raw_writel(0, lch_base + i);
 880         }
 881
 882         local_irq_restore(flags);
 883 }
 884 EXPORT_SYMBOL(omap_clear_dma);
 885
 886 void omap_start_dma(int lch)
 887 {
 888         u32 l;
 889
 890         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 891                 int next_lch, cur_lch;
 892                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 893
 894                 dma_chan_link_map[lch] = 1;
 895                 /* Set the link register of the first channel */
 896                 enable_lnk(lch);
 897
 898                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 899                 cur_lch = dma_chan[lch].next_lch;
 900                 do {
 901                         next_lch = dma_chan[cur_lch].next_lch;
 902
 903                         /* The loop case: we've been here already */
 904                         if (dma_chan_link_map[cur_lch])
 905                                 break;
 906                         /* Mark the current channel */
 907                         dma_chan_link_map[cur_lch] = 1;
 908
 909                         enable_lnk(cur_lch);
 910                         omap_enable_channel_irq(cur_lch);
 911
 912                         cur_lch = next_lch;
 913                 } while (next_lch != -1);
 914         } else if (cpu_class_is_omap2()) {
 915                 /* Errata: Need to write lch even if not using chaining */
 916                 dma_write(lch, CLNK_CTRL(lch));
 917         }
 918
 919         omap_enable_channel_irq(lch);
 920
 921         l = dma_read(CCR(lch));
 922
 923         /*
 924          * Errata: On ES2.0 BUFFERING disable must be set.
 925          * This will always fail on ES1.0
 926          */
 927         if (cpu_is_omap24xx())
 928                 l |= OMAP_DMA_CCR_EN;
 929
 930         l |= OMAP_DMA_CCR_EN;
 931         dma_write(l, CCR(lch));
 932
 933         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 934 }
 935 EXPORT_SYMBOL(omap_start_dma);
 936
 937 void omap_stop_dma(int lch)
 938 {
 939         u32 l;
 940
 941         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 942                 int next_lch, cur_lch = lch;
 943                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 944
 945                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 946                 do {
 947                         /* The loop case: we've been here already */
 948                         if (dma_chan_link_map[cur_lch])
 949                                 break;
 950                         /* Mark the current channel */
 951                         dma_chan_link_map[cur_lch] = 1;
 952
 953                         disable_lnk(cur_lch);
 954
 955                         next_lch = dma_chan[cur_lch].next_lch;
 956                         cur_lch = next_lch;
 957                 } while (next_lch != -1);
 958
 959                 return;
 960         }
 961
 962         /* Disable all interrupts on the channel */
 963         if (cpu_class_is_omap1())
 964                 dma_write(0, CICR(lch));
 965
 966         l = dma_read(CCR(lch));
 967         l &= ~OMAP_DMA_CCR_EN;
 968         dma_write(l, CCR(lch));
 969
 970         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 971 }
 972 EXPORT_SYMBOL(omap_stop_dma);
 973
 974 /*
 975  * Allows changing the DMA callback function or data. This may be needed if
 976  * the driver shares a single DMA channel for multiple dma triggers.
 977  */
 978 int omap_set_dma_callback(int lch,
 979                           void (*callback)(int lch, u16 ch_status, void *data),
 980                           void *data)
 981 {
 982         unsigned long flags;
 983
 984         if (lch < 0)
 985                 return -ENODEV;
 986
 987         spin_lock_irqsave(&dma_chan_lock, flags);
 988         if (dma_chan[lch].dev_id == -1) {
 989                 printk(KERN_ERR "DMA callback for not set for free channel\n");
 990                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 991                 return -EINVAL;
 992         }
 993         dma_chan[lch].callback = callback;
 994         dma_chan[lch].data = data;
 995         spin_unlock_irqrestore(&dma_chan_lock, flags);
 996
 997         return 0;
 998 }
 999 EXPORT_SYMBOL(omap_set_dma_callback);
1000
1001 /*
1002  * Returns current physical source address for the given DMA channel.
1003  * If the channel is running the caller must disable interrupts prior calling
1004  * this function and process the returned value before re-enabling interrupt to
1005  * prevent races with the interrupt handler. Note that in continuous mode there
1006  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1007  * in incorrect return value.
1008  */
1009 dma_addr_t omap_get_dma_src_pos(int lch)
1010 {
1011         dma_addr_t offset = 0;
1012
1013         if (cpu_class_is_omap1())
1014                 offset = (dma_addr_t)(dma_read(CSSA_L(lch)) |
1015                                         (dma_read(CSSA_U(lch)) << 16));
1016
1017         if (cpu_class_is_omap2()) {
1018                 offset = dma_read(CSAC(lch));
1019
1020                 /*
1021                  * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1022                  * read before the DMA controller finished disabling the channel.
1023                  */
1024                 if (offset == 0)
1025                         offset = dma_read(CSAC(lch));
1026         }
1027
1028         return offset;
1029 }
1030 EXPORT_SYMBOL(omap_get_dma_src_pos);
1031
1032 /*
1033  * Returns current physical destination address for the given DMA channel.
1034  * If the channel is running the caller must disable interrupts prior calling
1035  * this function and process the returned value before re-enabling interrupt to
1036  * prevent races with the interrupt handler. Note that in continuous mode there
1037  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1038  * in incorrect return value.
1039  */
1040 dma_addr_t omap_get_dma_dst_pos(int lch)
1041 {
1042         dma_addr_t offset = 0;
1043
1044         if (cpu_class_is_omap1())
1045                 offset = (dma_addr_t)(dma_read(CDSA_L(lch)) |
1046                                         (dma_read(CDSA_U(lch)) << 16));
1047
1048         if (cpu_class_is_omap2()) {
1049                 offset = dma_read(CDAC(lch));
1050
1051                 /*
1052                  * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1053                  * read before the DMA controller finished disabling the channel.
1054                  */
1055                 if (offset == 0)
1056                         offset = dma_read(CDAC(lch));
1057         }
1058
1059         return offset;
1060 }
1061 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1062
1063 /*
1064  * Returns current source transfer counting for the given DMA channel.
1065  * Can be used to monitor the progress of a transfer inside a block.
1066  * It must be called with disabled interrupts.
1067  */
1068 int omap_get_dma_src_addr_counter(int lch)
1069 {
1070         return (dma_addr_t)dma_read(CSAC(lch));
1071 }
1072 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
1073
1074 int omap_get_dma_active_status(int lch)
1075 {
1076         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1077 }
1078 EXPORT_SYMBOL(omap_get_dma_active_status);
1079
1080 int omap_dma_running(void)
1081 {
1082         int lch;
1083
1084         /* Check if LCD DMA is running */
1085         if (cpu_is_omap16xx())
1086                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1087                         return 1;
1088
1089         for (lch = 0; lch < dma_chan_count; lch++)
1090                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1091                         return 1;
1092
1093         return 0;
1094 }
1095
1096 /*
1097  * lch_queue DMA will start right after lch_head one is finished.
1098  * For this DMA link to start, you still need to start (see omap_start_dma)
1099  * the first one. That will fire up the entire queue.
1100  */
1101 void omap_dma_link_lch(int lch_head, int lch_queue)
1102 {
1103         if (omap_dma_in_1510_mode()) {
1104                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1105                 BUG();
1106                 return;
1107         }
1108
1109         if ((dma_chan[lch_head].dev_id == -1) ||
1110             (dma_chan[lch_queue].dev_id == -1)) {
1111                 printk(KERN_ERR "omap_dma: trying to link "
1112                        "non requested channels\n");
1113                 dump_stack();
1114         }
1115
1116         dma_chan[lch_head].next_lch = lch_queue;
1117 }
1118 EXPORT_SYMBOL(omap_dma_link_lch);
1119
1120 /*
1121  * Once the DMA queue is stopped, we can destroy it.
1122  */
1123 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1124 {
1125         if (omap_dma_in_1510_mode()) {
1126                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1127                 BUG();
1128                 return;
1129         }
1130
1131         if (dma_chan[lch_head].next_lch != lch_queue ||
1132             dma_chan[lch_head].next_lch == -1) {
1133                 printk(KERN_ERR "omap_dma: trying to unlink "
1134                        "non linked channels\n");
1135                 dump_stack();
1136         }
1137
1138         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1139             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1140                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1141                        "before unlinking\n");
1142                 dump_stack();
1143         }
1144
1145         dma_chan[lch_head].next_lch = -1;
1146 }
1147 EXPORT_SYMBOL(omap_dma_unlink_lch);
1148
1149 /*----------------------------------------------------------------------------*/
1150
1151 #ifndef CONFIG_ARCH_OMAP1
1152 /* Create chain of DMA channesls */
1153 static void create_dma_lch_chain(int lch_head, int lch_queue)
1154 {
1155         u32 l;
1156
1157         /* Check if this is the first link in chain */
1158         if (dma_chan[lch_head].next_linked_ch == -1) {
1159                 dma_chan[lch_head].next_linked_ch = lch_queue;
1160                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1161                 dma_chan[lch_queue].next_linked_ch = lch_head;
1162                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1163         }
1164
1165         /* a link exists, link the new channel in circular chain */
1166         else {
1167                 dma_chan[lch_queue].next_linked_ch =
1168                                         dma_chan[lch_head].next_linked_ch;
1169                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1170                 dma_chan[lch_head].next_linked_ch = lch_queue;
1171                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1172                                         lch_queue;
1173         }
1174
1175         l = dma_read(CLNK_CTRL(lch_head));
1176         l &= ~(0x1f);
1177         l |= lch_queue;
1178         dma_write(l, CLNK_CTRL(lch_head));
1179
1180         l = dma_read(CLNK_CTRL(lch_queue));
1181         l &= ~(0x1f);
1182         l |= (dma_chan[lch_queue].next_linked_ch);
1183         dma_write(l, CLNK_CTRL(lch_queue));
1184 }
1185
1186 /**
1187  * @brief omap_request_dma_chain : Request a chain of DMA channels
1188  *
1189  * @param dev_id - Device id using the dma channel
1190  * @param dev_name - Device name
1191  * @param callback - Call back function
1192  * @chain_id -
1193  * @no_of_chans - Number of channels requested
1194  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1195  *                                            OMAP_DMA_DYNAMIC_CHAIN
1196  * @params - Channel parameters
1197  *
1198  * @return - Succes : 0
1199  *           Failure: -EINVAL/-ENOMEM
1200  */
1201 int omap_request_dma_chain(int dev_id, const char *dev_name,
1202                            void (*callback) (int chain_id, u16 ch_status,
1203                                              void *data),
1204                            int *chain_id, int no_of_chans, int chain_mode,
1205                            struct omap_dma_channel_params params)
1206 {
1207         int *channels;
1208         int i, err;
1209
1210         /* Is the chain mode valid ? */
1211         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1212                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1213                 printk(KERN_ERR "Invalid chain mode requested\n");
1214                 return -EINVAL;
1215         }
1216
1217         if (unlikely((no_of_chans < 1
1218                         || no_of_chans > dma_lch_count))) {
1219                 printk(KERN_ERR "Invalid Number of channels requested\n");
1220                 return -EINVAL;
1221         }
1222
1223         /* Allocate a queue to maintain the status of the channels
1224          * in the chain */
1225         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1226         if (channels == NULL) {
1227                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1228                 return -ENOMEM;
1229         }
1230
1231         /* request and reserve DMA channels for the chain */
1232         for (i = 0; i < no_of_chans; i++) {
1233                 err = omap_request_dma(dev_id, dev_name,
1234                                         callback, 0, &channels[i]);
1235                 if (err < 0) {
1236                         int j;
1237                         for (j = 0; j < i; j++)
1238                                 omap_free_dma(channels[j]);
1239                         kfree(channels);
1240                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1241                         return err;
1242                 }
1243                 dma_chan[channels[i]].prev_linked_ch = -1;
1244                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1245
1246                 /*
1247                  * Allowing client drivers to set common parameters now,
1248                  * so that later only relevant (src_start, dest_start
1249                  * and element count) can be set
1250                  */
1251                 omap_set_dma_params(channels[i], &params);
1252         }
1253
1254         *chain_id = channels[0];
1255         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1256         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1257         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1258         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1259
1260         for (i = 0; i < no_of_chans; i++)
1261                 dma_chan[channels[i]].chain_id = *chain_id;
1262
1263         /* Reset the Queue pointers */
1264         OMAP_DMA_CHAIN_QINIT(*chain_id);
1265
1266         /* Set up the chain */
1267         if (no_of_chans == 1)
1268                 create_dma_lch_chain(channels[0], channels[0]);
1269         else {
1270                 for (i = 0; i < (no_of_chans - 1); i++)
1271                         create_dma_lch_chain(channels[i], channels[i + 1]);
1272         }
1273
1274         return 0;
1275 }
1276 EXPORT_SYMBOL(omap_request_dma_chain);
1277
1278 /**
1279  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1280  * params after setting it. Dont do this while dma is running!!
1281  *
1282  * @param chain_id - Chained logical channel id.
1283  * @param params
1284  *
1285  * @return - Success : 0
1286  *           Failure : -EINVAL
1287  */
1288 int omap_modify_dma_chain_params(int chain_id,
1289                                 struct omap_dma_channel_params params)
1290 {
1291         int *channels;
1292         u32 i;
1293
1294         /* Check for input params */
1295         if (unlikely((chain_id < 0
1296                         || chain_id >= dma_lch_count))) {
1297                 printk(KERN_ERR "Invalid chain id\n");
1298                 return -EINVAL;
1299         }
1300
1301         /* Check if the chain exists */
1302         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1303                 printk(KERN_ERR "Chain doesn't exists\n");
1304                 return -EINVAL;
1305         }
1306         channels = dma_linked_lch[chain_id].linked_dmach_q;
1307
1308         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1309                 /*
1310                  * Allowing client drivers to set common parameters now,
1311                  * so that later only relevant (src_start, dest_start
1312                  * and element count) can be set
1313                  */
1314                 omap_set_dma_params(channels[i], &params);
1315         }
1316
1317         return 0;
1318 }
1319 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1320
1321 /**
1322  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1323  *
1324  * @param chain_id
1325  *
1326  * @return - Success : 0
1327  *           Failure : -EINVAL
1328  */
1329 int omap_free_dma_chain(int chain_id)
1330 {
1331         int *channels;
1332         u32 i;
1333
1334         /* Check for input params */
1335         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1336                 printk(KERN_ERR "Invalid chain id\n");
1337                 return -EINVAL;
1338         }
1339
1340         /* Check if the chain exists */
1341         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1342                 printk(KERN_ERR "Chain doesn't exists\n");
1343                 return -EINVAL;
1344         }
1345
1346         channels = dma_linked_lch[chain_id].linked_dmach_q;
1347         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1348                 dma_chan[channels[i]].next_linked_ch = -1;
1349                 dma_chan[channels[i]].prev_linked_ch = -1;
1350                 dma_chan[channels[i]].chain_id = -1;
1351                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1352                 omap_free_dma(channels[i]);
1353         }
1354
1355         kfree(channels);
1356
1357         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1358         dma_linked_lch[chain_id].chain_mode = -1;
1359         dma_linked_lch[chain_id].chain_state = -1;
1360
1361         return (0);
1362 }
1363 EXPORT_SYMBOL(omap_free_dma_chain);
1364
1365 /**
1366  * @brief omap_dma_chain_status - Check if the chain is in
1367  * active / inactive state.
1368  * @param chain_id
1369  *
1370  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1371  *           Failure : -EINVAL
1372  */
1373 int omap_dma_chain_status(int chain_id)
1374 {
1375         /* Check for input params */
1376         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1377                 printk(KERN_ERR "Invalid chain id\n");
1378                 return -EINVAL;
1379         }
1380
1381         /* Check if the chain exists */
1382         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1383                 printk(KERN_ERR "Chain doesn't exists\n");
1384                 return -EINVAL;
1385         }
1386         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1387                         dma_linked_lch[chain_id].q_count);
1388
1389         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1390                 return OMAP_DMA_CHAIN_INACTIVE;
1391
1392         return OMAP_DMA_CHAIN_ACTIVE;
1393 }
1394 EXPORT_SYMBOL(omap_dma_chain_status);
1395
1396 /**
1397  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1398  * set the params and start the transfer.
1399  *
1400  * @param chain_id
1401  * @param src_start - buffer start address
1402  * @param dest_start - Dest address
1403  * @param elem_count
1404  * @param frame_count
1405  * @param callbk_data - channel callback parameter data.
1406  *
1407  * @return  - Success : 0
1408  *            Failure: -EINVAL/-EBUSY
1409  */
1410 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1411                         int elem_count, int frame_count, void *callbk_data)
1412 {
1413         int *channels;
1414         u32 l, lch;
1415         int start_dma = 0;
1416
1417         /*
1418          * if buffer size is less than 1 then there is
1419          * no use of starting the chain
1420          */
1421         if (elem_count < 1) {
1422                 printk(KERN_ERR "Invalid buffer size\n");
1423                 return -EINVAL;
1424         }
1425
1426         /* Check for input params */
1427         if (unlikely((chain_id < 0
1428                         || chain_id >= dma_lch_count))) {
1429                 printk(KERN_ERR "Invalid chain id\n");
1430                 return -EINVAL;
1431         }
1432
1433         /* Check if the chain exists */
1434         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1435                 printk(KERN_ERR "Chain doesn't exist\n");
1436                 return -EINVAL;
1437         }
1438
1439         /* Check if all the channels in chain are in use */
1440         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1441                 return -EBUSY;
1442
1443         /* Frame count may be negative in case of indexed transfers */
1444         channels = dma_linked_lch[chain_id].linked_dmach_q;
1445
1446         /* Get a free channel */
1447         lch = channels[dma_linked_lch[chain_id].q_tail];
1448
1449         /* Store the callback data */
1450         dma_chan[lch].data = callbk_data;
1451
1452         /* Increment the q_tail */
1453         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1454
1455         /* Set the params to the free channel */
1456         if (src_start != 0)
1457                 dma_write(src_start, CSSA(lch));
1458         if (dest_start != 0)
1459                 dma_write(dest_start, CDSA(lch));
1460
1461         /* Write the buffer size */
1462         dma_write(elem_count, CEN(lch));
1463         dma_write(frame_count, CFN(lch));
1464
1465         /*
1466          * If the chain is dynamically linked,
1467          * then we may have to start the chain if its not active
1468          */
1469         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1470
1471                 /*
1472                  * In Dynamic chain, if the chain is not started,
1473                  * queue the channel
1474                  */
1475                 if (dma_linked_lch[chain_id].chain_state ==
1476                                                 DMA_CHAIN_NOTSTARTED) {
1477                         /* Enable the link in previous channel */
1478                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1479                                                                 DMA_CH_QUEUED)
1480                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1481                         dma_chan[lch].state = DMA_CH_QUEUED;
1482                 }
1483
1484                 /*
1485                  * Chain is already started, make sure its active,
1486                  * if not then start the chain
1487                  */
1488                 else {
1489                         start_dma = 1;
1490
1491                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1492                                                         DMA_CH_STARTED) {
1493                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1494                                 dma_chan[lch].state = DMA_CH_QUEUED;
1495                                 start_dma = 0;
1496                                 if (0 == ((1 << 7) & dma_read(
1497                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1498                                         disable_lnk(dma_chan[lch].
1499                                                     prev_linked_ch);
1500                                         pr_debug("\n prev ch is stopped\n");
1501                                         start_dma = 1;
1502                                 }
1503                         }
1504
1505                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1506                                                         == DMA_CH_QUEUED) {
1507                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1508                                 dma_chan[lch].state = DMA_CH_QUEUED;
1509                                 start_dma = 0;
1510                         }
1511                         omap_enable_channel_irq(lch);
1512
1513                         l = dma_read(CCR(lch));
1514
1515                         if ((0 == (l & (1 << 24))))
1516                                 l &= ~(1 << 25);
1517                         else
1518                                 l |= (1 << 25);
1519                         if (start_dma == 1) {
1520                                 if (0 == (l & (1 << 7))) {
1521                                         l |= (1 << 7);
1522                                         dma_chan[lch].state = DMA_CH_STARTED;
1523                                         pr_debug("starting %d\n", lch);
1524                                         dma_write(l, CCR(lch));
1525                                 } else
1526                                         start_dma = 0;
1527                         } else {
1528                                 if (0 == (l & (1 << 7)))
1529                                         dma_write(l, CCR(lch));
1530                         }
1531                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1532                 }
1533         }
1534
1535         return 0;
1536 }
1537 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1538
1539 /**
1540  * @brief omap_start_dma_chain_transfers - Start the chain
1541  *
1542  * @param chain_id
1543  *
1544  * @return - Success : 0
1545  *           Failure : -EINVAL/-EBUSY
1546  */
1547 int omap_start_dma_chain_transfers(int chain_id)
1548 {
1549         int *channels;
1550         u32 l, i;
1551
1552         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1553                 printk(KERN_ERR "Invalid chain id\n");
1554                 return -EINVAL;
1555         }
1556
1557         channels = dma_linked_lch[chain_id].linked_dmach_q;
1558
1559         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1560                 printk(KERN_ERR "Chain is already started\n");
1561                 return -EBUSY;
1562         }
1563
1564         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1565                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1566                                                                         i++) {
1567                         enable_lnk(channels[i]);
1568                         omap_enable_channel_irq(channels[i]);
1569                 }
1570         } else {
1571                 omap_enable_channel_irq(channels[0]);
1572         }
1573
1574         l = dma_read(CCR(channels[0]));
1575         l |= (1 << 7);
1576         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1577         dma_chan[channels[0]].state = DMA_CH_STARTED;
1578
1579         if ((0 == (l & (1 << 24))))
1580                 l &= ~(1 << 25);
1581         else
1582                 l |= (1 << 25);
1583         dma_write(l, CCR(channels[0]));
1584
1585         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1586
1587         return 0;
1588 }
1589 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1590
1591 /**
1592  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1593  *
1594  * @param chain_id
1595  *
1596  * @return - Success : 0
1597  *           Failure : EINVAL
1598  */
1599 int omap_stop_dma_chain_transfers(int chain_id)
1600 {
1601         int *channels;
1602         u32 l, i;
1603         u32 sys_cf;
1604
1605         /* Check for input params */
1606         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1607                 printk(KERN_ERR "Invalid chain id\n");
1608                 return -EINVAL;
1609         }
1610
1611         /* Check if the chain exists */
1612         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1613                 printk(KERN_ERR "Chain doesn't exists\n");
1614                 return -EINVAL;
1615         }
1616         channels = dma_linked_lch[chain_id].linked_dmach_q;
1617
1618         /*
1619          * DMA Errata:
1620          * Special programming model needed to disable DMA before end of block
1621          */
1622         sys_cf = dma_read(OCP_SYSCONFIG);
1623         l = sys_cf;
1624         /* Middle mode reg set no Standby */
1625         l &= ~((1 << 12)|(1 << 13));
1626         dma_write(l, OCP_SYSCONFIG);
1627
1628         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1629
1630                 /* Stop the Channel transmission */
1631                 l = dma_read(CCR(channels[i]));
1632                 l &= ~(1 << 7);
1633                 dma_write(l, CCR(channels[i]));
1634
1635                 /* Disable the link in all the channels */
1636                 disable_lnk(channels[i]);
1637                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1638
1639         }
1640         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1641
1642         /* Reset the Queue pointers */
1643         OMAP_DMA_CHAIN_QINIT(chain_id);
1644
1645         /* Errata - put in the old value */
1646         dma_write(sys_cf, OCP_SYSCONFIG);
1647
1648         return 0;
1649 }
1650 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1651
1652 /* Get the index of the ongoing DMA in chain */
1653 /**
1654  * @brief omap_get_dma_chain_index - Get the element and frame index
1655  * of the ongoing DMA in chain
1656  *
1657  * @param chain_id
1658  * @param ei - Element index
1659  * @param fi - Frame index
1660  *
1661  * @return - Success : 0
1662  *           Failure : -EINVAL
1663  */
1664 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1665 {
1666         int lch;
1667         int *channels;
1668
1669         /* Check for input params */
1670         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1671                 printk(KERN_ERR "Invalid chain id\n");
1672                 return -EINVAL;
1673         }
1674
1675         /* Check if the chain exists */
1676         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1677                 printk(KERN_ERR "Chain doesn't exists\n");
1678                 return -EINVAL;
1679         }
1680         if ((!ei) || (!fi))
1681                 return -EINVAL;
1682
1683         channels = dma_linked_lch[chain_id].linked_dmach_q;
1684
1685         /* Get the current channel */
1686         lch = channels[dma_linked_lch[chain_id].q_head];
1687
1688         *ei = dma_read(CCEN(lch));
1689         *fi = dma_read(CCFN(lch));
1690
1691         return 0;
1692 }
1693 EXPORT_SYMBOL(omap_get_dma_chain_index);
1694
1695 /**
1696  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1697  * ongoing DMA in chain
1698  *
1699  * @param chain_id
1700  *
1701  * @return - Success : Destination position
1702  *           Failure : -EINVAL
1703  */
1704 int omap_get_dma_chain_dst_pos(int chain_id)
1705 {
1706         int lch;
1707         int *channels;
1708
1709         /* Check for input params */
1710         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1711                 printk(KERN_ERR "Invalid chain id\n");
1712                 return -EINVAL;
1713         }
1714
1715         /* Check if the chain exists */
1716         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1717                 printk(KERN_ERR "Chain doesn't exists\n");
1718                 return -EINVAL;
1719         }
1720
1721         channels = dma_linked_lch[chain_id].linked_dmach_q;
1722
1723         /* Get the current channel */
1724         lch = channels[dma_linked_lch[chain_id].q_head];
1725
1726         return dma_read(CDAC(lch));
1727 }
1728 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1729
1730 /**
1731  * @brief omap_get_dma_chain_src_pos - Get the source position
1732  * of the ongoing DMA in chain
1733  * @param chain_id
1734  *
1735  * @return - Success : Destination position
1736  *           Failure : -EINVAL
1737  */
1738 int omap_get_dma_chain_src_pos(int chain_id)
1739 {
1740         int lch;
1741         int *channels;
1742
1743         /* Check for input params */
1744         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1745                 printk(KERN_ERR "Invalid chain id\n");
1746                 return -EINVAL;
1747         }
1748
1749         /* Check if the chain exists */
1750         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1751                 printk(KERN_ERR "Chain doesn't exists\n");
1752                 return -EINVAL;
1753         }
1754
1755         channels = dma_linked_lch[chain_id].linked_dmach_q;
1756
1757         /* Get the current channel */
1758         lch = channels[dma_linked_lch[chain_id].q_head];
1759
1760         return dma_read(CSAC(lch));
1761 }
1762 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1763 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1764
1765 /*----------------------------------------------------------------------------*/
1766
1767 #ifdef CONFIG_ARCH_OMAP1
1768
1769 static int omap1_dma_handle_ch(int ch)
1770 {
1771         u32 csr;
1772
1773         if (enable_1510_mode && ch >= 6) {
1774                 csr = dma_chan[ch].saved_csr;
1775                 dma_chan[ch].saved_csr = 0;
1776         } else
1777                 csr = dma_read(CSR(ch));
1778         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1779                 dma_chan[ch + 6].saved_csr = csr >> 7;
1780                 csr &= 0x7f;
1781         }
1782         if ((csr & 0x3f) == 0)
1783                 return 0;
1784         if (unlikely(dma_chan[ch].dev_id == -1)) {
1785                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1786                        "%d (CSR %04x)\n", ch, csr);
1787                 return 0;
1788         }
1789         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1790                 printk(KERN_WARNING "DMA timeout with device %d\n",
1791                        dma_chan[ch].dev_id);
1792         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1793                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1794                        "with device %d\n", dma_chan[ch].dev_id);
1795         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1796                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1797         if (likely(dma_chan[ch].callback != NULL))
1798                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1799
1800         return 1;
1801 }
1802
1803 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1804 {
1805         int ch = ((int) dev_id) - 1;
1806         int handled = 0;
1807
1808         for (;;) {
1809                 int handled_now = 0;
1810
1811                 handled_now += omap1_dma_handle_ch(ch);
1812                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1813                         handled_now += omap1_dma_handle_ch(ch + 6);
1814                 if (!handled_now)
1815                         break;
1816                 handled += handled_now;
1817         }
1818
1819         return handled ? IRQ_HANDLED : IRQ_NONE;
1820 }
1821
1822 #else
1823 #define omap1_dma_irq_handler   NULL
1824 #endif
1825
1826 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1827
1828 static int omap2_dma_handle_ch(int ch)
1829 {
1830         u32 status = dma_read(CSR(ch));
1831
1832         if (!status) {
1833                 if (printk_ratelimit())
1834                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1835                                 ch);
1836                 dma_write(1 << ch, IRQSTATUS_L0);
1837                 return 0;
1838         }
1839         if (unlikely(dma_chan[ch].dev_id == -1)) {
1840                 if (printk_ratelimit())
1841                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1842                                         "channel %d\n", status, ch);
1843                 return 0;
1844         }
1845         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1846                 printk(KERN_INFO
1847                        "DMA synchronization event drop occurred with device "
1848                        "%d\n", dma_chan[ch].dev_id);
1849         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
1850                 printk(KERN_INFO "DMA transaction error with device %d\n",
1851                        dma_chan[ch].dev_id);
1852         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1853                 printk(KERN_INFO "DMA secure error with device %d\n",
1854                        dma_chan[ch].dev_id);
1855         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1856                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1857                        dma_chan[ch].dev_id);
1858
1859         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1860         dma_write(1 << ch, IRQSTATUS_L0);
1861
1862         /* If the ch is not chained then chain_id will be -1 */
1863         if (dma_chan[ch].chain_id != -1) {
1864                 int chain_id = dma_chan[ch].chain_id;
1865                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1866                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1867                         dma_chan[dma_chan[ch].next_linked_ch].state =
1868                                                         DMA_CH_STARTED;
1869                 if (dma_linked_lch[chain_id].chain_mode ==
1870                                                 OMAP_DMA_DYNAMIC_CHAIN)
1871                         disable_lnk(ch);
1872
1873                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1874                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1875
1876                 status = dma_read(CSR(ch));
1877         }
1878
1879         if (likely(dma_chan[ch].callback != NULL))
1880                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1881
1882         dma_write(status, CSR(ch));
1883
1884         return 0;
1885 }
1886
1887 /* STATUS register count is from 1-32 while our is 0-31 */
1888 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1889 {
1890         u32 val;
1891         int i;
1892
1893         val = dma_read(IRQSTATUS_L0);
1894         if (val == 0) {
1895                 if (printk_ratelimit())
1896                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1897                 return IRQ_HANDLED;
1898         }
1899         for (i = 0; i < dma_lch_count && val != 0; i++) {
1900                 if (val & 1)
1901                         omap2_dma_handle_ch(i);
1902                 val >>= 1;
1903         }
1904
1905         return IRQ_HANDLED;
1906 }
1907
1908 static struct irqaction omap24xx_dma_irq = {
1909         .name = "DMA",
1910         .handler = omap2_dma_irq_handler,
1911         .flags = IRQF_DISABLED
1912 };
1913
1914 #else
1915 static struct irqaction omap24xx_dma_irq;
1916 #endif
1917
1918 /*----------------------------------------------------------------------------*/
1919
1920 static struct lcd_dma_info {
1921         spinlock_t lock;
1922         int reserved;
1923         void (*callback)(u16 status, void *data);
1924         void *cb_data;
1925
1926         int active;
1927         unsigned long addr, size;
1928         int rotate, data_type, xres, yres;
1929         int vxres;
1930         int mirror;
1931         int xscale, yscale;
1932         int ext_ctrl;
1933         int src_port;
1934         int single_transfer;
1935 } lcd_dma;
1936
1937 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1938                          int data_type)
1939 {
1940         lcd_dma.addr = addr;
1941         lcd_dma.data_type = data_type;
1942         lcd_dma.xres = fb_xres;
1943         lcd_dma.yres = fb_yres;
1944 }
1945 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1946
1947 void omap_set_lcd_dma_src_port(int port)
1948 {
1949         lcd_dma.src_port = port;
1950 }
1951
1952 void omap_set_lcd_dma_ext_controller(int external)
1953 {
1954         lcd_dma.ext_ctrl = external;
1955 }
1956 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1957
1958 void omap_set_lcd_dma_single_transfer(int single)
1959 {
1960         lcd_dma.single_transfer = single;
1961 }
1962 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1963
1964 void omap_set_lcd_dma_b1_rotation(int rotate)
1965 {
1966         if (omap_dma_in_1510_mode()) {
1967                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1968                 BUG();
1969                 return;
1970         }
1971         lcd_dma.rotate = rotate;
1972 }
1973 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1974
1975 void omap_set_lcd_dma_b1_mirror(int mirror)
1976 {
1977         if (omap_dma_in_1510_mode()) {
1978                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1979                 BUG();
1980         }
1981         lcd_dma.mirror = mirror;
1982 }
1983 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1984
1985 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1986 {
1987         if (omap_dma_in_1510_mode()) {
1988                 printk(KERN_ERR "DMA virtual resulotion is not supported "
1989                                 "in 1510 mode\n");
1990                 BUG();
1991         }
1992         lcd_dma.vxres = vxres;
1993 }
1994 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1995
1996 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1997 {
1998         if (omap_dma_in_1510_mode()) {
1999                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2000                 BUG();
2001         }
2002         lcd_dma.xscale = xscale;
2003         lcd_dma.yscale = yscale;
2004 }
2005 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2006
2007 static void set_b1_regs(void)
2008 {
2009         unsigned long top, bottom;
2010         int es;
2011         u16 w;
2012         unsigned long en, fn;
2013         long ei, fi;
2014         unsigned long vxres;
2015         unsigned int xscale, yscale;
2016
2017         switch (lcd_dma.data_type) {
2018         case OMAP_DMA_DATA_TYPE_S8:
2019                 es = 1;
2020                 break;
2021         case OMAP_DMA_DATA_TYPE_S16:
2022                 es = 2;
2023                 break;
2024         case OMAP_DMA_DATA_TYPE_S32:
2025                 es = 4;
2026                 break;
2027         default:
2028                 BUG();
2029                 return;
2030         }
2031
2032         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2033         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2034         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2035         BUG_ON(vxres < lcd_dma.xres);
2036
2037 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2038                 ((y) * vxres * yscale + (x) * xscale) * es)
2039 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2040
2041         switch (lcd_dma.rotate) {
2042         case 0:
2043                 if (!lcd_dma.mirror) {
2044                         top = PIXADDR(0, 0);
2045                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2046                         /* 1510 DMA requires the bottom address to be 2 more
2047                          * than the actual last memory access location. */
2048                         if (omap_dma_in_1510_mode() &&
2049                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2050                                         bottom += 2;
2051                         ei = PIXSTEP(0, 0, 1, 0);
2052                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2053                 } else {
2054                         top = PIXADDR(lcd_dma.xres - 1, 0);
2055                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2056                         ei = PIXSTEP(1, 0, 0, 0);
2057                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2058                 }
2059                 en = lcd_dma.xres;
2060                 fn = lcd_dma.yres;
2061                 break;
2062         case 90:
2063                 if (!lcd_dma.mirror) {
2064                         top = PIXADDR(0, lcd_dma.yres - 1);
2065                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2066                         ei = PIXSTEP(0, 1, 0, 0);
2067                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2068                 } else {
2069                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2070                         bottom = PIXADDR(0, 0);
2071                         ei = PIXSTEP(0, 1, 0, 0);
2072                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2073                 }
2074                 en = lcd_dma.yres;
2075                 fn = lcd_dma.xres;
2076                 break;
2077         case 180:
2078                 if (!lcd_dma.mirror) {
2079                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2080                         bottom = PIXADDR(0, 0);
2081                         ei = PIXSTEP(1, 0, 0, 0);
2082                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2083                 } else {
2084                         top = PIXADDR(0, lcd_dma.yres - 1);
2085                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2086                         ei = PIXSTEP(0, 0, 1, 0);
2087                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2088                 }
2089                 en = lcd_dma.xres;
2090                 fn = lcd_dma.yres;
2091                 break;
2092         case 270:
2093                 if (!lcd_dma.mirror) {
2094                         top = PIXADDR(lcd_dma.xres - 1, 0);
2095                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2096                         ei = PIXSTEP(0, 0, 0, 1);
2097                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2098                 } else {
2099                         top = PIXADDR(0, 0);
2100                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2101                         ei = PIXSTEP(0, 0, 0, 1);
2102                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2103                 }
2104                 en = lcd_dma.yres;
2105                 fn = lcd_dma.xres;
2106                 break;
2107         default:
2108                 BUG();
2109                 return; /* Suppress warning about uninitialized vars */
2110         }
2111
2112         if (omap_dma_in_1510_mode()) {
2113                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2114                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2115                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2116                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2117
2118                 return;
2119         }
2120
2121         /* 1610 regs */
2122         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2123         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2124         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2125         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2126
2127         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2128         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2129
2130         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2131         w &= ~0x03;
2132         w |= lcd_dma.data_type;
2133         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2134
2135         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2136         /* Always set the source port as SDRAM for now*/
2137         w &= ~(0x03 << 6);
2138         if (lcd_dma.callback != NULL)
2139                 w |= 1 << 1;            /* Block interrupt enable */
2140         else
2141                 w &= ~(1 << 1);
2142         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2143
2144         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2145               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2146                 return;
2147
2148         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2149         /* Set the double-indexed addressing mode */
2150         w |= (0x03 << 12);
2151         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2152
2153         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2154         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2155         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2156 }
2157
2158 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2159 {
2160         u16 w;
2161
2162         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2163         if (unlikely(!(w & (1 << 3)))) {
2164                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2165                 return IRQ_NONE;
2166         }
2167         /* Ack the IRQ */
2168         w |= (1 << 3);
2169         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2170         lcd_dma.active = 0;
2171         if (lcd_dma.callback != NULL)
2172                 lcd_dma.callback(w, lcd_dma.cb_data);
2173
2174         return IRQ_HANDLED;
2175 }
2176
2177 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2178                          void *data)
2179 {
2180         spin_lock_irq(&lcd_dma.lock);
2181         if (lcd_dma.reserved) {
2182                 spin_unlock_irq(&lcd_dma.lock);
2183                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2184                 BUG();
2185                 return -EBUSY;
2186         }
2187         lcd_dma.reserved = 1;
2188         spin_unlock_irq(&lcd_dma.lock);
2189         lcd_dma.callback = callback;
2190         lcd_dma.cb_data = data;
2191         lcd_dma.active = 0;
2192         lcd_dma.single_transfer = 0;
2193         lcd_dma.rotate = 0;
2194         lcd_dma.vxres = 0;
2195         lcd_dma.mirror = 0;
2196         lcd_dma.xscale = 0;
2197         lcd_dma.yscale = 0;
2198         lcd_dma.ext_ctrl = 0;
2199         lcd_dma.src_port = 0;
2200
2201         return 0;
2202 }
2203 EXPORT_SYMBOL(omap_request_lcd_dma);
2204
2205 void omap_free_lcd_dma(void)
2206 {
2207         spin_lock(&lcd_dma.lock);
2208         if (!lcd_dma.reserved) {
2209                 spin_unlock(&lcd_dma.lock);
2210                 printk(KERN_ERR "LCD DMA is not reserved\n");
2211                 BUG();
2212                 return;
2213         }
2214         if (!enable_1510_mode)
2215                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2216                             OMAP1610_DMA_LCD_CCR);
2217         lcd_dma.reserved = 0;
2218         spin_unlock(&lcd_dma.lock);
2219 }
2220 EXPORT_SYMBOL(omap_free_lcd_dma);
2221
2222 void omap_enable_lcd_dma(void)
2223 {
2224         u16 w;
2225
2226         /*
2227          * Set the Enable bit only if an external controller is
2228          * connected. Otherwise the OMAP internal controller will
2229          * start the transfer when it gets enabled.
2230          */
2231         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2232                 return;
2233
2234         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2235         w |= 1 << 8;
2236         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2237
2238         lcd_dma.active = 1;
2239
2240         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2241         w |= 1 << 7;
2242         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2243 }
2244 EXPORT_SYMBOL(omap_enable_lcd_dma);
2245
2246 void omap_setup_lcd_dma(void)
2247 {
2248         BUG_ON(lcd_dma.active);
2249         if (!enable_1510_mode) {
2250                 /* Set some reasonable defaults */
2251                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2252                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2253                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2254         }
2255         set_b1_regs();
2256         if (!enable_1510_mode) {
2257                 u16 w;
2258
2259                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2260                 /*
2261                  * If DMA was already active set the end_prog bit to have
2262                  * the programmed register set loaded into the active
2263                  * register set.
2264                  */
2265                 w |= 1 << 11;           /* End_prog */
2266                 if (!lcd_dma.single_transfer)
2267                         w |= (3 << 8);  /* Auto_init, repeat */
2268                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2269         }
2270 }
2271 EXPORT_SYMBOL(omap_setup_lcd_dma);
2272
2273 void omap_stop_lcd_dma(void)
2274 {
2275         u16 w;
2276
2277         lcd_dma.active = 0;
2278         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2279                 return;
2280
2281         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2282         w &= ~(1 << 7);
2283         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2284
2285         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2286         w &= ~(1 << 8);
2287         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2288 }
2289 EXPORT_SYMBOL(omap_stop_lcd_dma);
2290
2291 /*----------------------------------------------------------------------------*/
2292
2293 static int __init omap_init_dma(void)
2294 {
2295         int ch, r;
2296
2297         if (cpu_class_is_omap1()) {
2298                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
2299                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2300         } else if (cpu_is_omap24xx()) {
2301                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
2302                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2303         } else if (cpu_is_omap34xx()) {
2304                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
2305                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2306         } else {
2307                 pr_err("DMA init failed for unsupported omap\n");
2308                 return -ENODEV;
2309         }
2310
2311         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2312                                 GFP_KERNEL);
2313         if (!dma_chan)
2314                 return -ENOMEM;
2315
2316         if (cpu_class_is_omap2()) {
2317                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2318                                                 dma_lch_count, GFP_KERNEL);
2319                 if (!dma_linked_lch) {
2320                         kfree(dma_chan);
2321                         return -ENOMEM;
2322                 }
2323         }
2324
2325         if (cpu_is_omap15xx()) {
2326                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2327                 dma_chan_count = 9;
2328                 enable_1510_mode = 1;
2329         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2330                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2331                        dma_read(HW_ID));
2332                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2333                        (dma_read(CAPS_0_U) << 16) |
2334                        dma_read(CAPS_0_L),
2335                        (dma_read(CAPS_1_U) << 16) |
2336                        dma_read(CAPS_1_L),
2337                        dma_read(CAPS_2), dma_read(CAPS_3),
2338                        dma_read(CAPS_4));
2339                 if (!enable_1510_mode) {
2340                         u16 w;
2341
2342                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2343                         w = dma_read(GSCR);
2344                         w |= 1 << 3;
2345                         dma_write(w, GSCR);
2346                         dma_chan_count = 16;
2347                 } else
2348                         dma_chan_count = 9;
2349                 if (cpu_is_omap16xx()) {
2350                         u16 w;
2351
2352                         /* this would prevent OMAP sleep */
2353                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2354                         w &= ~(1 << 8);
2355                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2356                 }
2357         } else if (cpu_class_is_omap2()) {
2358                 u8 revision = dma_read(REVISION) & 0xff;
2359                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2360                        revision >> 4, revision & 0xf);
2361                 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2362         } else {
2363                 dma_chan_count = 0;
2364                 return 0;
2365         }
2366
2367         spin_lock_init(&lcd_dma.lock);
2368         spin_lock_init(&dma_chan_lock);
2369
2370         for (ch = 0; ch < dma_chan_count; ch++) {
2371                 omap_clear_dma(ch);
2372                 dma_chan[ch].dev_id = -1;
2373                 dma_chan[ch].next_lch = -1;
2374
2375                 if (ch >= 6 && enable_1510_mode)
2376                         continue;
2377
2378                 if (cpu_class_is_omap1()) {
2379                         /*
2380                          * request_irq() doesn't like dev_id (ie. ch) being
2381                          * zero, so we have to kludge around this.
2382                          */
2383                         r = request_irq(omap1_dma_irq[ch],
2384                                         omap1_dma_irq_handler, 0, "DMA",
2385                                         (void *) (ch + 1));
2386                         if (r != 0) {
2387                                 int i;
2388
2389                                 printk(KERN_ERR "unable to request IRQ %d "
2390                                        "for DMA (error %d)\n",
2391                                        omap1_dma_irq[ch], r);
2392                                 for (i = 0; i < ch; i++)
2393                                         free_irq(omap1_dma_irq[i],
2394                                                  (void *) (i + 1));
2395                                 return r;
2396                         }
2397                 }
2398         }
2399
2400         if (cpu_is_omap2430() || cpu_is_omap34xx())
2401                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2402                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2403
2404         if (cpu_class_is_omap2())
2405                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2406
2407         /* FIXME: Update LCD DMA to work on 24xx */
2408         if (cpu_class_is_omap1()) {
2409                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2410                                 "LCD DMA", NULL);
2411                 if (r != 0) {
2412                         int i;
2413
2414                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2415                                "(error %d)\n", r);
2416                         for (i = 0; i < dma_chan_count; i++)
2417                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2418                         return r;
2419                 }
2420         }
2421
2422         return 0;
2423 }
2424
2425 arch_initcall(omap_init_dma);
2426
2427