arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/io.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/hardware.h>
  32 #include <asm/dma.h>
  33
  34 #include <asm/arch/tc.h>
  35
  36 #undef DEBUG
  37
  38 #ifndef CONFIG_ARCH_OMAP1
  39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  40         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  41 };
  42
  43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  44 #endif
  45
  46 #define OMAP_DMA_ACTIVE                 0x01
  47 #define OMAP_DMA_CCR_EN                 (1 << 7)
  48 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  49
  50 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  51
  52 static int enable_1510_mode;
  53
  54 struct omap_dma_lch {
  55         int next_lch;
  56         int dev_id;
  57         u16 saved_csr;
  58         u16 enabled_irqs;
  59         const char *dev_name;
  60         void (*callback)(int lch, u16 ch_status, void *data);
  61         void *data;
  62
  63 #ifndef CONFIG_ARCH_OMAP1
  64         /* required for Dynamic chaining */
  65         int prev_linked_ch;
  66         int next_linked_ch;
  67         int state;
  68         int chain_id;
  69
  70         int status;
  71 #endif
  72         long flags;
  73 };
  74
  75 struct dma_link_info {
  76         int *linked_dmach_q;
  77         int no_of_lchs_linked;
  78
  79         int q_count;
  80         int q_tail;
  81         int q_head;
  82
  83         int chain_state;
  84         int chain_mode;
  85
  86 };
  87
  88 static struct dma_link_info *dma_linked_lch;
  89
  90 #ifndef CONFIG_ARCH_OMAP1
  91
  92 /* Chain handling macros */
  93 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  94         do {                                                            \
  95                 dma_linked_lch[chain_id].q_head =                       \
  96                 dma_linked_lch[chain_id].q_tail =                       \
  97                 dma_linked_lch[chain_id].q_count = 0;                   \
  98         } while (0)
  99 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 100                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 101                 dma_linked_lch[chain_id].q_count)
 102 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 103         do {                                                            \
 104                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 105                 dma_linked_lch[chain_id].q_count)                       \
 106         } while (0)
 107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 108                 (0 == dma_linked_lch[chain_id].q_count)
 109 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 110         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 112         do {                                                            \
 113                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 114                 dma_linked_lch[chain_id].q_count--;                     \
 115         } while (0)
 116
 117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 118         do {                                                            \
 119                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 120                 dma_linked_lch[chain_id].q_count++; \
 121         } while (0)
 122 #endif
 123
 124 static int dma_lch_count;
 125 static int dma_chan_count;
 126
 127 static spinlock_t dma_chan_lock;
 128 static struct omap_dma_lch *dma_chan;
 129 void __iomem *omap_dma_base;
 130
 131 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 132         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 133         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 134         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 135         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 136         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 137 };
 138
 139 static inline void disable_lnk(int lch);
 140 static void omap_disable_channel_irq(int lch);
 141 static inline void omap_enable_channel_irq(int lch);
 142
 143 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 144                                                 __func__);
 145
 146 #define dma_read(reg)                                                   \
 147 ({                                                                      \
 148         u32 __val;                                                      \
 149         if (cpu_class_is_omap1())                                       \
 150                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 151         else                                                            \
 152                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 153         __val;                                                          \
 154 })
 155
 156 #define dma_write(val, reg)                                             \
 157 ({                                                                      \
 158         if (cpu_class_is_omap1())                                       \
 159                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 160         else                                                            \
 161                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 162 })
 163
 164 #ifdef CONFIG_ARCH_OMAP15XX
 165 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 166 int omap_dma_in_1510_mode(void)
 167 {
 168         return enable_1510_mode;
 169 }
 170 #else
 171 #define omap_dma_in_1510_mode()         0
 172 #endif
 173
 174 #ifdef CONFIG_ARCH_OMAP1
 175 static inline int get_gdma_dev(int req)
 176 {
 177         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 178         int shift = ((req - 1) % 5) * 6;
 179
 180         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 181 }
 182
 183 static inline void set_gdma_dev(int req, int dev)
 184 {
 185         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 186         int shift = ((req - 1) % 5) * 6;
 187         u32 l;
 188
 189         l = omap_readl(reg);
 190         l &= ~(0x3f << shift);
 191         l |= (dev - 1) << shift;
 192         omap_writel(l, reg);
 193 }
 194 #else
 195 #define set_gdma_dev(req, dev)  do {} while (0)
 196 #endif
 197
 198 /* Omap1 only */
 199 static void clear_lch_regs(int lch)
 200 {
 201         int i;
 202         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 203
 204         for (i = 0; i < 0x2c; i += 2)
 205                 __raw_writew(0, lch_base + i);
 206 }
 207
 208 void omap_set_dma_priority(int lch, int dst_port, int priority)
 209 {
 210         unsigned long reg;
 211         u32 l;
 212
 213         if (cpu_class_is_omap1()) {
 214                 switch (dst_port) {
 215                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 216                         reg = OMAP_TC_OCPT1_PRIOR;
 217                         break;
 218                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 219                         reg = OMAP_TC_OCPT2_PRIOR;
 220                         break;
 221                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 222                         reg = OMAP_TC_EMIFF_PRIOR;
 223                         break;
 224                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 225                         reg = OMAP_TC_EMIFS_PRIOR;
 226                         break;
 227                 default:
 228                         BUG();
 229                         return;
 230                 }
 231                 l = omap_readl(reg);
 232                 l &= ~(0xf << 8);
 233                 l |= (priority & 0xf) << 8;
 234                 omap_writel(l, reg);
 235         }
 236
 237         if (cpu_class_is_omap2()) {
 238                 u32 ccr;
 239
 240                 ccr = dma_read(CCR(lch));
 241                 if (priority)
 242                         ccr |= (1 << 6);
 243                 else
 244                         ccr &= ~(1 << 6);
 245                 dma_write(ccr, CCR(lch));
 246         }
 247 }
 248 EXPORT_SYMBOL(omap_set_dma_priority);
 249
 250 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 251                                   int frame_count, int sync_mode,
 252                                   int dma_trigger, int src_or_dst_synch)
 253 {
 254         u32 l;
 255
 256         l = dma_read(CSDP(lch));
 257         l &= ~0x03;
 258         l |= data_type;
 259         dma_write(l, CSDP(lch));
 260
 261         if (cpu_class_is_omap1()) {
 262                 u16 ccr;
 263
 264                 ccr = dma_read(CCR(lch));
 265                 ccr &= ~(1 << 5);
 266                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 267                         ccr |= 1 << 5;
 268                 dma_write(ccr, CCR(lch));
 269
 270                 ccr = dma_read(CCR2(lch));
 271                 ccr &= ~(1 << 2);
 272                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 273                         ccr |= 1 << 2;
 274                 dma_write(ccr, CCR2(lch));
 275         }
 276
 277         if (cpu_class_is_omap2() && dma_trigger) {
 278                 u32 val;
 279
 280                 val = dma_read(CCR(lch));
 281                 val &= ~(3 << 19);
 282                 if (dma_trigger > 63)
 283                         val |= 1 << 20;
 284                 if (dma_trigger > 31)
 285                         val |= 1 << 19;
 286
 287                 val &= ~(0x1f);
 288                 val |= (dma_trigger & 0x1f);
 289
 290                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 291                         val |= 1 << 5;
 292                 else
 293                         val &= ~(1 << 5);
 294
 295                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 296                         val |= 1 << 18;
 297                 else
 298                         val &= ~(1 << 18);
 299
 300                 if (src_or_dst_synch)
 301                         val |= 1 << 24;         /* source synch */
 302                 else
 303                         val &= ~(1 << 24);      /* dest synch */
 304
 305                 dma_write(val, CCR(lch));
 306         }
 307
 308         dma_write(elem_count, CEN(lch));
 309         dma_write(frame_count, CFN(lch));
 310 }
 311 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 312
 313 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 314 {
 315         u16 w;
 316
 317         BUG_ON(omap_dma_in_1510_mode());
 318
 319         if (cpu_class_is_omap2()) {
 320                 REVISIT_24XX();
 321                 return;
 322         }
 323
 324         w = dma_read(CCR2(lch));
 325         w &= ~0x03;
 326
 327         switch (mode) {
 328         case OMAP_DMA_CONSTANT_FILL:
 329                 w |= 0x01;
 330                 break;
 331         case OMAP_DMA_TRANSPARENT_COPY:
 332                 w |= 0x02;
 333                 break;
 334         case OMAP_DMA_COLOR_DIS:
 335                 break;
 336         default:
 337                 BUG();
 338         }
 339         dma_write(w, CCR2(lch));
 340
 341         w = dma_read(LCH_CTRL(lch));
 342         w &= ~0x0f;
 343         /* Default is channel type 2D */
 344         if (mode) {
 345                 dma_write((u16)color, COLOR_L(lch));
 346                 dma_write((u16)(color >> 16), COLOR_U(lch));
 347                 w |= 1;         /* Channel type G */
 348         }
 349         dma_write(w, LCH_CTRL(lch));
 350 }
 351 EXPORT_SYMBOL(omap_set_dma_color_mode);
 352
 353 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 354 {
 355         if (cpu_class_is_omap2()) {
 356                 u32 csdp;
 357
 358                 csdp = dma_read(CSDP(lch));
 359                 csdp &= ~(0x3 << 16);
 360                 csdp |= (mode << 16);
 361                 dma_write(csdp, CSDP(lch));
 362         }
 363 }
 364 EXPORT_SYMBOL(omap_set_dma_write_mode);
 365
 366 /* Note that src_port is only for omap1 */
 367 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 368                              unsigned long src_start,
 369                              int src_ei, int src_fi)
 370 {
 371         u32 l;
 372
 373         if (cpu_class_is_omap1()) {
 374                 u16 w;
 375
 376                 w = dma_read(CSDP(lch));
 377                 w &= ~(0x1f << 2);
 378                 w |= src_port << 2;
 379                 dma_write(w, CSDP(lch));
 380         }
 381
 382         l = dma_read(CCR(lch));
 383         l &= ~(0x03 << 12);
 384         l |= src_amode << 12;
 385         dma_write(l, CCR(lch));
 386
 387         if (cpu_class_is_omap1()) {
 388                 dma_write(src_start >> 16, CSSA_U(lch));
 389                 dma_write((u16)src_start, CSSA_L(lch));
 390         }
 391
 392         if (cpu_class_is_omap2())
 393                 dma_write(src_start, CSSA(lch));
 394
 395         dma_write(src_ei, CSEI(lch));
 396         dma_write(src_fi, CSFI(lch));
 397 }
 398 EXPORT_SYMBOL(omap_set_dma_src_params);
 399
 400 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 401 {
 402         omap_set_dma_transfer_params(lch, params->data_type,
 403                                      params->elem_count, params->frame_count,
 404                                      params->sync_mode, params->trigger,
 405                                      params->src_or_dst_synch);
 406         omap_set_dma_src_params(lch, params->src_port,
 407                                 params->src_amode, params->src_start,
 408                                 params->src_ei, params->src_fi);
 409
 410         omap_set_dma_dest_params(lch, params->dst_port,
 411                                  params->dst_amode, params->dst_start,
 412                                  params->dst_ei, params->dst_fi);
 413         if (params->read_prio || params->write_prio)
 414                 omap_dma_set_prio_lch(lch, params->read_prio,
 415                                       params->write_prio);
 416 }
 417 EXPORT_SYMBOL(omap_set_dma_params);
 418
 419 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 420 {
 421         if (cpu_class_is_omap2())
 422                 return;
 423
 424         dma_write(eidx, CSEI(lch));
 425         dma_write(fidx, CSFI(lch));
 426 }
 427 EXPORT_SYMBOL(omap_set_dma_src_index);
 428
 429 void omap_set_dma_src_data_pack(int lch, int enable)
 430 {
 431         u32 l;
 432
 433         l = dma_read(CSDP(lch));
 434         l &= ~(1 << 6);
 435         if (enable)
 436                 l |= (1 << 6);
 437         dma_write(l, CSDP(lch));
 438 }
 439 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 440
 441 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 442 {
 443         unsigned int burst = 0;
 444         u32 l;
 445
 446         l = dma_read(CSDP(lch));
 447         l &= ~(0x03 << 7);
 448
 449         switch (burst_mode) {
 450         case OMAP_DMA_DATA_BURST_DIS:
 451                 break;
 452         case OMAP_DMA_DATA_BURST_4:
 453                 if (cpu_class_is_omap2())
 454                         burst = 0x1;
 455                 else
 456                         burst = 0x2;
 457                 break;
 458         case OMAP_DMA_DATA_BURST_8:
 459                 if (cpu_class_is_omap2()) {
 460                         burst = 0x2;
 461                         break;
 462                 }
 463                 /* not supported by current hardware on OMAP1
 464                  * w |= (0x03 << 7);
 465                  * fall through
 466                  */
 467         case OMAP_DMA_DATA_BURST_16:
 468                 if (cpu_class_is_omap2()) {
 469                         burst = 0x3;
 470                         break;
 471                 }
 472                 /* OMAP1 don't support burst 16
 473                  * fall through
 474                  */
 475         default:
 476                 BUG();
 477         }
 478
 479         l |= (burst << 7);
 480         dma_write(l, CSDP(lch));
 481 }
 482 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 483
 484 /* Note that dest_port is only for OMAP1 */
 485 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 486                               unsigned long dest_start,
 487                               int dst_ei, int dst_fi)
 488 {
 489         u32 l;
 490
 491         if (cpu_class_is_omap1()) {
 492                 l = dma_read(CSDP(lch));
 493                 l &= ~(0x1f << 9);
 494                 l |= dest_port << 9;
 495                 dma_write(l, CSDP(lch));
 496         }
 497
 498         l = dma_read(CCR(lch));
 499         l &= ~(0x03 << 14);
 500         l |= dest_amode << 14;
 501         dma_write(l, CCR(lch));
 502
 503         if (cpu_class_is_omap1()) {
 504                 dma_write(dest_start >> 16, CDSA_U(lch));
 505                 dma_write(dest_start, CDSA_L(lch));
 506         }
 507
 508         if (cpu_class_is_omap2())
 509                 dma_write(dest_start, CDSA(lch));
 510
 511         dma_write(dst_ei, CDEI(lch));
 512         dma_write(dst_fi, CDFI(lch));
 513 }
 514 EXPORT_SYMBOL(omap_set_dma_dest_params);
 515
 516 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 517 {
 518         if (cpu_class_is_omap2())
 519                 return;
 520
 521         dma_write(eidx, CDEI(lch));
 522         dma_write(fidx, CDFI(lch));
 523 }
 524 EXPORT_SYMBOL(omap_set_dma_dest_index);
 525
 526 void omap_set_dma_dest_data_pack(int lch, int enable)
 527 {
 528         u32 l;
 529
 530         l = dma_read(CSDP(lch));
 531         l &= ~(1 << 13);
 532         if (enable)
 533                 l |= 1 << 13;
 534         dma_write(l, CSDP(lch));
 535 }
 536 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 537
 538 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 539 {
 540         unsigned int burst = 0;
 541         u32 l;
 542
 543         l = dma_read(CSDP(lch));
 544         l &= ~(0x03 << 14);
 545
 546         switch (burst_mode) {
 547         case OMAP_DMA_DATA_BURST_DIS:
 548                 break;
 549         case OMAP_DMA_DATA_BURST_4:
 550                 if (cpu_class_is_omap2())
 551                         burst = 0x1;
 552                 else
 553                         burst = 0x2;
 554                 break;
 555         case OMAP_DMA_DATA_BURST_8:
 556                 if (cpu_class_is_omap2())
 557                         burst = 0x2;
 558                 else
 559                         burst = 0x3;
 560                 break;
 561         case OMAP_DMA_DATA_BURST_16:
 562                 if (cpu_class_is_omap2()) {
 563                         burst = 0x3;
 564                         break;
 565                 }
 566                 /* OMAP1 don't support burst 16
 567                  * fall through
 568                  */
 569         default:
 570                 printk(KERN_ERR "Invalid DMA burst mode\n");
 571                 BUG();
 572                 return;
 573         }
 574         l |= (burst << 14);
 575         dma_write(l, CSDP(lch));
 576 }
 577 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 578
 579 static inline void omap_enable_channel_irq(int lch)
 580 {
 581         u32 status;
 582
 583         /* Clear CSR */
 584         if (cpu_class_is_omap1())
 585                 status = dma_read(CSR(lch));
 586         else if (cpu_class_is_omap2())
 587                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 588
 589         /* Enable some nice interrupts. */
 590         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 591 }
 592
 593 static void omap_disable_channel_irq(int lch)
 594 {
 595         if (cpu_class_is_omap2())
 596                 dma_write(0, CICR(lch));
 597 }
 598
 599 void omap_enable_dma_irq(int lch, u16 bits)
 600 {
 601         dma_chan[lch].enabled_irqs |= bits;
 602 }
 603 EXPORT_SYMBOL(omap_enable_dma_irq);
 604
 605 void omap_disable_dma_irq(int lch, u16 bits)
 606 {
 607         dma_chan[lch].enabled_irqs &= ~bits;
 608 }
 609 EXPORT_SYMBOL(omap_disable_dma_irq);
 610
 611 static inline void enable_lnk(int lch)
 612 {
 613         u32 l;
 614
 615         l = dma_read(CLNK_CTRL(lch));
 616
 617         if (cpu_class_is_omap1())
 618                 l &= ~(1 << 14);
 619
 620         /* Set the ENABLE_LNK bits */
 621         if (dma_chan[lch].next_lch != -1)
 622                 l = dma_chan[lch].next_lch | (1 << 15);
 623
 624 #ifndef CONFIG_ARCH_OMAP1
 625         if (cpu_class_is_omap2())
 626                 if (dma_chan[lch].next_linked_ch != -1)
 627                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 628 #endif
 629
 630         dma_write(l, CLNK_CTRL(lch));
 631 }
 632
 633 static inline void disable_lnk(int lch)
 634 {
 635         u32 l;
 636
 637         l = dma_read(CLNK_CTRL(lch));
 638
 639         /* Disable interrupts */
 640         if (cpu_class_is_omap1()) {
 641                 dma_write(0, CICR(lch));
 642                 /* Set the STOP_LNK bit */
 643                 l |= 1 << 14;
 644         }
 645
 646         if (cpu_class_is_omap2()) {
 647                 omap_disable_channel_irq(lch);
 648                 /* Clear the ENABLE_LNK bit */
 649                 l &= ~(1 << 15);
 650         }
 651
 652         dma_write(l, CLNK_CTRL(lch));
 653         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 654 }
 655
 656 static inline void omap2_enable_irq_lch(int lch)
 657 {
 658         u32 val;
 659
 660         if (!cpu_class_is_omap2())
 661                 return;
 662
 663         val = dma_read(IRQENABLE_L0);
 664         val |= 1 << lch;
 665         dma_write(val, IRQENABLE_L0);
 666 }
 667
 668 int omap_request_dma(int dev_id, const char *dev_name,
 669                      void (*callback)(int lch, u16 ch_status, void *data),
 670                      void *data, int *dma_ch_out)
 671 {
 672         int ch, free_ch = -1;
 673         unsigned long flags;
 674         struct omap_dma_lch *chan;
 675
 676         spin_lock_irqsave(&dma_chan_lock, flags);
 677         for (ch = 0; ch < dma_chan_count; ch++) {
 678                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 679                         free_ch = ch;
 680                         if (dev_id == 0)
 681                                 break;
 682                 }
 683         }
 684         if (free_ch == -1) {
 685                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 686                 return -EBUSY;
 687         }
 688         chan = dma_chan + free_ch;
 689         chan->dev_id = dev_id;
 690
 691         if (cpu_class_is_omap1())
 692                 clear_lch_regs(free_ch);
 693
 694         if (cpu_class_is_omap2())
 695                 omap_clear_dma(free_ch);
 696
 697         spin_unlock_irqrestore(&dma_chan_lock, flags);
 698
 699         chan->dev_name = dev_name;
 700         chan->callback = callback;
 701         chan->data = data;
 702
 703 #ifndef CONFIG_ARCH_OMAP1
 704         if (cpu_class_is_omap2()) {
 705                 chan->chain_id = -1;
 706                 chan->next_linked_ch = -1;
 707         }
 708 #endif
 709
 710         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 711
 712         if (cpu_class_is_omap1())
 713                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 714         else if (cpu_class_is_omap2())
 715                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 716                         OMAP2_DMA_TRANS_ERR_IRQ;
 717
 718         if (cpu_is_omap16xx()) {
 719                 /* If the sync device is set, configure it dynamically. */
 720                 if (dev_id != 0) {
 721                         set_gdma_dev(free_ch + 1, dev_id);
 722                         dev_id = free_ch + 1;
 723                 }
 724                 /*
 725                  * Disable the 1510 compatibility mode and set the sync device
 726                  * id.
 727                  */
 728                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 729         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
 730                 dma_write(dev_id, CCR(free_ch));
 731         }
 732
 733         if (cpu_class_is_omap2()) {
 734                 omap2_enable_irq_lch(free_ch);
 735                 omap_enable_channel_irq(free_ch);
 736                 /* Clear the CSR register and IRQ status register */
 737                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 738                 dma_write(1 << free_ch, IRQSTATUS_L0);
 739         }
 740
 741         *dma_ch_out = free_ch;
 742
 743         return 0;
 744 }
 745 EXPORT_SYMBOL(omap_request_dma);
 746
 747 void omap_free_dma(int lch)
 748 {
 749         unsigned long flags;
 750
 751         spin_lock_irqsave(&dma_chan_lock, flags);
 752         if (dma_chan[lch].dev_id == -1) {
 753                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 754                        lch);
 755                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 756                 return;
 757         }
 758
 759         dma_chan[lch].dev_id = -1;
 760         dma_chan[lch].next_lch = -1;
 761         dma_chan[lch].callback = NULL;
 762         spin_unlock_irqrestore(&dma_chan_lock, flags);
 763
 764         if (cpu_class_is_omap1()) {
 765                 /* Disable all DMA interrupts for the channel. */
 766                 dma_write(0, CICR(lch));
 767                 /* Make sure the DMA transfer is stopped. */
 768                 dma_write(0, CCR(lch));
 769         }
 770
 771         if (cpu_class_is_omap2()) {
 772                 u32 val;
 773                 /* Disable interrupts */
 774                 val = dma_read(IRQENABLE_L0);
 775                 val &= ~(1 << lch);
 776                 dma_write(val, IRQENABLE_L0);
 777
 778                 /* Clear the CSR register and IRQ status register */
 779                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 780                 dma_write(1 << lch, IRQSTATUS_L0);
 781
 782                 /* Disable all DMA interrupts for the channel. */
 783                 dma_write(0, CICR(lch));
 784
 785                 /* Make sure the DMA transfer is stopped. */
 786                 dma_write(0, CCR(lch));
 787                 omap_clear_dma(lch);
 788         }
 789 }
 790 EXPORT_SYMBOL(omap_free_dma);
 791
 792 /**
 793  * @brief omap_dma_set_global_params : Set global priority settings for dma
 794  *
 795  * @param arb_rate
 796  * @param max_fifo_depth
 797  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 798  *                                                  DMA_THREAD_RESERVE_ONET
 799  *                                                  DMA_THREAD_RESERVE_TWOT
 800  *                                                  DMA_THREAD_RESERVE_THREET
 801  */
 802 void
 803 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 804 {
 805         u32 reg;
 806
 807         if (!cpu_class_is_omap2()) {
 808                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 809                 return;
 810         }
 811
 812         if (arb_rate == 0)
 813                 arb_rate = 1;
 814
 815         reg = (arb_rate & 0xff) << 16;
 816         reg |= (0xff & max_fifo_depth);
 817
 818         dma_write(reg, GCR);
 819 }
 820 EXPORT_SYMBOL(omap_dma_set_global_params);
 821
 822 /**
 823  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 824  *
 825  * @param lch
 826  * @param read_prio - Read priority
 827  * @param write_prio - Write priority
 828  * Both of the above can be set with one of the following values :
 829  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 830  */
 831 int
 832 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 833                       unsigned char write_prio)
 834 {
 835         u32 l;
 836
 837         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 838                 printk(KERN_ERR "Invalid channel id\n");
 839                 return -EINVAL;
 840         }
 841         l = dma_read(CCR(lch));
 842         l &= ~((1 << 6) | (1 << 26));
 843         if (cpu_is_omap2430() || cpu_is_omap34xx())
 844                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 845         else
 846                 l |= ((read_prio & 0x1) << 6);
 847
 848         dma_write(l, CCR(lch));
 849
 850         return 0;
 851 }
 852 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 853
 854 /*
 855  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 856  * through omap_start_dma(). Any buffers in flight are discarded.
 857  */
 858 void omap_clear_dma(int lch)
 859 {
 860         unsigned long flags;
 861
 862         local_irq_save(flags);
 863
 864         if (cpu_class_is_omap1()) {
 865                 u32 l;
 866
 867                 l = dma_read(CCR(lch));
 868                 l &= ~OMAP_DMA_CCR_EN;
 869                 dma_write(l, CCR(lch));
 870
 871                 /* Clear pending interrupts */
 872                 l = dma_read(CSR(lch));
 873         }
 874
 875         if (cpu_class_is_omap2()) {
 876                 int i;
 877                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 878                 for (i = 0; i < 0x44; i += 4)
 879                         __raw_writel(0, lch_base + i);
 880         }
 881
 882         local_irq_restore(flags);
 883 }
 884 EXPORT_SYMBOL(omap_clear_dma);
 885
 886 void omap_start_dma(int lch)
 887 {
 888         u32 l;
 889
 890         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 891                 int next_lch, cur_lch;
 892                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 893
 894                 dma_chan_link_map[lch] = 1;
 895                 /* Set the link register of the first channel */
 896                 enable_lnk(lch);
 897
 898                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 899                 cur_lch = dma_chan[lch].next_lch;
 900                 do {
 901                         next_lch = dma_chan[cur_lch].next_lch;
 902
 903                         /* The loop case: we've been here already */
 904                         if (dma_chan_link_map[cur_lch])
 905                                 break;
 906                         /* Mark the current channel */
 907                         dma_chan_link_map[cur_lch] = 1;
 908
 909                         enable_lnk(cur_lch);
 910                         omap_enable_channel_irq(cur_lch);
 911
 912                         cur_lch = next_lch;
 913                 } while (next_lch != -1);
 914         } else if (cpu_class_is_omap2()) {
 915                 /* Errata: Need to write lch even if not using chaining */
 916                 dma_write(lch, CLNK_CTRL(lch));
 917         }
 918
 919         omap_enable_channel_irq(lch);
 920
 921         l = dma_read(CCR(lch));
 922
 923         /*
 924          * Errata: On ES2.0 BUFFERING disable must be set.
 925          * This will always fail on ES1.0
 926          */
 927         if (cpu_is_omap24xx())
 928                 l |= OMAP_DMA_CCR_EN;
 929
 930         l |= OMAP_DMA_CCR_EN;
 931         dma_write(l, CCR(lch));
 932
 933         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 934 }
 935 EXPORT_SYMBOL(omap_start_dma);
 936
 937 void omap_stop_dma(int lch)
 938 {
 939         u32 l;
 940
 941         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 942                 int next_lch, cur_lch = lch;
 943                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 944
 945                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 946                 do {
 947                         /* The loop case: we've been here already */
 948                         if (dma_chan_link_map[cur_lch])
 949                                 break;
 950                         /* Mark the current channel */
 951                         dma_chan_link_map[cur_lch] = 1;
 952
 953                         disable_lnk(cur_lch);
 954
 955                         next_lch = dma_chan[cur_lch].next_lch;
 956                         cur_lch = next_lch;
 957                 } while (next_lch != -1);
 958
 959                 return;
 960         }
 961
 962         /* Disable all interrupts on the channel */
 963         if (cpu_class_is_omap1())
 964                 dma_write(0, CICR(lch));
 965
 966         l = dma_read(CCR(lch));
 967         l &= ~OMAP_DMA_CCR_EN;
 968         dma_write(l, CCR(lch));
 969
 970         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 971 }
 972 EXPORT_SYMBOL(omap_stop_dma);
 973
 974 /*
 975  * Allows changing the DMA callback function or data. This may be needed if
 976  * the driver shares a single DMA channel for multiple dma triggers.
 977  */
 978 int omap_set_dma_callback(int lch,
 979                           void (*callback)(int lch, u16 ch_status, void *data),
 980                           void *data)
 981 {
 982         unsigned long flags;
 983
 984         if (lch < 0)
 985                 return -ENODEV;
 986
 987         spin_lock_irqsave(&dma_chan_lock, flags);
 988         if (dma_chan[lch].dev_id == -1) {
 989                 printk(KERN_ERR "DMA callback for not set for free channel\n");
 990                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 991                 return -EINVAL;
 992         }
 993         dma_chan[lch].callback = callback;
 994         dma_chan[lch].data = data;
 995         spin_unlock_irqrestore(&dma_chan_lock, flags);
 996
 997         return 0;
 998 }
 999 EXPORT_SYMBOL(omap_set_dma_callback);
1000
1001 /*
1002  * Returns current physical source address for the given DMA channel.
1003  * If the channel is running the caller must disable interrupts prior calling
1004  * this function and process the returned value before re-enabling interrupt to
1005  * prevent races with the interrupt handler. Note that in continuous mode there
1006  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1007  * in incorrect return value.
1008  */
1009 dma_addr_t omap_get_dma_src_pos(int lch)
1010 {
1011         dma_addr_t offset = 0;
1012
1013         offset = dma_read(CSAC(lch));
1014
1015         /*
1016          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1017          * read before the DMA controller finished disabling the channel.
1018          */
1019         if (offset == 0)
1020                 offset = dma_read(CSAC(lch));
1021
1022         if (cpu_class_is_omap1())
1023                 offset |= (dma_read(CSSA_U(lch)) << 16);
1024
1025         return offset;
1026 }
1027 EXPORT_SYMBOL(omap_get_dma_src_pos);
1028
1029 /*
1030  * Returns current physical destination address for the given DMA channel.
1031  * If the channel is running the caller must disable interrupts prior calling
1032  * this function and process the returned value before re-enabling interrupt to
1033  * prevent races with the interrupt handler. Note that in continuous mode there
1034  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1035  * in incorrect return value.
1036  */
1037 dma_addr_t omap_get_dma_dst_pos(int lch)
1038 {
1039         dma_addr_t offset = 0;
1040
1041         offset = dma_read(CDAC(lch));
1042
1043         /*
1044          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1045          * read before the DMA controller finished disabling the channel.
1046          */
1047         if (offset == 0)
1048                 offset = dma_read(CDAC(lch));
1049
1050         if (cpu_class_is_omap1())
1051                 offset |= (dma_read(CDSA_U(lch)) << 16);
1052
1053         return offset;
1054 }
1055 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1056
1057 int omap_get_dma_active_status(int lch)
1058 {
1059         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1060 }
1061 EXPORT_SYMBOL(omap_get_dma_active_status);
1062
1063 int omap_dma_running(void)
1064 {
1065         int lch;
1066
1067         /* Check if LCD DMA is running */
1068         if (cpu_is_omap16xx())
1069                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1070                         return 1;
1071
1072         for (lch = 0; lch < dma_chan_count; lch++)
1073                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1074                         return 1;
1075
1076         return 0;
1077 }
1078
1079 /*
1080  * lch_queue DMA will start right after lch_head one is finished.
1081  * For this DMA link to start, you still need to start (see omap_start_dma)
1082  * the first one. That will fire up the entire queue.
1083  */
1084 void omap_dma_link_lch(int lch_head, int lch_queue)
1085 {
1086         if (omap_dma_in_1510_mode()) {
1087                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1088                 BUG();
1089                 return;
1090         }
1091
1092         if ((dma_chan[lch_head].dev_id == -1) ||
1093             (dma_chan[lch_queue].dev_id == -1)) {
1094                 printk(KERN_ERR "omap_dma: trying to link "
1095                        "non requested channels\n");
1096                 dump_stack();
1097         }
1098
1099         dma_chan[lch_head].next_lch = lch_queue;
1100 }
1101 EXPORT_SYMBOL(omap_dma_link_lch);
1102
1103 /*
1104  * Once the DMA queue is stopped, we can destroy it.
1105  */
1106 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1107 {
1108         if (omap_dma_in_1510_mode()) {
1109                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1110                 BUG();
1111                 return;
1112         }
1113
1114         if (dma_chan[lch_head].next_lch != lch_queue ||
1115             dma_chan[lch_head].next_lch == -1) {
1116                 printk(KERN_ERR "omap_dma: trying to unlink "
1117                        "non linked channels\n");
1118                 dump_stack();
1119         }
1120
1121         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1122             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1123                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1124                        "before unlinking\n");
1125                 dump_stack();
1126         }
1127
1128         dma_chan[lch_head].next_lch = -1;
1129 }
1130 EXPORT_SYMBOL(omap_dma_unlink_lch);
1131
1132 /*----------------------------------------------------------------------------*/
1133
1134 #ifndef CONFIG_ARCH_OMAP1
1135 /* Create chain of DMA channesls */
1136 static void create_dma_lch_chain(int lch_head, int lch_queue)
1137 {
1138         u32 l;
1139
1140         /* Check if this is the first link in chain */
1141         if (dma_chan[lch_head].next_linked_ch == -1) {
1142                 dma_chan[lch_head].next_linked_ch = lch_queue;
1143                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1144                 dma_chan[lch_queue].next_linked_ch = lch_head;
1145                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1146         }
1147
1148         /* a link exists, link the new channel in circular chain */
1149         else {
1150                 dma_chan[lch_queue].next_linked_ch =
1151                                         dma_chan[lch_head].next_linked_ch;
1152                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1153                 dma_chan[lch_head].next_linked_ch = lch_queue;
1154                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1155                                         lch_queue;
1156         }
1157
1158         l = dma_read(CLNK_CTRL(lch_head));
1159         l &= ~(0x1f);
1160         l |= lch_queue;
1161         dma_write(l, CLNK_CTRL(lch_head));
1162
1163         l = dma_read(CLNK_CTRL(lch_queue));
1164         l &= ~(0x1f);
1165         l |= (dma_chan[lch_queue].next_linked_ch);
1166         dma_write(l, CLNK_CTRL(lch_queue));
1167 }
1168
1169 /**
1170  * @brief omap_request_dma_chain : Request a chain of DMA channels
1171  *
1172  * @param dev_id - Device id using the dma channel
1173  * @param dev_name - Device name
1174  * @param callback - Call back function
1175  * @chain_id -
1176  * @no_of_chans - Number of channels requested
1177  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1178  *                                            OMAP_DMA_DYNAMIC_CHAIN
1179  * @params - Channel parameters
1180  *
1181  * @return - Succes : 0
1182  *           Failure: -EINVAL/-ENOMEM
1183  */
1184 int omap_request_dma_chain(int dev_id, const char *dev_name,
1185                            void (*callback) (int chain_id, u16 ch_status,
1186                                              void *data),
1187                            int *chain_id, int no_of_chans, int chain_mode,
1188                            struct omap_dma_channel_params params)
1189 {
1190         int *channels;
1191         int i, err;
1192
1193         /* Is the chain mode valid ? */
1194         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1195                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1196                 printk(KERN_ERR "Invalid chain mode requested\n");
1197                 return -EINVAL;
1198         }
1199
1200         if (unlikely((no_of_chans < 1
1201                         || no_of_chans > dma_lch_count))) {
1202                 printk(KERN_ERR "Invalid Number of channels requested\n");
1203                 return -EINVAL;
1204         }
1205
1206         /* Allocate a queue to maintain the status of the channels
1207          * in the chain */
1208         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1209         if (channels == NULL) {
1210                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1211                 return -ENOMEM;
1212         }
1213
1214         /* request and reserve DMA channels for the chain */
1215         for (i = 0; i < no_of_chans; i++) {
1216                 err = omap_request_dma(dev_id, dev_name,
1217                                         callback, 0, &channels[i]);
1218                 if (err < 0) {
1219                         int j;
1220                         for (j = 0; j < i; j++)
1221                                 omap_free_dma(channels[j]);
1222                         kfree(channels);
1223                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1224                         return err;
1225                 }
1226                 dma_chan[channels[i]].prev_linked_ch = -1;
1227                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1228
1229                 /*
1230                  * Allowing client drivers to set common parameters now,
1231                  * so that later only relevant (src_start, dest_start
1232                  * and element count) can be set
1233                  */
1234                 omap_set_dma_params(channels[i], &params);
1235         }
1236
1237         *chain_id = channels[0];
1238         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1239         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1240         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1241         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1242
1243         for (i = 0; i < no_of_chans; i++)
1244                 dma_chan[channels[i]].chain_id = *chain_id;
1245
1246         /* Reset the Queue pointers */
1247         OMAP_DMA_CHAIN_QINIT(*chain_id);
1248
1249         /* Set up the chain */
1250         if (no_of_chans == 1)
1251                 create_dma_lch_chain(channels[0], channels[0]);
1252         else {
1253                 for (i = 0; i < (no_of_chans - 1); i++)
1254                         create_dma_lch_chain(channels[i], channels[i + 1]);
1255         }
1256
1257         return 0;
1258 }
1259 EXPORT_SYMBOL(omap_request_dma_chain);
1260
1261 /**
1262  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1263  * params after setting it. Dont do this while dma is running!!
1264  *
1265  * @param chain_id - Chained logical channel id.
1266  * @param params
1267  *
1268  * @return - Success : 0
1269  *           Failure : -EINVAL
1270  */
1271 int omap_modify_dma_chain_params(int chain_id,
1272                                 struct omap_dma_channel_params params)
1273 {
1274         int *channels;
1275         u32 i;
1276
1277         /* Check for input params */
1278         if (unlikely((chain_id < 0
1279                         || chain_id >= dma_lch_count))) {
1280                 printk(KERN_ERR "Invalid chain id\n");
1281                 return -EINVAL;
1282         }
1283
1284         /* Check if the chain exists */
1285         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1286                 printk(KERN_ERR "Chain doesn't exists\n");
1287                 return -EINVAL;
1288         }
1289         channels = dma_linked_lch[chain_id].linked_dmach_q;
1290
1291         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1292                 /*
1293                  * Allowing client drivers to set common parameters now,
1294                  * so that later only relevant (src_start, dest_start
1295                  * and element count) can be set
1296                  */
1297                 omap_set_dma_params(channels[i], &params);
1298         }
1299
1300         return 0;
1301 }
1302 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1303
1304 /**
1305  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1306  *
1307  * @param chain_id
1308  *
1309  * @return - Success : 0
1310  *           Failure : -EINVAL
1311  */
1312 int omap_free_dma_chain(int chain_id)
1313 {
1314         int *channels;
1315         u32 i;
1316
1317         /* Check for input params */
1318         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1319                 printk(KERN_ERR "Invalid chain id\n");
1320                 return -EINVAL;
1321         }
1322
1323         /* Check if the chain exists */
1324         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1325                 printk(KERN_ERR "Chain doesn't exists\n");
1326                 return -EINVAL;
1327         }
1328
1329         channels = dma_linked_lch[chain_id].linked_dmach_q;
1330         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1331                 dma_chan[channels[i]].next_linked_ch = -1;
1332                 dma_chan[channels[i]].prev_linked_ch = -1;
1333                 dma_chan[channels[i]].chain_id = -1;
1334                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1335                 omap_free_dma(channels[i]);
1336         }
1337
1338         kfree(channels);
1339
1340         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1341         dma_linked_lch[chain_id].chain_mode = -1;
1342         dma_linked_lch[chain_id].chain_state = -1;
1343
1344         return (0);
1345 }
1346 EXPORT_SYMBOL(omap_free_dma_chain);
1347
1348 /**
1349  * @brief omap_dma_chain_status - Check if the chain is in
1350  * active / inactive state.
1351  * @param chain_id
1352  *
1353  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1354  *           Failure : -EINVAL
1355  */
1356 int omap_dma_chain_status(int chain_id)
1357 {
1358         /* Check for input params */
1359         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1360                 printk(KERN_ERR "Invalid chain id\n");
1361                 return -EINVAL;
1362         }
1363
1364         /* Check if the chain exists */
1365         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1366                 printk(KERN_ERR "Chain doesn't exists\n");
1367                 return -EINVAL;
1368         }
1369         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1370                         dma_linked_lch[chain_id].q_count);
1371
1372         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1373                 return OMAP_DMA_CHAIN_INACTIVE;
1374
1375         return OMAP_DMA_CHAIN_ACTIVE;
1376 }
1377 EXPORT_SYMBOL(omap_dma_chain_status);
1378
1379 /**
1380  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1381  * set the params and start the transfer.
1382  *
1383  * @param chain_id
1384  * @param src_start - buffer start address
1385  * @param dest_start - Dest address
1386  * @param elem_count
1387  * @param frame_count
1388  * @param callbk_data - channel callback parameter data.
1389  *
1390  * @return  - Success : 0
1391  *            Failure: -EINVAL/-EBUSY
1392  */
1393 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1394                         int elem_count, int frame_count, void *callbk_data)
1395 {
1396         int *channels;
1397         u32 l, lch;
1398         int start_dma = 0;
1399
1400         /*
1401          * if buffer size is less than 1 then there is
1402          * no use of starting the chain
1403          */
1404         if (elem_count < 1) {
1405                 printk(KERN_ERR "Invalid buffer size\n");
1406                 return -EINVAL;
1407         }
1408
1409         /* Check for input params */
1410         if (unlikely((chain_id < 0
1411                         || chain_id >= dma_lch_count))) {
1412                 printk(KERN_ERR "Invalid chain id\n");
1413                 return -EINVAL;
1414         }
1415
1416         /* Check if the chain exists */
1417         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1418                 printk(KERN_ERR "Chain doesn't exist\n");
1419                 return -EINVAL;
1420         }
1421
1422         /* Check if all the channels in chain are in use */
1423         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1424                 return -EBUSY;
1425
1426         /* Frame count may be negative in case of indexed transfers */
1427         channels = dma_linked_lch[chain_id].linked_dmach_q;
1428
1429         /* Get a free channel */
1430         lch = channels[dma_linked_lch[chain_id].q_tail];
1431
1432         /* Store the callback data */
1433         dma_chan[lch].data = callbk_data;
1434
1435         /* Increment the q_tail */
1436         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1437
1438         /* Set the params to the free channel */
1439         if (src_start != 0)
1440                 dma_write(src_start, CSSA(lch));
1441         if (dest_start != 0)
1442                 dma_write(dest_start, CDSA(lch));
1443
1444         /* Write the buffer size */
1445         dma_write(elem_count, CEN(lch));
1446         dma_write(frame_count, CFN(lch));
1447
1448         /*
1449          * If the chain is dynamically linked,
1450          * then we may have to start the chain if its not active
1451          */
1452         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1453
1454                 /*
1455                  * In Dynamic chain, if the chain is not started,
1456                  * queue the channel
1457                  */
1458                 if (dma_linked_lch[chain_id].chain_state ==
1459                                                 DMA_CHAIN_NOTSTARTED) {
1460                         /* Enable the link in previous channel */
1461                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1462                                                                 DMA_CH_QUEUED)
1463                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1464                         dma_chan[lch].state = DMA_CH_QUEUED;
1465                 }
1466
1467                 /*
1468                  * Chain is already started, make sure its active,
1469                  * if not then start the chain
1470                  */
1471                 else {
1472                         start_dma = 1;
1473
1474                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1475                                                         DMA_CH_STARTED) {
1476                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1477                                 dma_chan[lch].state = DMA_CH_QUEUED;
1478                                 start_dma = 0;
1479                                 if (0 == ((1 << 7) & dma_read(
1480                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1481                                         disable_lnk(dma_chan[lch].
1482                                                     prev_linked_ch);
1483                                         pr_debug("\n prev ch is stopped\n");
1484                                         start_dma = 1;
1485                                 }
1486                         }
1487
1488                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1489                                                         == DMA_CH_QUEUED) {
1490                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1491                                 dma_chan[lch].state = DMA_CH_QUEUED;
1492                                 start_dma = 0;
1493                         }
1494                         omap_enable_channel_irq(lch);
1495
1496                         l = dma_read(CCR(lch));
1497
1498                         if ((0 == (l & (1 << 24))))
1499                                 l &= ~(1 << 25);
1500                         else
1501                                 l |= (1 << 25);
1502                         if (start_dma == 1) {
1503                                 if (0 == (l & (1 << 7))) {
1504                                         l |= (1 << 7);
1505                                         dma_chan[lch].state = DMA_CH_STARTED;
1506                                         pr_debug("starting %d\n", lch);
1507                                         dma_write(l, CCR(lch));
1508                                 } else
1509                                         start_dma = 0;
1510                         } else {
1511                                 if (0 == (l & (1 << 7)))
1512                                         dma_write(l, CCR(lch));
1513                         }
1514                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1515                 }
1516         }
1517
1518         return 0;
1519 }
1520 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1521
1522 /**
1523  * @brief omap_start_dma_chain_transfers - Start the chain
1524  *
1525  * @param chain_id
1526  *
1527  * @return - Success : 0
1528  *           Failure : -EINVAL/-EBUSY
1529  */
1530 int omap_start_dma_chain_transfers(int chain_id)
1531 {
1532         int *channels;
1533         u32 l, i;
1534
1535         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1536                 printk(KERN_ERR "Invalid chain id\n");
1537                 return -EINVAL;
1538         }
1539
1540         channels = dma_linked_lch[chain_id].linked_dmach_q;
1541
1542         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1543                 printk(KERN_ERR "Chain is already started\n");
1544                 return -EBUSY;
1545         }
1546
1547         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1548                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1549                                                                         i++) {
1550                         enable_lnk(channels[i]);
1551                         omap_enable_channel_irq(channels[i]);
1552                 }
1553         } else {
1554                 omap_enable_channel_irq(channels[0]);
1555         }
1556
1557         l = dma_read(CCR(channels[0]));
1558         l |= (1 << 7);
1559         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1560         dma_chan[channels[0]].state = DMA_CH_STARTED;
1561
1562         if ((0 == (l & (1 << 24))))
1563                 l &= ~(1 << 25);
1564         else
1565                 l |= (1 << 25);
1566         dma_write(l, CCR(channels[0]));
1567
1568         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1569
1570         return 0;
1571 }
1572 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1573
1574 /**
1575  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1576  *
1577  * @param chain_id
1578  *
1579  * @return - Success : 0
1580  *           Failure : EINVAL
1581  */
1582 int omap_stop_dma_chain_transfers(int chain_id)
1583 {
1584         int *channels;
1585         u32 l, i;
1586         u32 sys_cf;
1587
1588         /* Check for input params */
1589         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1590                 printk(KERN_ERR "Invalid chain id\n");
1591                 return -EINVAL;
1592         }
1593
1594         /* Check if the chain exists */
1595         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1596                 printk(KERN_ERR "Chain doesn't exists\n");
1597                 return -EINVAL;
1598         }
1599         channels = dma_linked_lch[chain_id].linked_dmach_q;
1600
1601         /*
1602          * DMA Errata:
1603          * Special programming model needed to disable DMA before end of block
1604          */
1605         sys_cf = dma_read(OCP_SYSCONFIG);
1606         l = sys_cf;
1607         /* Middle mode reg set no Standby */
1608         l &= ~((1 << 12)|(1 << 13));
1609         dma_write(l, OCP_SYSCONFIG);
1610
1611         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1612
1613                 /* Stop the Channel transmission */
1614                 l = dma_read(CCR(channels[i]));
1615                 l &= ~(1 << 7);
1616                 dma_write(l, CCR(channels[i]));
1617
1618                 /* Disable the link in all the channels */
1619                 disable_lnk(channels[i]);
1620                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1621
1622         }
1623         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1624
1625         /* Reset the Queue pointers */
1626         OMAP_DMA_CHAIN_QINIT(chain_id);
1627
1628         /* Errata - put in the old value */
1629         dma_write(sys_cf, OCP_SYSCONFIG);
1630
1631         return 0;
1632 }
1633 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1634
1635 /* Get the index of the ongoing DMA in chain */
1636 /**
1637  * @brief omap_get_dma_chain_index - Get the element and frame index
1638  * of the ongoing DMA in chain
1639  *
1640  * @param chain_id
1641  * @param ei - Element index
1642  * @param fi - Frame index
1643  *
1644  * @return - Success : 0
1645  *           Failure : -EINVAL
1646  */
1647 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1648 {
1649         int lch;
1650         int *channels;
1651
1652         /* Check for input params */
1653         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1654                 printk(KERN_ERR "Invalid chain id\n");
1655                 return -EINVAL;
1656         }
1657
1658         /* Check if the chain exists */
1659         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1660                 printk(KERN_ERR "Chain doesn't exists\n");
1661                 return -EINVAL;
1662         }
1663         if ((!ei) || (!fi))
1664                 return -EINVAL;
1665
1666         channels = dma_linked_lch[chain_id].linked_dmach_q;
1667
1668         /* Get the current channel */
1669         lch = channels[dma_linked_lch[chain_id].q_head];
1670
1671         *ei = dma_read(CCEN(lch));
1672         *fi = dma_read(CCFN(lch));
1673
1674         return 0;
1675 }
1676 EXPORT_SYMBOL(omap_get_dma_chain_index);
1677
1678 /**
1679  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1680  * ongoing DMA in chain
1681  *
1682  * @param chain_id
1683  *
1684  * @return - Success : Destination position
1685  *           Failure : -EINVAL
1686  */
1687 int omap_get_dma_chain_dst_pos(int chain_id)
1688 {
1689         int lch;
1690         int *channels;
1691
1692         /* Check for input params */
1693         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1694                 printk(KERN_ERR "Invalid chain id\n");
1695                 return -EINVAL;
1696         }
1697
1698         /* Check if the chain exists */
1699         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1700                 printk(KERN_ERR "Chain doesn't exists\n");
1701                 return -EINVAL;
1702         }
1703
1704         channels = dma_linked_lch[chain_id].linked_dmach_q;
1705
1706         /* Get the current channel */
1707         lch = channels[dma_linked_lch[chain_id].q_head];
1708
1709         return dma_read(CDAC(lch));
1710 }
1711 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1712
1713 /**
1714  * @brief omap_get_dma_chain_src_pos - Get the source position
1715  * of the ongoing DMA in chain
1716  * @param chain_id
1717  *
1718  * @return - Success : Destination position
1719  *           Failure : -EINVAL
1720  */
1721 int omap_get_dma_chain_src_pos(int chain_id)
1722 {
1723         int lch;
1724         int *channels;
1725
1726         /* Check for input params */
1727         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1728                 printk(KERN_ERR "Invalid chain id\n");
1729                 return -EINVAL;
1730         }
1731
1732         /* Check if the chain exists */
1733         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1734                 printk(KERN_ERR "Chain doesn't exists\n");
1735                 return -EINVAL;
1736         }
1737
1738         channels = dma_linked_lch[chain_id].linked_dmach_q;
1739
1740         /* Get the current channel */
1741         lch = channels[dma_linked_lch[chain_id].q_head];
1742
1743         return dma_read(CSAC(lch));
1744 }
1745 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1746 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1747
1748 /*----------------------------------------------------------------------------*/
1749
1750 #ifdef CONFIG_ARCH_OMAP1
1751
1752 static int omap1_dma_handle_ch(int ch)
1753 {
1754         u32 csr;
1755
1756         if (enable_1510_mode && ch >= 6) {
1757                 csr = dma_chan[ch].saved_csr;
1758                 dma_chan[ch].saved_csr = 0;
1759         } else
1760                 csr = dma_read(CSR(ch));
1761         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1762                 dma_chan[ch + 6].saved_csr = csr >> 7;
1763                 csr &= 0x7f;
1764         }
1765         if ((csr & 0x3f) == 0)
1766                 return 0;
1767         if (unlikely(dma_chan[ch].dev_id == -1)) {
1768                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1769                        "%d (CSR %04x)\n", ch, csr);
1770                 return 0;
1771         }
1772         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1773                 printk(KERN_WARNING "DMA timeout with device %d\n",
1774                        dma_chan[ch].dev_id);
1775         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1776                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1777                        "with device %d\n", dma_chan[ch].dev_id);
1778         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1779                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1780         if (likely(dma_chan[ch].callback != NULL))
1781                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1782
1783         return 1;
1784 }
1785
1786 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1787 {
1788         int ch = ((int) dev_id) - 1;
1789         int handled = 0;
1790
1791         for (;;) {
1792                 int handled_now = 0;
1793
1794                 handled_now += omap1_dma_handle_ch(ch);
1795                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1796                         handled_now += omap1_dma_handle_ch(ch + 6);
1797                 if (!handled_now)
1798                         break;
1799                 handled += handled_now;
1800         }
1801
1802         return handled ? IRQ_HANDLED : IRQ_NONE;
1803 }
1804
1805 #else
1806 #define omap1_dma_irq_handler   NULL
1807 #endif
1808
1809 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1810
1811 static int omap2_dma_handle_ch(int ch)
1812 {
1813         u32 status = dma_read(CSR(ch));
1814
1815         if (!status) {
1816                 if (printk_ratelimit())
1817                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1818                                 ch);
1819                 dma_write(1 << ch, IRQSTATUS_L0);
1820                 return 0;
1821         }
1822         if (unlikely(dma_chan[ch].dev_id == -1)) {
1823                 if (printk_ratelimit())
1824                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1825                                         "channel %d\n", status, ch);
1826                 return 0;
1827         }
1828         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1829                 printk(KERN_INFO
1830                        "DMA synchronization event drop occurred with device "
1831                        "%d\n", dma_chan[ch].dev_id);
1832         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
1833                 printk(KERN_INFO "DMA transaction error with device %d\n",
1834                        dma_chan[ch].dev_id);
1835         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1836                 printk(KERN_INFO "DMA secure error with device %d\n",
1837                        dma_chan[ch].dev_id);
1838         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1839                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1840                        dma_chan[ch].dev_id);
1841
1842         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1843         dma_write(1 << ch, IRQSTATUS_L0);
1844
1845         /* If the ch is not chained then chain_id will be -1 */
1846         if (dma_chan[ch].chain_id != -1) {
1847                 int chain_id = dma_chan[ch].chain_id;
1848                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1849                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1850                         dma_chan[dma_chan[ch].next_linked_ch].state =
1851                                                         DMA_CH_STARTED;
1852                 if (dma_linked_lch[chain_id].chain_mode ==
1853                                                 OMAP_DMA_DYNAMIC_CHAIN)
1854                         disable_lnk(ch);
1855
1856                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1857                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1858
1859                 status = dma_read(CSR(ch));
1860         }
1861
1862         if (likely(dma_chan[ch].callback != NULL))
1863                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1864
1865         dma_write(status, CSR(ch));
1866
1867         return 0;
1868 }
1869
1870 /* STATUS register count is from 1-32 while our is 0-31 */
1871 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1872 {
1873         u32 val;
1874         int i;
1875
1876         val = dma_read(IRQSTATUS_L0);
1877         if (val == 0) {
1878                 if (printk_ratelimit())
1879                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1880                 return IRQ_HANDLED;
1881         }
1882         for (i = 0; i < dma_lch_count && val != 0; i++) {
1883                 if (val & 1)
1884                         omap2_dma_handle_ch(i);
1885                 val >>= 1;
1886         }
1887
1888         return IRQ_HANDLED;
1889 }
1890
1891 static struct irqaction omap24xx_dma_irq = {
1892         .name = "DMA",
1893         .handler = omap2_dma_irq_handler,
1894         .flags = IRQF_DISABLED
1895 };
1896
1897 #else
1898 static struct irqaction omap24xx_dma_irq;
1899 #endif
1900
1901 /*----------------------------------------------------------------------------*/
1902
1903 static struct lcd_dma_info {
1904         spinlock_t lock;
1905         int reserved;
1906         void (*callback)(u16 status, void *data);
1907         void *cb_data;
1908
1909         int active;
1910         unsigned long addr, size;
1911         int rotate, data_type, xres, yres;
1912         int vxres;
1913         int mirror;
1914         int xscale, yscale;
1915         int ext_ctrl;
1916         int src_port;
1917         int single_transfer;
1918 } lcd_dma;
1919
1920 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1921                          int data_type)
1922 {
1923         lcd_dma.addr = addr;
1924         lcd_dma.data_type = data_type;
1925         lcd_dma.xres = fb_xres;
1926         lcd_dma.yres = fb_yres;
1927 }
1928 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1929
1930 void omap_set_lcd_dma_src_port(int port)
1931 {
1932         lcd_dma.src_port = port;
1933 }
1934
1935 void omap_set_lcd_dma_ext_controller(int external)
1936 {
1937         lcd_dma.ext_ctrl = external;
1938 }
1939 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1940
1941 void omap_set_lcd_dma_single_transfer(int single)
1942 {
1943         lcd_dma.single_transfer = single;
1944 }
1945 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1946
1947 void omap_set_lcd_dma_b1_rotation(int rotate)
1948 {
1949         if (omap_dma_in_1510_mode()) {
1950                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1951                 BUG();
1952                 return;
1953         }
1954         lcd_dma.rotate = rotate;
1955 }
1956 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1957
1958 void omap_set_lcd_dma_b1_mirror(int mirror)
1959 {
1960         if (omap_dma_in_1510_mode()) {
1961                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1962                 BUG();
1963         }
1964         lcd_dma.mirror = mirror;
1965 }
1966 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1967
1968 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1969 {
1970         if (omap_dma_in_1510_mode()) {
1971                 printk(KERN_ERR "DMA virtual resulotion is not supported "
1972                                 "in 1510 mode\n");
1973                 BUG();
1974         }
1975         lcd_dma.vxres = vxres;
1976 }
1977 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1978
1979 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1980 {
1981         if (omap_dma_in_1510_mode()) {
1982                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
1983                 BUG();
1984         }
1985         lcd_dma.xscale = xscale;
1986         lcd_dma.yscale = yscale;
1987 }
1988 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1989
1990 static void set_b1_regs(void)
1991 {
1992         unsigned long top, bottom;
1993         int es;
1994         u16 w;
1995         unsigned long en, fn;
1996         long ei, fi;
1997         unsigned long vxres;
1998         unsigned int xscale, yscale;
1999
2000         switch (lcd_dma.data_type) {
2001         case OMAP_DMA_DATA_TYPE_S8:
2002                 es = 1;
2003                 break;
2004         case OMAP_DMA_DATA_TYPE_S16:
2005                 es = 2;
2006                 break;
2007         case OMAP_DMA_DATA_TYPE_S32:
2008                 es = 4;
2009                 break;
2010         default:
2011                 BUG();
2012                 return;
2013         }
2014
2015         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2016         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2017         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2018         BUG_ON(vxres < lcd_dma.xres);
2019
2020 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2021                 ((y) * vxres * yscale + (x) * xscale) * es)
2022 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2023
2024         switch (lcd_dma.rotate) {
2025         case 0:
2026                 if (!lcd_dma.mirror) {
2027                         top = PIXADDR(0, 0);
2028                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2029                         /* 1510 DMA requires the bottom address to be 2 more
2030                          * than the actual last memory access location. */
2031                         if (omap_dma_in_1510_mode() &&
2032                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2033                                         bottom += 2;
2034                         ei = PIXSTEP(0, 0, 1, 0);
2035                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2036                 } else {
2037                         top = PIXADDR(lcd_dma.xres - 1, 0);
2038                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2039                         ei = PIXSTEP(1, 0, 0, 0);
2040                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2041                 }
2042                 en = lcd_dma.xres;
2043                 fn = lcd_dma.yres;
2044                 break;
2045         case 90:
2046                 if (!lcd_dma.mirror) {
2047                         top = PIXADDR(0, lcd_dma.yres - 1);
2048                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2049                         ei = PIXSTEP(0, 1, 0, 0);
2050                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2051                 } else {
2052                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2053                         bottom = PIXADDR(0, 0);
2054                         ei = PIXSTEP(0, 1, 0, 0);
2055                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2056                 }
2057                 en = lcd_dma.yres;
2058                 fn = lcd_dma.xres;
2059                 break;
2060         case 180:
2061                 if (!lcd_dma.mirror) {
2062                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2063                         bottom = PIXADDR(0, 0);
2064                         ei = PIXSTEP(1, 0, 0, 0);
2065                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2066                 } else {
2067                         top = PIXADDR(0, lcd_dma.yres - 1);
2068                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2069                         ei = PIXSTEP(0, 0, 1, 0);
2070                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2071                 }
2072                 en = lcd_dma.xres;
2073                 fn = lcd_dma.yres;
2074                 break;
2075         case 270:
2076                 if (!lcd_dma.mirror) {
2077                         top = PIXADDR(lcd_dma.xres - 1, 0);
2078                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2079                         ei = PIXSTEP(0, 0, 0, 1);
2080                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2081                 } else {
2082                         top = PIXADDR(0, 0);
2083                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2084                         ei = PIXSTEP(0, 0, 0, 1);
2085                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2086                 }
2087                 en = lcd_dma.yres;
2088                 fn = lcd_dma.xres;
2089                 break;
2090         default:
2091                 BUG();
2092                 return; /* Suppress warning about uninitialized vars */
2093         }
2094
2095         if (omap_dma_in_1510_mode()) {
2096                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2097                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2098                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2099                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2100
2101                 return;
2102         }
2103
2104         /* 1610 regs */
2105         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2106         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2107         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2108         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2109
2110         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2111         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2112
2113         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2114         w &= ~0x03;
2115         w |= lcd_dma.data_type;
2116         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2117
2118         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2119         /* Always set the source port as SDRAM for now*/
2120         w &= ~(0x03 << 6);
2121         if (lcd_dma.callback != NULL)
2122                 w |= 1 << 1;            /* Block interrupt enable */
2123         else
2124                 w &= ~(1 << 1);
2125         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2126
2127         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2128               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2129                 return;
2130
2131         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2132         /* Set the double-indexed addressing mode */
2133         w |= (0x03 << 12);
2134         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2135
2136         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2137         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2138         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2139 }
2140
2141 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2142 {
2143         u16 w;
2144
2145         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2146         if (unlikely(!(w & (1 << 3)))) {
2147                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2148                 return IRQ_NONE;
2149         }
2150         /* Ack the IRQ */
2151         w |= (1 << 3);
2152         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2153         lcd_dma.active = 0;
2154         if (lcd_dma.callback != NULL)
2155                 lcd_dma.callback(w, lcd_dma.cb_data);
2156
2157         return IRQ_HANDLED;
2158 }
2159
2160 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2161                          void *data)
2162 {
2163         spin_lock_irq(&lcd_dma.lock);
2164         if (lcd_dma.reserved) {
2165                 spin_unlock_irq(&lcd_dma.lock);
2166                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2167                 BUG();
2168                 return -EBUSY;
2169         }
2170         lcd_dma.reserved = 1;
2171         spin_unlock_irq(&lcd_dma.lock);
2172         lcd_dma.callback = callback;
2173         lcd_dma.cb_data = data;
2174         lcd_dma.active = 0;
2175         lcd_dma.single_transfer = 0;
2176         lcd_dma.rotate = 0;
2177         lcd_dma.vxres = 0;
2178         lcd_dma.mirror = 0;
2179         lcd_dma.xscale = 0;
2180         lcd_dma.yscale = 0;
2181         lcd_dma.ext_ctrl = 0;
2182         lcd_dma.src_port = 0;
2183
2184         return 0;
2185 }
2186 EXPORT_SYMBOL(omap_request_lcd_dma);
2187
2188 void omap_free_lcd_dma(void)
2189 {
2190         spin_lock(&lcd_dma.lock);
2191         if (!lcd_dma.reserved) {
2192                 spin_unlock(&lcd_dma.lock);
2193                 printk(KERN_ERR "LCD DMA is not reserved\n");
2194                 BUG();
2195                 return;
2196         }
2197         if (!enable_1510_mode)
2198                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2199                             OMAP1610_DMA_LCD_CCR);
2200         lcd_dma.reserved = 0;
2201         spin_unlock(&lcd_dma.lock);
2202 }
2203 EXPORT_SYMBOL(omap_free_lcd_dma);
2204
2205 void omap_enable_lcd_dma(void)
2206 {
2207         u16 w;
2208
2209         /*
2210          * Set the Enable bit only if an external controller is
2211          * connected. Otherwise the OMAP internal controller will
2212          * start the transfer when it gets enabled.
2213          */
2214         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2215                 return;
2216
2217         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2218         w |= 1 << 8;
2219         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2220
2221         lcd_dma.active = 1;
2222
2223         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2224         w |= 1 << 7;
2225         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2226 }
2227 EXPORT_SYMBOL(omap_enable_lcd_dma);
2228
2229 void omap_setup_lcd_dma(void)
2230 {
2231         BUG_ON(lcd_dma.active);
2232         if (!enable_1510_mode) {
2233                 /* Set some reasonable defaults */
2234                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2235                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2236                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2237         }
2238         set_b1_regs();
2239         if (!enable_1510_mode) {
2240                 u16 w;
2241
2242                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2243                 /*
2244                  * If DMA was already active set the end_prog bit to have
2245                  * the programmed register set loaded into the active
2246                  * register set.
2247                  */
2248                 w |= 1 << 11;           /* End_prog */
2249                 if (!lcd_dma.single_transfer)
2250                         w |= (3 << 8);  /* Auto_init, repeat */
2251                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2252         }
2253 }
2254 EXPORT_SYMBOL(omap_setup_lcd_dma);
2255
2256 void omap_stop_lcd_dma(void)
2257 {
2258         u16 w;
2259
2260         lcd_dma.active = 0;
2261         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2262                 return;
2263
2264         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2265         w &= ~(1 << 7);
2266         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2267
2268         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2269         w &= ~(1 << 8);
2270         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2271 }
2272 EXPORT_SYMBOL(omap_stop_lcd_dma);
2273
2274 /*----------------------------------------------------------------------------*/
2275
2276 static int __init omap_init_dma(void)
2277 {
2278         int ch, r;
2279
2280         if (cpu_class_is_omap1()) {
2281                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
2282                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2283         } else if (cpu_is_omap24xx()) {
2284                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
2285                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2286         } else if (cpu_is_omap34xx()) {
2287                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
2288                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2289         } else {
2290                 pr_err("DMA init failed for unsupported omap\n");
2291                 return -ENODEV;
2292         }
2293
2294         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2295                                 GFP_KERNEL);
2296         if (!dma_chan)
2297                 return -ENOMEM;
2298
2299         if (cpu_class_is_omap2()) {
2300                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2301                                                 dma_lch_count, GFP_KERNEL);
2302                 if (!dma_linked_lch) {
2303                         kfree(dma_chan);
2304                         return -ENOMEM;
2305                 }
2306         }
2307
2308         if (cpu_is_omap15xx()) {
2309                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2310                 dma_chan_count = 9;
2311                 enable_1510_mode = 1;
2312         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2313                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2314                        dma_read(HW_ID));
2315                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2316                        (dma_read(CAPS_0_U) << 16) |
2317                        dma_read(CAPS_0_L),
2318                        (dma_read(CAPS_1_U) << 16) |
2319                        dma_read(CAPS_1_L),
2320                        dma_read(CAPS_2), dma_read(CAPS_3),
2321                        dma_read(CAPS_4));
2322                 if (!enable_1510_mode) {
2323                         u16 w;
2324
2325                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2326                         w = dma_read(GSCR);
2327                         w |= 1 << 3;
2328                         dma_write(w, GSCR);
2329                         dma_chan_count = 16;
2330                 } else
2331                         dma_chan_count = 9;
2332                 if (cpu_is_omap16xx()) {
2333                         u16 w;
2334
2335                         /* this would prevent OMAP sleep */
2336                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2337                         w &= ~(1 << 8);
2338                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2339                 }
2340         } else if (cpu_class_is_omap2()) {
2341                 u8 revision = dma_read(REVISION) & 0xff;
2342                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2343                        revision >> 4, revision & 0xf);
2344                 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2345         } else {
2346                 dma_chan_count = 0;
2347                 return 0;
2348         }
2349
2350         spin_lock_init(&lcd_dma.lock);
2351         spin_lock_init(&dma_chan_lock);
2352
2353         for (ch = 0; ch < dma_chan_count; ch++) {
2354                 omap_clear_dma(ch);
2355                 dma_chan[ch].dev_id = -1;
2356                 dma_chan[ch].next_lch = -1;
2357
2358                 if (ch >= 6 && enable_1510_mode)
2359                         continue;
2360
2361                 if (cpu_class_is_omap1()) {
2362                         /*
2363                          * request_irq() doesn't like dev_id (ie. ch) being
2364                          * zero, so we have to kludge around this.
2365                          */
2366                         r = request_irq(omap1_dma_irq[ch],
2367                                         omap1_dma_irq_handler, 0, "DMA",
2368                                         (void *) (ch + 1));
2369                         if (r != 0) {
2370                                 int i;
2371
2372                                 printk(KERN_ERR "unable to request IRQ %d "
2373                                        "for DMA (error %d)\n",
2374                                        omap1_dma_irq[ch], r);
2375                                 for (i = 0; i < ch; i++)
2376                                         free_irq(omap1_dma_irq[i],
2377                                                  (void *) (i + 1));
2378                                 return r;
2379                         }
2380                 }
2381         }
2382
2383         if (cpu_is_omap2430() || cpu_is_omap34xx())
2384                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2385                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2386
2387         if (cpu_class_is_omap2())
2388                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2389
2390         /* FIXME: Update LCD DMA to work on 24xx */
2391         if (cpu_class_is_omap1()) {
2392                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2393                                 "LCD DMA", NULL);
2394                 if (r != 0) {
2395                         int i;
2396
2397                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2398                                "(error %d)\n", r);
2399                         for (i = 0; i < dma_chan_count; i++)
2400                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2401                         return r;
2402                 }
2403         }
2404
2405         return 0;
2406 }
2407
2408 arch_initcall(omap_init_dma);
2409
2410