2 * arch/arm/plat-nomadik/include/plat/ste_dma40.h
4 * Copyright (C) ST-Ericsson 2007-2010
5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Per Friden <per.friden@stericsson.com>
7 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
14 #include <linux/dmaengine.h>
15 #include <linux/workqueue.h>
16 #include <linux/interrupt.h>
17 #include <linux/dmaengine.h>
19 /* dev types for memcpy */
20 #define STEDMA40_DEV_DST_MEMORY (-1)
21 #define STEDMA40_DEV_SRC_MEMORY (-1)
24 * Description of bitfields of channel_type variable is available in
29 #define STEDMA40_INFO_PRIO_TYPE_POS 2
30 #define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS)
31 #define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS)
34 #define STEDMA40_INFO_CH_MODE_TYPE_POS 6
35 #define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS)
36 #define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS)
37 #define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS)
40 #define STEDMA40_INFO_CH_MODE_OPT_POS 8
41 #define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
42 #define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
43 #define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
44 #define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
45 #define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
46 #define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
49 #define STEDMA40_INFO_TIM_POS 10
50 #define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)
51 #define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)
53 /* End of channel_type configuration */
55 #define STEDMA40_ESIZE_8_BIT 0x0
56 #define STEDMA40_ESIZE_16_BIT 0x1
57 #define STEDMA40_ESIZE_32_BIT 0x2
58 #define STEDMA40_ESIZE_64_BIT 0x3
60 /* The value 4 indicates that PEN-reg shall be set to 0 */
61 #define STEDMA40_PSIZE_PHY_1 0x4
62 #define STEDMA40_PSIZE_PHY_2 0x0
63 #define STEDMA40_PSIZE_PHY_4 0x1
64 #define STEDMA40_PSIZE_PHY_8 0x2
65 #define STEDMA40_PSIZE_PHY_16 0x3
68 * The number of elements differ in logical and
71 #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
72 #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
73 #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
74 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
76 enum stedma40_flow_ctrl {
77 STEDMA40_NO_FLOW_CTRL,
81 enum stedma40_endianess {
82 STEDMA40_LITTLE_ENDIAN,
86 enum stedma40_periph_data_width {
87 STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
88 STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
89 STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
90 STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
93 struct stedma40_half_channel_info {
94 enum stedma40_endianess endianess;
95 enum stedma40_periph_data_width data_width;
97 enum stedma40_flow_ctrl flow_ctrl;
100 enum stedma40_xfer_dir {
102 STEDMA40_MEM_TO_PERIPH,
103 STEDMA40_PERIPH_TO_MEM,
104 STEDMA40_PERIPH_TO_PERIPH
109 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
111 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
112 * @channel_type: priority, mode, mode options and interrupt configuration.
113 * @src_dev_type: Src device type
114 * @dst_dev_type: Dst device type
115 * @src_info: Parameters for dst half channel
116 * @dst_info: Parameters for dst half channel
117 * @pre_transfer_data: Data to be passed on to the pre_transfer() function.
118 * @pre_transfer: Callback used if needed before preparation of transfer.
119 * Only called if device is set. size of bytes to transfer
120 * (in case of multiple element transfer size is size of the first element).
123 * This structure has to be filled by the client drivers.
124 * It is recommended to do all dma configurations for clients in the machine.
127 struct stedma40_chan_cfg {
128 enum stedma40_xfer_dir dir;
129 unsigned int channel_type;
132 struct stedma40_half_channel_info src_info;
133 struct stedma40_half_channel_info dst_info;
134 void *pre_transfer_data;
135 int (*pre_transfer) (struct dma_chan *chan,
141 * struct stedma40_platform_data - Configuration struct for the dma device.
143 * @dev_len: length of dev_tx and dev_rx
144 * @dev_tx: mapping between destination event line and io address
145 * @dev_rx: mapping between source event line and io address
146 * @memcpy: list of memcpy event lines
147 * @memcpy_len: length of memcpy
148 * @memcpy_conf_phy: default configuration of physical channel memcpy
149 * @memcpy_conf_log: default configuration of logical channel memcpy
150 * @llis_per_log: number of max linked list items per logical channel
151 * @disabled_channels: A vector, ending with -1, that marks physical channels
152 * that are for different reasons not available for the driver.
154 struct stedma40_platform_data {
156 const dma_addr_t *dev_tx;
157 const dma_addr_t *dev_rx;
160 struct stedma40_chan_cfg *memcpy_conf_phy;
161 struct stedma40_chan_cfg *memcpy_conf_log;
162 unsigned int llis_per_log;
163 int disabled_channels[8];
167 * setdma40_set_psize() - Used for changing the package size of an
168 * already configured dma channel.
170 * @chan: dmaengine handle
171 * @src_psize: new package side for src. (STEDMA40_PSIZE*)
172 * @src_psize: new package side for dst. (STEDMA40_PSIZE*)
174 * returns 0 on ok, otherwise negative error number.
176 int stedma40_set_psize(struct dma_chan *chan,
181 * stedma40_filter() - Provides stedma40_chan_cfg to the
182 * ste_dma40 dma driver via the dmaengine framework.
183 * does some checking of what's provided.
185 * Never directly called by client. It used by dmaengine.
186 * @chan: dmaengine handle.
187 * @data: Must be of type: struct stedma40_chan_cfg and is
188 * the configuration of the framework.
193 bool stedma40_filter(struct dma_chan *chan, void *data);
196 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
197 * scattergatter lists.
199 * @chan: dmaengine handle
200 * @sgl_dst: Destination scatter list
201 * @sgl_src: Source scatter list
202 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
203 * and each element must match the corresponding element in the other scatter
205 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
208 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
209 struct scatterlist *sgl_dst,
210 struct scatterlist *sgl_src,
211 unsigned int sgl_len,
212 unsigned long flags);
215 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
218 * @chan: dmaengine handle
219 * @addr: source or destination physicall address.
220 * @size: bytes to transfer
221 * @direction: direction of transfer
222 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
226 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
229 enum dma_data_direction direction,
232 struct scatterlist sg;
233 sg_init_table(&sg, 1);
234 sg.dma_address = addr;
237 return chan->device->device_prep_slave_sg(chan, &sg, 1,