2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/errno.h>
19 #include <asm/mach/irq.h>
20 #include <asm/exception.h>
22 #include <mach/hardware.h>
23 #include <mach/common.h>
25 #include "irq-common.h"
28 *****************************************
30 *****************************************
33 #define TZIC_INTCNTL 0x0000 /* Control register */
34 #define TZIC_INTTYPE 0x0004 /* Controller Type register */
35 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
36 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
37 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
38 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
39 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
40 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
41 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
42 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
43 #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
44 #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
45 #define TZIC_PND0 0x0D00 /* Pending Register 0 */
46 #define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */
47 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
48 #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
49 #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
51 void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
53 #define TZIC_NUM_IRQS 128
56 static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
58 unsigned int index, mask, value;
61 if (unlikely(index >= 4))
63 mask = 1U << (irq & 0x1F);
65 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
68 __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
73 #define tzic_set_irq_fiq NULL
76 static unsigned int *wakeup_intr[4];
78 static struct mxc_extra_irq tzic_extra_irq = {
80 .set_irq_fiq = tzic_set_irq_fiq,
84 static __init void tzic_init_gc(unsigned int irq_start)
86 struct irq_chip_generic *gc;
87 struct irq_chip_type *ct;
88 int idx = irq_start >> 5;
90 gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
92 gc->private = &tzic_extra_irq;
93 gc->wake_enabled = IRQ_MSK(32);
94 wakeup_intr[idx] = &gc->wake_active;
97 ct->chip.irq_mask = irq_gc_mask_disable_reg;
98 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
99 ct->chip.irq_set_wake = irq_gc_set_wake;
100 ct->regs.disable = TZIC_ENCLEAR0(idx);
101 ct->regs.enable = TZIC_ENSET0(idx);
103 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
106 asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
109 int i, irqofs, handled;
114 for (i = 0; i < 4; i++) {
115 stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
116 __raw_readl(tzic_base + TZIC_INTSEC0(i));
120 irqofs = fls(stat) - 1;
121 handle_IRQ(irqofs + i * 32, regs);
122 stat &= ~(1 << irqofs);
129 * This function initializes the TZIC hardware and disables all the
130 * interrupts. It registers the interrupt enable and disable functions
131 * to the kernel for each interrupt source.
133 void __init tzic_init_irq(void __iomem *irqbase)
138 /* put the TZIC into the reset value with
139 * all interrupts disabled
141 i = __raw_readl(tzic_base + TZIC_INTCNTL);
143 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
144 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
145 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
147 for (i = 0; i < 4; i++)
148 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
150 /* disable all interrupts */
151 for (i = 0; i < 4; i++)
152 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
154 /* all IRQ no FIQ Warning :: No selection */
156 for (i = 0; i < TZIC_NUM_IRQS; i += 32)
164 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
168 * tzic_enable_wake() - enable wakeup interrupt
170 * @param is_idle 1 if called in idle loop (ENSET0 register);
171 * 0 to be used when called from low power entry
172 * @return 0 if successful; non-zero otherwise
174 int tzic_enable_wake(int is_idle)
178 __raw_writel(1, tzic_base + TZIC_DSMINT);
179 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
182 for (i = 0; i < 4; i++) {
183 v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
185 __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));